CN208690259U - Semiconductor capacitor - Google Patents
Semiconductor capacitor Download PDFInfo
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- CN208690259U CN208690259U CN201821285583.7U CN201821285583U CN208690259U CN 208690259 U CN208690259 U CN 208690259U CN 201821285583 U CN201821285583 U CN 201821285583U CN 208690259 U CN208690259 U CN 208690259U
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- Prior art keywords
- layer
- grid conducting
- conducting layer
- film thickness
- semiconductor capacitor
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Abstract
The utility model provides a kind of semiconductor capacitor; include array layer; the array is laminated to be provided with spaced multiple grid conducting layers; the grid conducting layer protective layer for protecting the grid conducting layer is equipped on the grid conducting layer; the utility model is by keeping the grid conducting layer protective layer thickness of the grid conducting layer to stablize, to ensure product wafer yield.
Description
Technical field
The utility model relates to semiconductor integrated circuit reservoir technical field, in particular to memory subassembly device construction and
Process more particularly to a kind of semiconductor capacitor.
Background technique
Due to low-pressure chemical vapor deposition (Low pressure chemical vapor deposition, referred to as:
LPCVD) silicon nitride boiler tube board 100 can deposit a part of silicon nitride in daily deposition film in cassette 110, interior quartz ampoule
On 102 and outer quartz ampoule 101 etc. components (parts), as Fig. 1 is painted 100 schematic diagram of silicon nitride boiler tube board.With processing
(Run) the batch number of goods is more and more, and the film remained on parts can be more and more, can be easy to fall on wafer from
And generate micronic dust (particle).Under normal circumstances, lpcvd silicon nitride boiler tube will do it the period certainly after Run to quantitative batch
Dynamic striping maintenance (AUTO CLN).AUTO CLN is by being passed through the corrosive gas such as fluorine gas to the film remained on parts
Corroded, thus make remaining film largely fall off from parts and by remove (Purge) and etc. be sent into factory service end.
Since the film on the parts such as the cassette 110 of lpcvd silicon nitride boiler tube, interior quartz ampoule 102 and outer quartz ampoule 101 is in AUTO
It is disposed of after CLN, so board can compensate a part of film of deposition to these parts when depositing again after AUTO CLN
On.As the batch number of Run gradually increases, the film being deposited on the parts such as cassette and inside and outside quartz ampoule is gradually saturated, and is needed
Compensating can be fewer and fewer to the film on these parts, and the film deposited on wafer can be more and more.
Can be compensated when being deposited again after AUTO CLN due to lpcvd silicon nitride board a part of film of deposition to cassette with
On the parts such as inside and outside quartz ampoule, and as the batch number of Run gradually increases, the film being deposited on these parts is gradually satisfied
With needing to compensate can be fewer and fewer to the film on these parts.So, within the same AUTO CLN period, identical
Under the conditions of Run goods, the film thickness of the first Run batch can reduce much compared to the film thickness before AUTO CLN after AUTO CLN, and with
The increase of Run goods batch number, the film thickness of deposition it is increasing.But it after the film saturation deposited on parts, deposits to
Film thickness on wafer is basically unchanged, as shown in Figure 2.This phenomenon becomes larger with film thickness (target) of Run goods processing procedure
And it is more obvious.Grid conducting layer protective layer (PG GATE SIN layer) be diffusion silicon nitride processing procedure in film thickness target most
Big processing procedure (film thickness target is 1800 angstroms), so this phenomenon is particularly evident.
As shown in figure 3, working as grid conducting layer protective layer 503 (PG GATE SIN layer, Si3N4Layer) deposition thickness mistake
When big, (the SiO that SNC OX layer, SOD mode is formed of storage node contacts oxide skin(coating) 504 then deposited will lead to2
Layer) SiO of array 501 (Array) overlying regions is retained in after planarization (CMP)2Layer is blocked up.When the memory node left connects
When the thickness of touching oxide skin(coating) 504 is excessive, in then etching storage node contacts oxide skin(coating) 504 and the composite layer above it
When 505 (oxide, carbon, SION etc..), due to the limitation of etching machine technique, the layer that causes to be etched cannot be etched
Completely, and then cause storage node contacts (SNC) layer 506 (Poly and metal etc ...) then deposited cannot be with
The contact of the region Array, exists and leaves filled layer H1, operation element is made to fail.And when the thickness of the deposition of grid conducting layer protective layer 503
Hour is spent, the storage node contacts oxide skin(coating) then deposited is will lead to and is retained in Array overlying regions after planarization
SiO2Layer can be very few, the channel length after composite layer so as to cause subsequent etching storage node contacts oxide skin(coating) and above it
Become smaller, and then it is small to spend the storage node contacts thickness of deposition, grid conducting layer and metal interlevel distance K1 are too small, cause to deposit
Metal 507 and the coupling effect of grid conducting layer 502 above storage node contact layer is excessive, device performance is influenced, such as Fig. 4 institute
Show.So the stability of 503 film thickness of grid conducting layer protective layer is for guaranteeing that product yield plays very important work
With.
Utility model content
The technical problem to be solved by the utility model is to provide a kind of semiconductor capacitors, reduce due to grid conducting layer
Protective layer film thickness stability is poor and leads to the risk of product wafer defect, ensures product wafer yield.To realize above-mentioned technology mesh
, the specific technical solution that the utility model is taken are as follows: a kind of semiconductor capacitor includes array layer, the array layer one
Face is provided with spaced multiple grid conducting layers, and the grid for protecting the grid conducting layer are equipped on the grid conducting layer
Pole conductive layer protective layer.
As the improved technical solution of the utility model, the thickness of the grid conducting layer protective layer between 1770 angstroms~
1830 angstroms.
As the improved technical solution of the utility model, the grid conducting layer protection interlayer is additionally provided with filled layer.
As the improved technical solution of the utility model, the filled layer is another relative to the grid conducting layer protective layer
The storage node contacts layer there are two arranged in parallel is set on one side.
As the improved technical solution of the utility model, the storage node contacts layer is relative to the another of the array layer
Face is equipped with metal layer.
As the improved technical solution of the utility model, the metal interlevel is equipped with metallic spacer.
As the improved technical solution of the utility model, the metallic spacer material includes silicon nitride.
As the improved technical solution of the utility model, the material of the grid conducting layer protective layer includes silicon nitride.
Beneficial effect
The utility model is to be provided with spaced multiple Gate Electrode Conductives the array is laminated comprising array layer
Layer is equipped with the grid conducting layer protective layer for protecting the grid conducting layer on the grid conducting layer, by keeping the grid
The grid conducting layer protective layer thickness of pole conductive layer is stablized, to ensure product wafer yield.
Detailed description of the invention
Fig. 1 is painted silicon nitride boiler tube board schematic diagram in the utility model embodiment.
Fig. 2 is painted in the utility model embodiment the film of grid conducting layer protective layer different disposal batch number under the same terms
It is thick.
Fig. 3 is painted in the utility model embodiment causes wafer to generate defect when grid conducting layer protective layer thickness is excessive
Process schematic.
Fig. 4 is painted in the utility model embodiment causes wafer to generate defect when grid conducting layer protective layer thickness is too small
Process schematic.
Fig. 5 is painted the flow diagram of semiconductor capacitor operating method in the utility model embodiment.
Fig. 6 is painted the film thickness compensation schematic diagram of grid conducting layer protective layer different batches number under the same terms.
Fig. 7 is painted to be protected using wafer grid conductive layer after the batch control device improved in the utility model embodiment
Sheath deposition process schematic diagram.
Fig. 8 is painted in the utility model embodiment using grid conducting layer protection tunic when improved batch control device
Thick tendency chart.
Fig. 9 is painted the process flow chart of semiconductor capacitor operating method in the utility model embodiment.
Figure 10 is painted semiconductor capacitor structure schematic diagram in the utility model embodiment.
In figure, 100, nitride deposition boiler tube board；101, outer quartz ampoule；102, interior quartz ampoule；110, cassette；200, certainly
Dynamic striping driving device；201, start button；202, end key；300, batch control device；301, preset value processing unit；302,
Offset processing unit；400, film thickness setting device；500, wafer；501, array layer；502, grid conducting layer；503, grid is led
Protection of electrical lay-er layer；504, filled layer；505, composite layer；506, storage node contacts layer；507, metal layer；508, metal is isolated
Layer；H1, filled layer is left；K1, grid conducting layer and metal interlevel distance；Cn, film thickness value；The difference of Dn, film thickness；F (x), connect
Reforwarding row offset.
Specific embodiment
To keep the purpose and technical solution of the utility model embodiment clearer, implement below in conjunction with the utility model
The technical solution of the utility model is clearly and completely described in example.Obviously, described embodiment is the utility model
A part of the embodiment, instead of all the embodiments.Based on described the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained under the premise of being not necessarily to creative work, belongs to the model of the utility model protection
It encloses.
Those skilled in the art of the present technique are appreciated that unless otherwise defined, all terms used herein (including technology art
Language and scientific term) there is meaning identical with the general understanding of those of ordinary skill in the utility model fields.Also
It should be understood that those terms such as defined in the general dictionary should be understood that have in the context of the prior art
The consistent meaning of meaning will not be explained in an idealized or overly formal meaning and unless defined as here.
Embodiment 1
The utility model provides a kind of semiconductor capacitor, as shown in Figure 10, is painted in the utility model embodiment and partly leads
Bulk capacitor structural schematic diagram, includes array layer 501, and the array layer 501 is provided with spaced multiple grids on one side and leads
Electric layer 502 is equipped with the grid conducting layer protective layer 503 for protecting the grid conducting layer 502 on the grid conducting layer 502,
In the present embodiment, the thickness of the grid conducting layer protective layer 503 is between 1770 angstroms~1830 angstroms.The grid conducting layer protection
It is additionally provided with filled layer 504 between layer 503, the filled layer 504 is equipped with relative to the another side of the grid conducting layer protective layer 503
The storage node contacts layer 506 of two arranged in parallel, the storage node contacts layer 506 are another relative to the array layer 501
It is equipped with metal layer 507 on one side, is equipped with metallic spacer 508 between the metal layer 507, in the present embodiment, the metallic spacer
508 materials include silicon nitride, and the material of the grid conducting layer protective layer 503 includes silicon nitride.
Grid conducting layer protective layer film thickness tendency chart when being painted batch processed after the utility model improves such as Fig. 8, by institute
The grid conducting layer protective layer film thickness on wafer 500 is stated to be held essentially constant between 1770 angstroms~1830 angstroms, so as to avoid
500 product defects of wafer substantially increase the yield of 500 product of wafer.
How the utility model obtains method such as Fig. 9 of grid conducting layer protective layer in homogeneous thickness in specific implementation process
It is shown, it is painted the process flow chart of the utility model method, is specifically comprised the following steps:
S1, a kind of equipment for improving grid conducting layer protective layer film thickness stability is provided, the equipment includes that silicon nitride is heavy
Product boiler tube board 100, automatic striping driving device 200, batch control device 300 and film thickness setting device 400, the silicon nitride
Deposition boiler tube board 100 is used to make the processing procedure of grid conducting layer deposition protective layer；The automatic striping driving device 200 connects
The nitride deposition boiler tube board 100, for driving the nitride deposition boiler tube board 100, to execute the silicon nitride
The film accumulated on 100 inner part of deposition boiler tube board automatically removes；It is equipped at preset value in the batch control device 300
Unit 301 and offset processing unit 302 are managed, the preset value processing unit 301 is used to set the default ginseng of handled batch
Numerical value (default)；The offset processing unit 302 is used to set the numeration offset of handled batch；The numeration is mended
It repays value and is matched in the same automatic striping period corresponding batch and preceding a batch when the batch control device 300 is not used
Secondary film thickness deviation (Offset (1st~2nd)), the numeration offset correspond to the batch order compensation of the processing batch
Correct the preset parameter value (default)；The film thickness setting device 400 is used to collect each nitride deposition boiler tube
The thickness of the film that each processing procedure deposits within an automatic striping period of board 100 simultaneously sets film thickness targets value；S1 step packet
Include: Xiang Suoshu nitride deposition boiler tube board 100 is loaded into the cassette 110 that wafer 500 is housed；Open the batch control device
300；Film thickness targets value in the preset value processing unit 301 is set in the batch control device 300；
S2, as shown in figure 5, depict the operating process schematic diagram of the utility model method, control and fill via the batch
The 300 drivings nitride deposition boiler tube board 100 is set, to carry out silicon nitride deposition process, including carries out first batch processing,
The film thickness value that film thickness setting device 400 detects described in first batch after treatment is C1；Progress second lot processing, second
The film thickness value that the film thickness setting device 400 detects after batch processed is C2；Until carrying out the n-th batch processed, n-th batch
The film thickness value that film thickness setting device 400 detects described in secondary after treatment is Cn.
S3, the film thickness value detected after n-th batch processed reach the film thickness targets value, and automatic activation is described certainly
Trigger assembly 201 in dynamic striping driving device 200, enables the nitride deposition boiler tube board 100 start automatic striping；When certainly
After dynamic striping, stop component 202 in automatic striping driving device 200 described in automatic trigger, it is heavy to close the silicon nitride
Product boiler tube board 100 removes membrane operations automatically, while making batch count value auto zero, and make the automatic striping driving device
Automatic striping information is fed back to the batch control device 300 by 200, to carry out the first batch processing of step S2；
The number that the offset processing unit 302 in S4, the batch control device 300 will be collected by step S3
According to being handled, difference D1, D2, D3 ... Dn of film thickness after the batch processed of front and back are converted into continuous operation offset f (x) simultaneously
The preset parameter value of the batch corresponding to invocation step S2 after order compensating approach is the preset parameter value when batch processed,
Wherein x=1,1,2,3,4 ... n-1, n are positive integer, when the nitride deposition boiler tube board 100 processing to second lot or
The preset parameter value added and subtracted the corresponding continuous operation offset automatically when different batches after second lot and work as batch processed,
To carry out the second lot or second lot post-processing of step S2.
Specifically, being shown in Table 1, it is shown as 100 different time of nitride deposition boiler tube board and different location film thickness value
And offset.
1 nitride deposition boiler tube board different time of table and different location film thickness value and film thickness deviation
The numerical value of other test points other than the test point of middle part as can be seen from Table 1, film thickness deviation 1 is maximum,
This is because silicon nitride film is all clear on all parts in the nitride deposition boiler tube board 100 after carrying out automatic striping
When removing, then the first batch after film thickness being gone to handle automatically, the wafer 500 deposits the grid conducting layer protective layer 503,
The grid conducting layer protective layer 503 deposited in the present embodiment is silicon nitride film, and having should much sink at this time
It accumulates in the nitride deposition on the wafer 500 to the nitride deposition boiler tube board 100 on all parts, so as to cause
The silicon nitride film film thickness deposited on the wafer 500 sharply declines, as shown in Fig. 2, depicting the crystalline substance under the same terms
The film thickness of the 503 different disposal batch number of the grid conducting layer protective layer deposited on circle 500, the grid conducting layer protective layer
For 503 film thickness between 1570 angstroms~1830 angstroms, film thickness is extremely unstable.When carrying out second lot processing, at this time by being nitrogenized
Deposited partial nitridation silicon thin film on 100 all parts of siliceous deposits boiler tube board, will not largely attract the silicon nitride after
It is continuous to be deposited on 100 all parts of nitride deposition boiler tube board, so that depositing to the nitridation on the wafer 500
Silicon thin film also becomes more, until deposit on 100 all parts of nitride deposition boiler tube board silicon nitride film saturation,
The silicon nitride film thickness deposited on the wafer 500 no longer changes.
Specifically, the utility model connects the batch control device 300 in the automatic striping driving device 200,
With the variation of automatic 200 runing time of striping driving device, product on 100 inner part of nitride deposition boiler tube board
Tired film thickness is gradually increased, these film thickness numerical value can all be collected into film thickness setting device 400 and be handled, data that treated
Can be transferred to the offset processing unit 302, realize inverse compensation automatically, namely other than the test point of middle part other are same
One test point, when first batch is handled after the automatic striping of the nitride deposition boiler tube board 100, the film thickness recompensed is inclined
Difference 1 is maximum, carries out the film thickness deviation 1 when the film thickness deviation 2 when second lot processing is less than first batch processing, carries out
Film thickness deviation 3 when third batch processed is less than the film thickness deviation 2 when first batch is handled, and middle part test point is due to film
It is thick invariable, therefore film thickness deviation is always zero.Make the grid conducting layer being eventually deposited on the wafer 500 in this way
The protective layer film thickness of deposition is uniform and stable, is able to maintain substantially between 1770 angstroms~1830 angstroms, so as to guarantee the wafer 500
Product yield, as Fig. 7 is painted wafer grid conductive layer protective layer after the batch control device improved using the utility model
Deposition process schematic diagram, grid conducting layer protective layer film thickness tendency chart when being painted batch processed after the utility model improves such as Fig. 8.
The above is only the embodiments of the present invention, and the description thereof is more specific and detailed, but can not therefore understand
For a limitation on the scope of the patent of the present invention.It should be pointed out that for those of ordinary skill in the art, not taking off
Under the premise of from the utility model design, various modifications and improvements can be made, these belong to the protection of the utility model
Range.
Claims (8)
- Include array layer 1. a kind of semiconductor capacitor, which is characterized in that the array is laminated be provided with it is spaced more A grid conducting layer is equipped with the grid conducting layer protective layer for protecting the grid conducting layer on the grid conducting layer.
- 2. semiconductor capacitor according to claim 1, which is characterized in that the thickness of the grid conducting layer protective layer is situated between In 1770 angstroms~1830 angstroms.
- 3. semiconductor capacitor according to claim 1, which is characterized in that the grid conducting layer protection interlayer is additionally provided with Filled layer.
- 4. semiconductor capacitor according to claim 3, which is characterized in that the filled layer is relative to the Gate Electrode Conductive The another side of layer protective layer sets the storage node contacts layer there are two arranged in parallel.
- 5. semiconductor capacitor according to claim 4, which is characterized in that the storage node contacts layer is relative to described The another side of array layer is equipped with metal layer.
- 6. semiconductor capacitor according to claim 5, which is characterized in that the metal interlevel is equipped with metallic spacer.
- 7. semiconductor capacitor according to claim 6, which is characterized in that the metallic spacer material includes nitridation Silicon.
- 8. semiconductor capacitor according to claim 1 to 4, which is characterized in that the grid conducting layer protective layer Material includes silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821285583.7U CN208690259U (en) | 2018-08-10 | 2018-08-10 | Semiconductor capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821285583.7U CN208690259U (en) | 2018-08-10 | 2018-08-10 | Semiconductor capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208690259U true CN208690259U (en) | 2019-04-02 |
Family
ID=65884523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821285583.7U Active CN208690259U (en) | 2018-08-10 | 2018-08-10 | Semiconductor capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208690259U (en) |
-
2018
- 2018-08-10 CN CN201821285583.7U patent/CN208690259U/en active Active
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