CN208399916U - A kind of height emulating instrument for radio altimeter - Google Patents
A kind of height emulating instrument for radio altimeter Download PDFInfo
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- CN208399916U CN208399916U CN201820859370.4U CN201820859370U CN208399916U CN 208399916 U CN208399916 U CN 208399916U CN 201820859370 U CN201820859370 U CN 201820859370U CN 208399916 U CN208399916 U CN 208399916U
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Abstract
The utility model discloses a kind of height emulating instruments for radio altimeter, including low-converter, analog-digital converter, the digital time delayer based on FPGA, digital analog converter and upconverter, the signal output end of the low-converter is connect by analog-digital converter with the signal input part of the digital time delayer based on FPGA, and the signal output end of the digital time delayer based on FPGA is connected by digital analog converter and the signal input part of upconverter.The utility model is used based on the digital time delayer that FPGA is realized come instead of physical delay line employed in traditional equipment, cost is not only greatly reduced, equipment volume is reduced and mitigates weight of equipment, and since the utility model is the delay process for realizing digital signal based on FPGA, therefore, the precision of delay is higher.The utility model is widely portable in various radio altitude simulation systems as a kind of height emulating instrument for radio altimeter.
Description
Technical field
The utility model relates to signal simulation instrument more particularly to a kind of height emulating instruments for radio altimeter.
Background technique
Technology word is explained:
FPGA:Field-Programmable Gate Array, i.e. field programmable gate array.
LO:Local Oscillator, i.e. local oscillator.
Low-converter: radiofrequency signal is mixed in frequency mixer with local oscillation signal, then retains difference frequency letter by filter
Number, to realize that radiofrequency signal downconverts to the device of intermediate frequency or baseband signal.
Upconverter: baseband signal and local oscillation signal are mixed in frequency mixer, then retain mixing letter by filter
Number, to realize the device of intermediate frequency or baseband signal up-conversion to radiofrequency signal.
Analog signal: being sampled into the device of digital signal by analog-digital converter (ADC), according to the sample rate of setting to simulation
Signal is sampled, and each sampled point is converted into N bit, and N is determined by the vertical resolution of converter, such as 12 moulds
Number converter is then converted into 12 bits, and 16 analog-digital converters are then converted into 16 bits.
Digital analog converter (DAC): by digital signal samples at the device of analog signal, turned according to the turnover rate of setting
It changes, is converted into an analog voltage signal per N number of binary number, and N is determined by the vertical resolution of converter, such as 12 digit moulds
Converter is then that every 12 binary numbers are converted into an analog voltage；16 digit mode converters are then by every 16 two
System number is converted into an analog voltage.
Radio altimeter is one of modern aircraft various electronic, and the reality on ground is left for survey aircraft
Highly, it is in one of the important equipment into guarantee aircraft safety in close and landing mission.Currently, radio altimeter has frequency modulation
Constant amplitude formula (FMCW), constant difference frequency modulation frequency constant amplitude formula, pulsed (PULSE) and this 4 kinds of modes of pulse compression come realize height
Measurement, but the basic principle of this 4 kinds of modes is the same, is returned from aircraft to ground, then by ground using radio wave
Aircraft realizes elevation carrection to measure the time of its experience, specific as shown in Figure 1.Due to the spread speed C of radio wave
It is fixed and known, therefore the time of radio wave experience is directly proportional to tested height H, specifically, is tested the calculating of height H
Formula are as follows: H=C*t/2；Wherein, the time interval measured needed for t is expressed as.
In the test and process fault detection of radio altimeter, height emulator is needed to simulate the height of aircraft
The altitude range of degree, commonly required simulation is 0~762m (civil aircraft) or 0~6000m (military secret), reaches as high as 12000m.Mesh
Before, emulator mainly uses delay line delay to realize the simulation of height, since the delay of delay line is fixed and invariable, because
This will realize the simulation of full-height range, it is necessary to be realized using the delay line combination of more different sizes, and delay line combines
It is realized by RF switch, specific implementation principle is as shown in Figure 2.As it can be seen that the delay line and switch of existing height emulator
Quantity is very more, then leads to that equipment cost is high, volume is big, weight is big, upgrading not convenient for safeguarding in this way.
Utility model content
In order to solve the above-mentioned technical problem, the purpose of the utility model is to provide a kind of height for radio altimeter
Emulating instrument can reach and reduce cost, reduces equipment volume and mitigate the purpose of weight of equipment.
The technical scheme adopted by the utility model is a kind of height emulating instrument for radio altimeter, including under
Frequency converter, analog-digital converter, the digital time delayer based on FPGA, digital analog converter and upconverter, the letter of the low-converter
Number output end is connect by analog-digital converter with the signal input part of the digital time delayer based on FPGA, the number based on FPGA
The signal output end of word delayer is connected by digital analog converter and the signal input part of upconverter.
Further, described to be realized based on the digital time delayer of FPGA using shift register.
Further, further include governor circuit, the enable end of the governor circuit and the digital time delayer based on FPGA and when
The connection of clock end.
Further, the digital time delayer based on FPGA includes several first d type flip flops, several described the first D
The signal output end of previous first d type flip flop in trigger is connect with the signal input part of the first d type flip flop of the latter；Institute
The signal for stating the signal output end and first the first d type flip flop in several described first d type flip flops of analog-digital converter is defeated
Enter end connection, the signal output end of most one the first d type flip flop in several described first d type flip flops and digital analog converter
Signal input part connection；
The enable end of several first d type flip flops and clock end are connect with governor circuit.
It further, further include access selection circuit, the digital time delayer based on FPGA includes several the 2nd D triggering
Device, the signal output end and the second d type flip flop of the latter of previous second d type flip flop in several described second d type flip flops
Signal input part connection；First in the signal output end of the analog-digital converter and several described second d type flip flops
The signal input part of second d type flip flop connects, and the signal output end of several second d type flip flops selects electricity by access
The connection of the signal input part of road and digital analog converter；
The enable end of several second d type flip flops and clock end are connect with governor circuit.
Further, the access selection circuit is switching circuit or data selector；The control of the data selector
End is connect with governor circuit.
Further, the switching circuit is electric-controlled switch circuit；The control terminal and governor circuit of the electric-controlled switch circuit
Connection.
Further, the governor circuit is also connected with display screen and power panel.
Further, the governor circuit includes mainboard and CPU, the mainboard respectively with CPU, display screen, power panel and
The enable end of digital time delayer based on FPGA is connected with clock end.
Further, the display screen is touch screen.
The beneficial effects of the utility model are: the height emulating instrument of the utility model include low-converter, analog-digital converter,
Digital time delayer, digital analog converter and upconverter based on FPGA, and the signal output end of the low-converter passes through modulus
Converter is connect with the signal input part of the digital time delayer based on FPGA, and the signal of the digital time delayer based on FPGA is defeated
Outlet is connected by digital analog converter and the signal input part of upconverter, it is seen then that the utility model uses real based on FPGA
Existing digital time delayer not only to greatly reduce cost, reduction is set instead of physical delay line employed in traditional equipment
Standby volume and mitigation weight of equipment, and since the utility model is the delay process for realizing digital signal based on FPGA, because
This, the precision of delay is higher.
Detailed description of the invention
Fig. 1 is the operation principle schematic diagram of radio altimeter；
Fig. 2 is the structural schematic diagram of present level emulator；
Fig. 3 is that a kind of first specific embodiment structure of the height emulating instrument for radio altimeter of the utility model is shown
It is intended to；
Fig. 4 is that a kind of second specific embodiment structure of the height emulating instrument for radio altimeter of the utility model is shown
It is intended to；
Fig. 5 is a specific embodiment structural schematic diagram of the digital time delayer based on FPGA；
Fig. 6 is the first specific embodiment structural schematic diagram of access selection circuit；
Fig. 7 is the second specific embodiment structural schematic diagram of access selection circuit；
Fig. 8 is the third specific embodiment structural schematic diagram of access selection circuit.
1, switching circuit.
Specific embodiment
The utility model is described in further detail in the following with reference to the drawings and specific embodiments.
As shown in figure 3, a kind of height emulating instrument for radio altimeter, including low-converter, analog-digital converter, base
In the digital time delayer, digital analog converter and upconverter of FPGA, the signal output end of the low-converter passes through analog-to-digital conversion
Device is connect with the signal input part of the digital time delayer based on FPGA, the signal output end of the digital time delayer based on FPGA
It is connected by digital analog converter and the signal input part of upconverter.
For above-mentioned height emulating instrument, concrete operating principle are as follows: the low-converter receives radio altimeter hair
After the radiofrequency signal of injection, down-converted is carried out to the radiofrequency signal received, to obtain analog baseband signal, and will simulation
Baseband signal is exported to analog-digital converter；After the analog-digital converter receives analog baseband signal, to analog baseband signal into
Row analog-to-digital conversion process to be converted to digital baseband signal, and digital baseband signal is exported to the number based on FPGA and is prolonged
When device；It is described delay process is carried out to the digital baseband signal that receives based on the digital time delayer of FPGA after exported again to digital-to-analogue
Converter；Digital baseband signal after delay is carried out digital-to-analogue conversion processing by the digital analog converter, corresponding to be converted to
Analog baseband signal, and analog baseband signal is exported to upconverter；The upconverter by digital analog converter to being transmitted
Analog baseband signal carries out upconversion process, to obtain corresponding radiofrequency signal, and this radiofrequency signal is exported to radio height
The receiving end of table is spent, such radio altimeter just can be based on the radiofrequency signal launched and the radiofrequency signal received, to survey
The delay of signal is measured, and height is calculated according to the linear relationship between height and signal delay, to realize altitude simulation.
As it can be seen that the height emulating instrument of the utility model is applicable to all types of radio altimeters, and the utility model uses
Physical delay line employed in traditional equipment is substituted based on the digital time delayer that FPGA is realized, is not only greatly reduced into
Originally, reduce equipment volume and mitigate weight of equipment, and realize the delay process of digital baseband signal based on FPGA, therefore phase
Compared with the analog signal delay process (as shown in Figure 2) of traditional equipment, the delay precision of the utility model is higher.
It is further used as the preferred embodiment of the present embodiment, the digital time delayer based on FPGA uses shift LD
Device is realized.In the present embodiment, due to realizing the digital time delayer using shift register, using shifting
The clock end of bit register inputs different clock signals to shift register, just can control digital time delayer realize it is different
Delay time achievees the effect that delay is controllable, and operation ease, flexibility are higher；Also, using shift register to realize
Digital time delayer is stated, can reach the simple effect of circuitry.For example, the corresponding height of 1ns is Hpn=300000000m/s*
1ns/2=0.15m/ns, then, according to the height of required emulation, to input corresponding clock signal, digital time delayer is enabled to prolong
When corresponding time, be just able to achieve the emulation of desired height in this way.
Specifically, it is supplied to the clock signal of shift register, it can be by electronics such as computer, host computer, governor circuits
Equipment/electronic circuit provides.
Be further used as the preferred embodiment of the present embodiment, further include governor circuit, the governor circuit be based on
The enable end of the digital time delayer of FPGA is connected with clock end.As it can be seen that in the present embodiment, using governor circuit for the number
Word delayer provides enable signal and/or clock signal, the small product size of height emulating instrument can be enabled smaller in this way, saves equipment pendulum
Between emptying.
It is further used as the preferred embodiment of the present embodiment, as shown in figure 4, the governor circuit is also connected with display screen
And power panel；The governor circuit includes mainboard and CPU, the mainboard respectively with CPU, display screen, power panel and be based on
The enable end of the digital time delayer of FPGA is connected with clock end.Wherein, the display screen is preferably touch screen；The power panel pair
It is main board power supply after the 28V direct current of access carries out respective handling.
It is further used as the preferred embodiment of the present embodiment, for the above-mentioned digital time delayer based on FPGA, can be had
Two kinds of preferred embodiments, it is specific as follows shown.
1, the first preferred embodiment of the digital time delayer based on FPGA
As shown in figure 5, the digital time delayer based on FPGA includes the first shift register, first shift LD
Device includes several first d type flip flops, the signal output of previous first d type flip flop in several described first d type flip flops
End is connect with the signal input part of the first d type flip flop of the latter, i.e., several first d type flip flops are connected in series, and (n-1)th first
The signal output end of d type flip flop is connect with the signal input part of n-th of first d type flip flops；The signal of the analog-digital converter is defeated
Outlet is connect with the signal input part of first the first d type flip flop in several described first d type flip flops, it is described several
The signal output end of most one the first d type flip flop in one d type flip flop and the signal input part of digital analog converter connect；
The enable end of several first d type flip flops and clock end are connect with governor circuit.Specifically, described several
The enable end of a first d type flip flop and clock end are connect with mainboard.Wherein, n 1,2,3 ..., N, N is the first d type flip flop
Total number.
It, can be by enabling the number of the first d type flip flop different for the above-mentioned digital time delayer based on FPGA, and/or enable
The clock cycle for being input to the clock signal of the clock end CLK of the first d type flip flop is different, to realize the digital time delayer
Delay adjustment control, to meet the requirement of different height emulation.
2, the second preferred embodiment of the digital time delayer based on FPGA
The height emulating instrument of the utility model further includes access selection circuit, and the digital time delayer based on FPGA includes
Second shift register, second shift register include several second d type flip flops, several described second d type flip flops
In the signal output end of previous second d type flip flop connect with the signal input part of the second d type flip flop of the latter, i.e., several
Second d type flip flop is connected in series, and the signal output end of (n-1)th the second d type flip flop and the signal of n-th of second d type flip flops are defeated
Enter end connection；First the 2nd D in the signal output end of the analog-digital converter and several described second d type flip flops is triggered
The signal input part of device connects, and the signal output end of several second d type flip flops passes through access selection circuit and digital-to-analogue
The signal input part of converter connects；
The enable end of several second d type flip flops and clock end are connect with governor circuit.Specifically, described several
The enable end of a second d type flip flop and clock end are connect with mainboard.Wherein, n 1,2,3 ..., N, N is the second d type flip flop
Total number.
For the above-mentioned digital time delayer based on FPGA, digital baseband signal can be selected to pass through by access selection circuit
It is exported after crossing how many second d type flip flops, to realize the difference of signal delay, for example, N number of second d type flip flop is shared, at this point,
It needs to enable digital baseband signal by preceding N-2 the second d type flip flops, to realize corresponding delay, at this point, then selecting N-2
The signal that the signal output end of second d type flip flop is exported is exported to the signal input part of digital analog converter, that is, gates N-2
Carry out data transmission between the signal output end of second d type flip flop and the signal input part of digital analog converter；And/or it can pass through
Enable the clock cycle for the clock signal of clock end CLK for being input to the second d type flip flop different, to realize the digital time delayer
Delay adjust control, with meet different height emulation requirement.
In a preferred embodiment, the access selection circuit is switching circuit 1；Specifically, as shown in fig. 6, for opening
Powered-down road 1, may particularly include several first switches, if at this point, the signal output end of several second d type flip flops with
One end of dry first switch connects one to one respectively, and the other end of several first switches is then and digital-to-analogue conversion
The signal input part of device connects, in this way, when needing to enable digital baseband signal by preceding N-2 the second d type flip flops, to realize correspondence
Delay, at this point, the first switch closure that the signal output end that N-2 the second d type flip flops then may be selected is connected.It can
See, the control of delay time can be realized by switching circuit 1.Similarly, as shown in fig. 7, for the switching circuit 1,
May particularly include a multi-channel switch, wherein multi-channel switch includes several normally opened contacts and a normally-closed contact,
Signal output end of several the described normally opened contacts respectively with several the second d type flip flops connects one to one, and one
Normally-closed contact is then connect with the signal input part of digital analog converter, in this way when needing to enable digital analog converter and some the 2nd D to touch
When sending out device connection, then the switch in multi-channel switch is enabled to connect with corresponding normally opened contact.
In a preferred embodiment, flexibility is operated conveniently in order to improve, the switching circuit 1 is preferably electric-controlled switch electricity
Road or the access selection circuit are preferably data selector (as shown in Figure 8)；Mainboard and electricity in the governor circuit
Control the control terminal of switching circuit or the control terminal connection of data selector.At this point, the mainboard can be according to the setting of input
Parameter, so that the control terminal of electric-controlled switch circuit or the control terminal of data selector are output control signals to, to realize data
The selection of access.Wherein, for the setting parameter of the input, user can be inputted by equipment such as keyboard, touch screens；The electricity
Controlling switching circuit can be electric magnetic switch.
In a preferred embodiment, the data selector chip that model 74LS151 can be used in the data selector comes
It realizes.
It is obtained by above-mentioned, the height emulating instrument for radio altimeter a kind of for the utility model, by using
The physical delay line in traditional equipment is replaced based on the digital time delayer of FPGA, is not only greatly reduced cost, is reduced equipment
Volume and mitigation weight of equipment, and since low-converter, analog-digital converter, base is utilized in the height emulating instrument of the utility model
In the digital time delayer, digital analog converter and upconverter of FPGA, the radiofrequency signal of radio altimeter transmitting is successively carried out
Down-converted, analog-to-digital conversion process, digital signal delay process, digital-to-analogue conversion processing and upconversion process, i.e., with number
Signal processing means come realize signal be delayed, can be improved the precision and reliable and stable degree of delay in this way.As it can be seen that this is practical
Novel emulating instrument is applicable in the radio altitude simulation system of fixed wing aircraft, helicopter and other aircraft.
It is to be illustrated to the preferable implementation of the utility model, but the invention is not limited to the reality above
Example is applied, those skilled in the art can also make various equivalent changes without departing from the spirit of the present invention
Shape or replacement, these equivalent deformations or replacement are all included in the scope defined by the claims of the present application.
Claims (10)
1. a kind of height emulating instrument for radio altimeter, which is characterized in that including low-converter, analog-digital converter, base
In the digital time delayer, digital analog converter and upconverter of FPGA, the signal output end of the low-converter passes through analog-to-digital conversion
Device is connect with the signal input part of the digital time delayer based on FPGA, the signal output end of the digital time delayer based on FPGA
It is connected by digital analog converter and the signal input part of upconverter.
2. a kind of height emulating instrument for radio altimeter according to claim 1, which is characterized in that described to be based on
The digital time delayer of FPGA is realized using shift register.
3. a kind of height emulating instrument for radio altimeter according to claim 2, which is characterized in that further include master control
Circuit, the governor circuit are connect with the enable end of the digital time delayer based on FPGA and clock end.
4. a kind of height emulating instrument for radio altimeter according to claim 3, which is characterized in that described to be based on
The digital time delayer of FPGA includes several first d type flip flops, the previous first D touching in several described first d type flip flops
The signal output end of hair device is connect with the signal input part of the first d type flip flop of the latter；The signal of the analog-digital converter exports
End connect with the signal input part of first the first d type flip flop in several described first d type flip flops, it is described several first
The signal output end of most one the first d type flip flop in d type flip flop and the signal input part of digital analog converter connect；
The enable end of several first d type flip flops and clock end are connect with governor circuit.
5. a kind of height emulating instrument for radio altimeter according to claim 3, which is characterized in that further include access
Selection circuit, the digital time delayer based on FPGA include several second d type flip flops, several described second d type flip flops
In the signal output end of previous second d type flip flop connect with the signal input part of the second d type flip flop of the latter；The modulus
The signal input part of first the second d type flip flop in the signal output end of converter and several described second d type flip flops connects
It connects, the signal output end of several second d type flip flops passes through access selection circuit and the signal of digital analog converter inputs
End connection；l
The enable end of several second d type flip flops and clock end are connect with governor circuit.
6. a kind of height emulating instrument for radio altimeter according to claim 5, which is characterized in that the access choosing
Selecting circuit is switching circuit or data selector；The control terminal of the data selector is connect with governor circuit.
7. a kind of height emulating instrument for radio altimeter according to claim 6, which is characterized in that the switch electricity
Road is electric-controlled switch circuit；The control terminal of the electric-controlled switch circuit is connect with governor circuit.
8. a kind of height emulating instrument for radio altimeter according to claim 3, which is characterized in that the master control electricity
Road is also connected with display screen and power panel.
9. a kind of height emulating instrument for radio altimeter according to claim 8, which is characterized in that the master control electricity
Road includes mainboard and CPU, and the mainboard is enabled with CPU, display screen, power panel and digital time delayer based on FPGA respectively
End is connected with clock end.
10. a kind of height emulating instrument for radio altimeter according to claim 8, which is characterized in that the display
Screen is touch screen.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201820859370.4U CN208399916U (en) | 2018-06-04 | 2018-06-04 | A kind of height emulating instrument for radio altimeter |
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| CN201820859370.4U CN208399916U (en) | 2018-06-04 | 2018-06-04 | A kind of height emulating instrument for radio altimeter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115209433A (en) * | 2022-07-22 | 2022-10-18 | 大连市共进科技有限公司 | Base station high-frequency signal simulation method and device, terminal equipment and readable storage medium |
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2018
- 2018-06-04 CN CN201820859370.4U patent/CN208399916U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115209433A (en) * | 2022-07-22 | 2022-10-18 | 大连市共进科技有限公司 | Base station high-frequency signal simulation method and device, terminal equipment and readable storage medium |
| CN115209433B (en) * | 2022-07-22 | 2023-07-21 | 大连市共进科技有限公司 | Base station high-frequency signal simulation method, device, terminal equipment and readable storage medium |
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