CN208369547U - Digital signal detecting device, MIPI RFFE are from equipment and system - Google Patents
Digital signal detecting device, MIPI RFFE are from equipment and system Download PDFInfo
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- CN208369547U CN208369547U CN201820905915.0U CN201820905915U CN208369547U CN 208369547 U CN208369547 U CN 208369547U CN 201820905915 U CN201820905915 U CN 201820905915U CN 208369547 U CN208369547 U CN 208369547U
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Abstract
The utility model embodiment discloses digital signal detecting device, MIPI RFFE from equipment and system, and digital signal detecting device includes: two Acquisition Circuits and selection output circuit；The first input end of first Acquisition Circuit is connected with the second input terminal of the second Acquisition Circuit, and the second input terminal of the first Acquisition Circuit is connected with the first input end of the second Acquisition Circuit；The output end of two Acquisition Circuits is connected with the input terminal of selection output circuit；Acquisition Circuit receives signal using first input end and is acquired to the second input terminal reception signal, and whether verifying acquisition signal meets data-signal feature；Output circuit is selected, the selection output acquisition signal in received acquisition signal and invalid signals.Various abnormal conditions have been fully taken into account by the slave equipment of MIPI RFFE that digital signal detecting device constructs, can effectively solve the problems, such as in MIPI RFFE system two identical MIPI RFFE from the bus collision of equipment.
Description
Technical field
The utility model embodiment is related to computer hardware technology more particularly to a kind of digital signal detecting device, MIPI
RFFE is from equipment and MIPI RFFE system.
Background technique
With the continuous development of technology, people to radio-frequency front-end equipment (such as power amplifier, active antenna tuner,
Low-noise amplifier and duplexer etc.) demand be continuously increased, for device manufacturer, control all radio-frequency front-ends and set
Standby will be very huge challenge.MIPI (Mobile Industry Processor Interface, mobile Industry Processor
Interface) alliance be RFFE (RF Front-End.Radio-frequency front-end) equipment formulation standard, a set of be used for multiple headend equipments is provided
The bus interface connected thus can easily control these RFFE equipment with radio frequency chip.
A kind of schematic diagram of MIPI RFFE system in the prior art is shown in fig 1 a.As shown in Figure 1a, MIPI
RFFE standard defines a kind of interface in RFFE equipment room, can be with one main equipment of carry, while most in single RFFE bus
More carries 15 (are illustrated only in Fig. 1 a from equipment 1 and from equipment 2) from equipment.The bus use two signal lines, one
It is the clock cable (SCLK) controlled by host, another is mono-/bis-to data line (SDATA), is coupled in RFFE bus
Each RFFE from equipment can by USID (Unique Slave ID, from device identifier), PID (PRODUCT_ID,
Product identifiers) or the identity signal such as MfrlID (MANUFACTURER_ID, manufacturer identifier) it is identified.
It shows in Figure 1b in the prior art, the waveform diagram of signal is transmitted on SCLK and SDATA.As shown in Figure 1 b,
The upper each frame data of SDATA are all started by a SSC (Sequence Start Condition, sequence start condition) signal,
Clock signal is not transmitted on this when SCLK.After SSC signal, and then just transmission command frame (command frame),
Preceding 4 bits (bit) of command frame are SA signals, for matching identification information of the RFFE from equipment.If
One RFFE matches the SA signal from equipment, then knows that above-mentioned command frame is that RFFE main equipment is initiated for oneself
Operation.
But when two USID, PID and MfrlID from equipment are all the same, MIPI RFFE main equipment then can not area
Divide above-mentioned two from equipment.In view of the above technical problems, the prior art gives a solution, as illustrated in figure 1 c, when two
When a MIPI RFFE is identical from equipment (from equipment 1 and from equipment 2), main equipment will be connected to from the SCLK of equipment 1
SCLK, SDATA are connected to the SDATA of main equipment；The SDATA of main equipment will be connected to from the SCLK of equipment 2, SDATA is connected to main equipment
SCLK.It is each whether mutual come the SCLK and SDATA for perceiving itself by detecting SSC signal in receiving signal from equipment
It changes, and then programming again can be carried out to the identity characteristic information of itself, distinguish two in MIPI RFFE system to realize
A identical MIPI RFFE is from equipment.
In the process of implementing the utility model, the discovery prior art has following defects that the prior art is logical to inventor
SSC is crossed to detect whether SCLK and SDATA is exchanged, if bus occurs jagged or indefinite state when powering on and makes SSC
Signal is distorted, then is difficult to ensure the accuracy to SCLK and SDATA identification.Deficiency is considered to abnormal conditions, identification is accurate
It is poor to spend.
Utility model content
In view of this, the utility model embodiment provide a kind of digital signal detecting device, MIPI RFFE from equipment and
MIPI RFFE system mentions while identical MIPI RFFE is from the bus collision of equipment in solving the problems, such as MIPI RFFE system
The high identification accuracy and reliability of entire MIPI RFFE system.
In a first aspect, the utility model embodiment provides a kind of digital signal detecting device, comprising: circuit structure is identical
Two Acquisition Circuits and selection output circuit；
Wherein, the first input end of first Acquisition Circuit is connected with the second input terminal of second Acquisition Circuit, and first
Second input terminal of a Acquisition Circuit is connected with the first input end of second Acquisition Circuit；The output end of two Acquisition Circuits point
It is not connected with two input terminals of the selection output circuit；
The Acquisition Circuit, for using first input end received signal as clock to the received letter of the second input terminal
It number is acquired, and the characteristics of whether acquisition signal meets data-signal is verified, if so, the acquisition signal is exported, it is otherwise, defeated
Invalid signals are set out；
The selection output circuit, in received acquisition signal and invalid signals, selection to export the acquisition
Signal is as the data-signal.
Second aspect, the utility model embodiment additionally provide a kind of MIPI RFFE from equipment, comprising: as this is practical new
Digital signal detecting device described in type any embodiment, the first equipment input terminal, the second equipment input terminal and data-signal
Processing unit；
The first of any of the first equipment input terminal and the digital signal detecting device target Acquisition Circuit is defeated
Enter end to be connected；The second equipment input terminal is connected with the second input terminal of the target Acquisition Circuit；At the data-signal
Unit is managed, is connected with selection output circuit described in the digital signal detecting device；
The first equipment input terminal, for receiving clock signal or data-signal；
The second equipment input terminal, for receiving data signal or clock signal；
The digital signal detecting device, for defeated in the first equipment input terminal and the second equipment input terminal
Correct data-signal is selected to be sent to the data signal processing unit in the signal entered；
The data signal processing unit, for handling the received data-signal；
Wherein, it is prestored in the data signal processing unit matched from device address from equipment with the MIPI RFFE.
The third aspect, the utility model embodiment additionally provide a kind of MIPI RFFE system, comprising: MIPI RFFE master sets
Standby, two MIPI RFFE as described in the utility model any embodiment are from equipment；First MIPI RFFE from equipment and
Two equipment of the identical type that second MIPI RFFE is produced from equipment for same manufacturer；
Wherein, the clock end of the MIPI RFFE main equipment is respectively with first MIPI RFFE from the first of equipment
The the second equipment input terminal of equipment input terminal and second MIPI RFFE from the device is connected, the MIPI RFFE
The data terminal of main equipment is respectively with first MIPI RFFE from the second equipment input terminal of equipment and second described
The the first equipment input terminal of MIPI RFFE from the device is connected；Each MIPI RFFE is prestored from the file register of equipment
Have different from device address.
The utility model embodiment is by using identical two Acquisition Circuits of circuit structure and selection output circuit structure
Digital signal detecting device is made, by by two input terminal interconnections of above-mentioned two Acquisition Circuit, may be implemented when input
Into two input signals of above-mentioned digital signal detecting device, one is clock signal, when another is data-signal, two
Acquisition Circuit uses respective first input end received signal to carry out as clock to the second input terminal received signal respectively
Acquisition respectively exports corresponding signal extremely according to verification result after the characteristics of whether verifying acquisition signal meets data-signal
Output circuit is selected, no matter how two input signals that may be implemented to be input to digital signal detecting device adopt with above-mentioned two
Collector be connected, the selection output circuit can accurately outputting data signals effect, according to above-mentioned detection of data signal
Device, for corresponding construction MIPI RFFE after equipment, the MIPI RFFE constructed has fully taken into account various abnormal feelings from equipment
Condition, and then two identical MIPI RFFE can accurately, be reliably solved in MIPI RFFE system from the bus of equipment
Collision problem.
Detailed description of the invention
Fig. 1 a is a kind of schematic diagram of MIPI RFFE system in the prior art；
Fig. 1 b is the waveform diagram that signal is transmitted on a kind of SCLK and SDATA in the prior art；
Fig. 1 c is a kind of schematic diagram of MIPI RFFE system for solving bus collision in the prior art；
Fig. 2 a is a kind of structure chart for digital signal detecting device that the utility model embodiment one provides；
Fig. 2 b is the structural representation of the Acquisition Circuit in the digital signal detecting device that the utility model embodiment one provides
Figure；
Fig. 3 a is a kind of MIPI RFFE that provides of the utility model embodiment two from the structural schematic diagram of equipment；
Fig. 3 b is the MIPI RFFE that provides of the utility model embodiment two from the concrete structure schematic diagram of equipment；
Fig. 3 c is that a kind of structure of the Acquisition Circuit of the MIPI RFFE of the offer of the utility model embodiment two from the device is shown
It is intended to；
Fig. 4 is a kind of structural schematic diagram for MIPI RFFE system that the utility model embodiment three provides.
Specific embodiment
The utility model is described in further detail with reference to the accompanying drawings and examples.It is understood that herein
Described specific embodiment is used only for explaining the utility model, rather than the restriction to the utility model.It further needs exist for
It is bright, part relevant to the utility model is illustrated only for ease of description, in attached drawing rather than entire infrastructure.
Embodiment one
Fig. 2 a is a kind of structure chart for digital signal detecting device that the utility model embodiment one provides, such as Fig. 2 a institute
Show, the digital signal detecting device includes: identical two Acquisition Circuits (the first Acquisition Circuit in such as 2a of circuit structure
110 and second Acquisition Circuit 120) and selection output circuit 130；
Wherein, the second input terminal phase of the first input end of first Acquisition Circuit 110 and second Acquisition Circuit 120
Even, the second input terminal of first Acquisition Circuit 130 is connected with the first input end of second Acquisition Circuit 120；Two acquisitions
The output end of circuit is connected with two input terminals of the selection output circuit 130 respectively；
The Acquisition Circuit (the first Acquisition Circuit 110 or the second Acquisition Circuit 120), for being connect using first input end
The signal of receipts is acquired the second input terminal received signal as clock, and verifies whether acquisition signal meets data-signal
The characteristics of, if so, the acquisition signal is exported, and otherwise, output setting invalid signals；
The selection output circuit 130, for being adopted described in selection output in received acquisition signal and invalid signals
Collect signal as the data-signal.
As shown in Figure 2 a, there are two input terminal and an output end, above-mentioned two inputs for digital signal detecting device tool
End is connected with the first end of the first Acquisition Circuit 110 and second end respectively, and defeated with the second of the second Acquisition Circuit 120 respectively
Enter end and first input end is connected, the output end of digital signal detecting device is the output end for selecting output circuit 130.
Wherein, the function of digital signal detecting device is clock signal for the two paths of signals in input all the way, and another way is
When data-signal, no matter what above-mentioned clock signal and data-signal were specifically inputted from which input terminal, selection output electricity
Lu Junneng is effectively exported data-signal.Specific implementation is that two Acquisition Circuits use respective first respectively
Data terminal receives signal and is acquired as clock to the second input terminal received signal, it is to be understood that only one is adopted
Collector can correctly acquire out the data-signal, and another way then can not correctly acquire the data-signal.Later, respectively
Acquisition Circuit respectively verifies whether the acquisition signal oneself collected meets data-signal feature, such as: it whether include specific
Whether the check results of the combination of data, parity check bit accurate, or whether meet data-signal signal characteristic (for example,
Average-power-range etc.), likewise, only one Acquisition Circuit can determine that its acquisition signal collected meets data-signal
Feature, and the acquisition signal is accordingly exported, another Acquisition Circuit then can determine whether that its acquisition signal collected does not meet number
According to signal characteristic, and accordingly output setting invalid signals.Correspondingly, as long as setting selection output circuit 130 receives at the same time
When acquiring signal and invalid signals, the difference of the two can be correctly differentiated, can accordingly export the acquisition signal as institute
State data-signal.
It is understood that those skilled in the art can the logic that realized according to Acquisition Circuit, patrolled using various
Volume device (for example, NAND gate perhaps comparator etc.) is overlapped out the Acquisition Circuit or can directly be compiled using FPGA or DSP etc.
Journey logical device realizes above-mentioned Acquisition Circuit, and the present embodiment is to this and is not limited.
In an optional embodiment of the present embodiment, the invalid signals are full low level signal；Correspondingly, institute
State select output circuit can for or gate device, described or gate device be used for input be the acquisition signal and it is described entirely it is low
When level signal, the acquisition signal is exported.
It in the present embodiment, is the data-signal for setting the data frame of data bits, the utility model for data type
Embodiment gives a kind of structural schematic diagram of Acquisition Circuit.Wherein, the utility model embodiment one is shown in figure 2b to mention
The structural schematic diagram of Acquisition Circuit in the digital signal detecting device of confession.
As shown in Figure 2 b, the Acquisition Circuit, specifically includes: the matched shift LD of data bits with the data frame
Device 1001, counter 1002, data-signal judging unit 1003 and with gate device 1004；
The input end of clock of the shift register 1001 is the first input end, and the signal of the shift register is defeated
Entering end is second input terminal, each register of the shift register 1001 (register 1, register 2 in Fig. 2 b ...,
The output end of register n) is connected with the input terminal of the data-signal judging unit respectively；The input terminal of the counter 1002
It is connected with the input end of clock of the shift register 1001, the output end and the data-signal of the counter 1002 judge
The input terminal of unit 1003 is connected, and the acquisition signal output end of the data-signal judging unit 1003 judges that position exports with effective
End is connected with described with two input terminals of gate device 1004 respectively, and the output end with gate device 1004 is Acquisition Circuit
Output end；
The shift register 1001, for acquire with the matched acquisition signal of the data bits of the data frame, and will
The acquisition signal is sent to the data-signal judging unit 1003；
The counter 1002, for being judged to the data-signal when counting up to the data bits of the data frame
Unit 1003 sends instruction information；
The data-signal judging unit 1003, for when receiving the instruction information, by the shift register
The data group cooperation of each register storage is that the acquisition signal is exported to the acquisition signal output end, and verifies institute in 1001
Acquisition signal the characteristics of whether meeting data-signal is stated, and generates effective judgement position corresponding with verification result and exports to described and have
Effect judges position output end；
Described and gate device 1004, for exporting the result of effective judgement position and the acquisition signal phase with after.
In the present embodiment, the working principle of the Acquisition Circuit is as follows: if the first input end of Acquisition Circuit is correct
Accessed clock signal, the second input terminal of Acquisition Circuit has correctly accessed data-signal, then counter 1002 count
To data frame data bits (for example, 3bit, 5bit etc.) when, the data that are stored in each register in shift register 1001
Every data in the as described data frame.Correspondingly, when data-signal judging unit 1003 detects the counter 1002
When the instruction information of transmission, the data group cooperation that register each in the shift register 1001 can be stored is the acquisition
Signal, and the characteristics of whether the acquisition signal meets data-signal can be verified in turn, position is effectively judged accordingly to generate.Allusion quotation
Type, if the characteristics of acquisition signal meets data-signal, effective judgement position of high level signal can be accordingly exported,
If the characteristics of acquisition signal does not meet data-signal can accordingly export effective judgement position of low level signal.Phase
Answer, data-signal judging unit 1003 by will acquire signal and effectively judge position export to gate device 1004, can be with
It realizes and 1004 outputting data signals of gate device or full low level signal.
It should be noted that in the present embodiment, the number of the effective judgement position generated in data-signal judging unit 1003
Amount can be for 1 or multiple, and the acquisition signal exported in data-signal judging unit 1003 can may be for 1 tunnel
Multichannel (combination of multiple signals constitutes the data frames of a completion), correspondingly, the quantity with gate device 1004 can also be with
For 1 or multiple, those skilled in the art can targetedly design above-mentioned parameter according to the actual features of data-signal
Quantity and combination, the present embodiment is to this and is not limited.
The utility model embodiment is by using identical two Acquisition Circuits of circuit structure and selection output circuit structure
Digital signal detecting device is made, by by two input terminal interconnections of above-mentioned two Acquisition Circuit, may be implemented when input
Into two input signals of above-mentioned digital signal detecting device, one is clock signal, when another is data-signal, two
Acquisition Circuit uses respective first input end received signal to carry out as clock to the second input terminal received signal respectively
Acquisition, and the characteristics of whether acquisition signal meets data-signal is verified, and corresponding signal is respectively exported extremely according to verification result
Output circuit is selected, no matter how two input signals that may be implemented to be input to digital signal detecting device adopt with above-mentioned two
Collector be connected, the selection output circuit can accurately outputting data signals effect.
On the basis of the various embodiments described above, the Acquisition Circuit can also include: lock-in circuit；
The lock-in circuit, it is electric with effective judgement position output end of this Acquisition Circuit and another acquisition respectively
Road is connected；For locking described another in the effective judgement position output end output useful signal for determining this Acquisition Circuit
A Acquisition Circuit no longer works.
Typically, the lock-in circuit can be realized by trigger and/or latch.The benefit being arranged in this way is to prevent
Only clock signal interferes whole device with the signal generated middle all the way that data-signal is reversely connected, and improves the anti-of whole device
Interference performance.
Embodiment two
Fig. 3 a is a kind of MIPI RFFE that provides of the utility model embodiment two from equipment.As shown in Figure 3a, the MIPI
RFFE is from the digital signal detecting device 310 that equipment includes: as described in the utility model any embodiment, the first equipment input terminal
320, the second equipment input terminal 330 and data signal processing unit 340；
Any of the first equipment input terminal 320 and the digital signal detecting device 310 target Acquisition Circuit (example
Such as, such as the first Acquisition Circuit in 3a) first input end be connected；The second equipment input terminal 330 is acquired with the target
Second input terminal of circuit is connected；The data signal processing unit 340, and described in the digital signal detecting device 310
Output circuit is selected to be connected；
The first equipment input terminal 320, for receiving clock signal or data-signal；The second equipment input terminal
330, signal or clock signal for receiving data；
The digital signal detecting device 310, for defeated in the first equipment input terminal 320 and second equipment
Entering in the signal of 330 input of end selects correct data-signal to be sent to the data signal processing unit 340；
The data signal processing unit 340, for handling the received data-signal.
Typically, the first equipment input terminal 320 generally end SCLK of MIPI RFFE from the device, described second
The end SDATA of equipment input terminal 330, generally MIPI RFFE from the device.
In the present embodiment, give a kind of specific structure of MIPI RFFE from equipment, by MIPI RFFE from setting
The standby middle digital signal detecting device 310 using as described in the utility model any embodiment, can effectively solve MIPI RFFE
Bus collision problem of two identical MIPI RFFE from equipment in system.
Specifically, can in MIPI RFFE from two Acquisition Circuits in the digital signal detecting device 310 of equipment,
It is pre-configured with different from device address, and being configured in MIPI RFFE main equipment in advance can be according to above-mentioned two from setting
Two identical MIPI RFFE are distinguished from equipment in standby address.Correspondingly, in two equipment by two MIPI RFFE from equipment
When input terminal interconnection is on MIPI RFFE main equipment, each MIPI RFFE is from equipment according to can finally match
It can be with effective solution bus collision as respective from device address from device address.
Typically, as shown in Figure 1 b, MIPI RFFE is received from equipment, the data-signal that MIPI RFFE main equipment is sent
Specifically: 13 command frames, wherein the 0th~3 of the command frame is from device address, the 4-11 of the command frame
Position is RFFE order, and the 12nd of the command frame is parity check bit；
Correspondingly, the Acquisition Circuit in the digital signal detecting device 310, concrete configuration is at least one of following to verify
The characteristics of whether meeting data-signal:
Verify parity check bit in the command frame whether with the binary adds of preceding 12-bit data in the command frame and
As a result match；Verify whether the RFFE order in the command frame matches with the standard RFFE order prestored；And verifying
Whether matching from device address from device address with the standard prestored in the command frame；Wherein, different Acquisition Circuit
In prestore different standards from device address.
On the basis of the various embodiments described above, the data signal processing unit be can specifically include: Frame processes list
Member and state machine and file register；
The Frame processes unit and state machine, for receiving the RFFE order in the command frame, and to institute
RFFE order is stated to be handled；The file register, for from device address, and docking described in receiving in the command frame
The described of receipts is handled from device address.
Fig. 3 b is the MIPI RFFE of the offer of the utility model embodiment two from a kind of concrete structure schematic diagram of equipment, such as
It include a capture circuit in each Acquisition Circuit in digital signal detecting device shown in Fig. 3 b.Wherein the first acquisition electricity
The first end on road 3001 is connected with MIPI RFFE from the end SCLK (the first equipment input terminal) of equipment, second end and MIPI RFFE
It is connected from the end SDATA (the second equipment input terminal) of equipment, then one CLK of concrete configuration is captured in the first Acquisition Circuit 3001
DATA circuit and one and gate device；The first end of second Acquisition Circuit 3002 and MIPI RFFE are from the end SDATA of equipment
(the second equipment input terminal) is connected, and second end is connected with MIPI RFFE from the end SCLK (the first equipment input terminal) of equipment, then and the
One DATA of concrete configuration captures CLK circuit and one and gate device in two Acquisition Circuits 3002.Wherein, in the first acquisition electricity
It is pre-configured with usid1 in road 3001, is pre-configured with usid2 in the second Acquisition Circuit 2002.Wherein, CLK captures DATA circuit
It is identical with the DATA capture structure of CLK circuit, it is opposite only as the signal of clock and data.
Wherein, CLK captures DATA circuit, and using MIPI RFFE, the end SCLK received signal is adopted as clock from the device
Collect the end SDATA received signal, and removes the SA in matching acquisition signal using usid1；DATA captures CLK circuit: using MIPI
RFFE signal of the end the DATA received signal as clock acquisition CLK terminal from the device, and go matching to acquire using usid2
SA in signal.
Wherein, Partiy OK&Command valid contains the "AND" of two states altogether, namely: in acquisition signal
Whether parity check bit is accurate (Partiy OK), and whether the RFFE order in acquisition signal orders with the standard RFFE prestored
Order matches (Command valid), if two states are "Yes", can determine that signal collected is data-signal,
Correspondingly, Partiy OK&Command valid is high level.
In fact, SCLK and SDATA that MIPI RFFE main equipment is sent are determining.So two groups of Acquisition Circuits (
One Acquisition Circuit 3001 and the second Acquisition Circuit 3002) only one can export the height of Partiy OK&Command valid
Level.At this point it is possible to which assert the Acquisition Circuit output that output Partiy OK&Command valid is high level is effective
SCLK and SDATA, while the Acquisition Circuit sends out a Lock signal, the Acquisition Circuit of other mistake to being lock out, allows separately
One group of Acquisition Circuit no longer works.
Further, since two Acquisition Circuits can export respectively respective SCLK, SDATA, RFFE order collected with
And usidx (x=1 or 2) signal, after respectively carrying out with operation with Partiy OK&Command valid, Fig. 3 b
In two export with only one in door and door is useful signal, another and door export full low level signal.Later
By or gate device 3003, by after two output result phase "or" with door, output is exactly real SCLK, SDATA, RFFE
Order and usid signal.SCLK, SDATA, RFFE command signal can be sent into Frame processes unit and state machine later
3004, and usid is sent into file register 3005 so that MIPI RFFE from equipment determine itself from device identification
For above-mentioned usid, and can be for RFFE order execution corresponding operation.
In an optional embodiment of the present embodiment, by two acquisitions electricity in the digital signal detecting device
It is same that two clocks, the Frame processes unit in road and the clock in state machine and the file register carry out clock
Step.The benefit being arranged in this way is to guarantee foundation and the retention time of digital circuit.
As previously mentioned, being to set the data frame of data bits (hereinafter directly with 13 command frames in the data-signal
For) when, the Acquisition Circuit specifically includes: with the matched shift register of data bits of the data frame, counter,
Data-signal judging unit and and gate device.Wherein, Fig. 3 c be the utility model embodiment two provide MIPI RFFE from
A kind of structural schematic diagram of Acquisition Circuit in equipment.
Wherein it is possible to command frame completely be acquired by shift register, when counter counts have counted to 13 expression command frames
Acquisition terminates.Each SSC can reset counter and shift register.It may determine that odd even school after command frame, which acquires, to be completed
Test whether correct and order is effective.
Wherein, as shown in Figure 3c, the data-signal judging unit 3011 in the Acquisition Circuit has judged three kinds of logics altogether: life
Enable whether the parity check bit in frame matches (Parity with the binary add and result of preceding 12-bit data in the command frame
OK=(~^reg [12:1]==reg [0], the data that store in register 0 whether with stored in register 12- register 1
The binary add of data and the inverted value of result are consistent, if so, Parity OK is high level, otherwise Parity OK is low
Level)；Whether the RFFE order in command frame matches (Command_valid==reg with the standard RFFE order prestored
Whether the data stored in [8:1]==RFFE valid command, register 8- register 1 are that a RFFE effectively refers to
It enables, if so, Command_valid is high level, otherwise, Command_valid is low level)；And in command frame from
Device address whether match with the standard that prestores from device address (USID_match=reg [12:9]==USIDx [3:
0], whether the data stored in register 12- register 9 are consistent with the data stored in USIDx [3:0], if so,
USID_match is high level, and otherwise, USID_match is low level).
Correspondingly, by two and gate device, can finally respectively obtain Partiy OK&Command valid signal,
RFFE order and usidx signal.
The MIPI RFFE constructed by above-mentioned digital signal detecting device has fully taken into account various exceptions from equipment
Situation, and then accurate, reliably can determine data-signal in received two paths of signals and feed back corresponding usidx letter
Number so that MIPI RFFE from equipment use the usidx signal as itself from device address.
Embodiment three
Fig. 4 is a kind of structural schematic diagram for MIPI RFFE system that the utility model embodiment three provides.The MIPI
RFFE system includes: MIPI RFFE main equipment 401, the two MIPI RFFE as described in the utility model any embodiment from setting
Standby (that is: the first MIPI RFFE in Fig. 4 from equipment 402 and the 2nd MIPI RFFE from equipment 403), first MIPI
(the 2nd MIPI RFFE is from setting from equipment (the first MIPI RFFE from equipment 402) and second MIPI RFFE from equipment by RFFE
Two equipment (USID, PID and MfrlID are all the same) of the standby identical type 403) produced for same manufacturer；
Wherein, the clock end (SCLK) of the MIPI RFFE main equipment 401 is respectively with the first MIPI RFFE from equipment
First equipment input terminal (SCLK) and the 2nd MIPI RFFE are from second equipment input terminal (SDATA) phase in equipment 403
Even, the data terminal (SDATA) of the MIPI RFFE main equipment 401 is respectively with the first MIPI RFFE from the of equipment 402
Two equipment input terminals (SDATA) and the 2nd MIPI RFFE are from first equipment input terminal (SCLK) phase in equipment 403
Even.
By above-mentioned setting, two identical MIPI in MIPI RFFE system can accurately, be reliably solved
Bus collision problem of the RFFE from equipment.
Note that above are only the preferred embodiment and institute's application technology principle of the utility model.Those skilled in the art's meeting
Understand, the utility model is not limited to specific embodiment described here, is able to carry out for a person skilled in the art various bright
Aobvious variation, readjustment and substitution is without departing from the protection scope of the utility model.Therefore, although passing through above embodiments
The utility model is described in further detail, but the utility model is not limited only to above embodiments, is not departing from
It can also include more other equivalent embodiments in the case that the utility model is conceived, and the scope of the utility model is by appended
Scope of the claims determine.
Claims (9)
1. a kind of digital signal detecting device characterized by comprising identical two Acquisition Circuits of circuit structure and selection
Output circuit；
Wherein, the first input end of first Acquisition Circuit is connected with the second input terminal of second Acquisition Circuit, and first is adopted
Second input terminal of collector is connected with the first input end of second Acquisition Circuit；The output end of two Acquisition Circuits respectively with
Two input terminals of the selection output circuit are connected；
The Acquisition Circuit, for use first input end received signal as clock to the second input terminal received signal into
Row acquisition, and the characteristics of whether acquisition signal meets data-signal is verified, if so, exporting the acquisition signal, otherwise, output is set
Determine invalid signals；
The selection output circuit, in received acquisition signal and invalid signals, selection to export the acquisition signal
As the data-signal.
2. digital signal detecting device according to claim 1, which is characterized in that the invalid signals are full low level letter
Number；
It is described select output circuit for or gate device, described or gate device be used for input be the acquisition signal and it is described entirely
When low level signal, the acquisition signal is exported.
3. digital signal detecting device according to claim 1, which is characterized in that the data-signal includes: setting number
According to the data frame of digit；
The Acquisition Circuit, specifically includes: the matched shift register of data bits, counter, data with the data frame
Signal judging unit and and gate device；
The input end of clock of the shift register is the first input end, and the signal input part of the shift register is institute
State the second input terminal, the input with the data-signal judging unit respectively of the output end of each register of the shift register
End is connected；The input terminal of the counter is connected with the input end of clock of the shift register, the output end of the counter
Be connected with the input terminal of the data-signal judging unit, the acquisition signal output end of the data-signal judging unit and effectively
Judge that position output end is connected with described with two input terminals of gate device respectively, the output end with gate device is Acquisition Circuit
Output end；
The shift register, for acquire with the matched acquisition signal of the data bits of the data frame, and by the acquisition
Signal is sent to the data-signal judging unit；
The counter, for being sent to the data-signal judging unit when counting up to the data bits of the data frame
Indicate information；
The data-signal judging unit, for will respectively be deposited in the shift register when receiving the instruction information
The data group cooperation of device storage is that the acquisition signal is exported to the acquisition signal output end, and is verified the acquisition signal and be
No the characteristics of meeting data-signal, and generate effective judgement position corresponding with verification result and export to effective judgement position output
End；
Described and gate device, for exporting the result of effective judgement position and the acquisition signal phase with after.
4. digital signal detecting device according to claim 3, which is characterized in that the Acquisition Circuit, further includes: locking
Circuit；
The lock-in circuit, respectively with effective judgement position output end of this Acquisition Circuit and another Acquisition Circuit phase
Even；For in the effective judgement position output end output useful signal for determining this Acquisition Circuit, described another of locking to be adopted
Collector no longer works.
5. digital signal detecting device according to claim 4, which is characterized in that the lock-in circuit passes through trigger,
And/or latch is realized.
6. a kind of MIPI RFFE is from equipment characterized by comprising data-signal inspection as described in any one in claim 1-5
Survey device, the first equipment input terminal, the second equipment input terminal and data signal processing unit；
The first input end of any of the first equipment input terminal and the digital signal detecting device target Acquisition Circuit
It is connected；The second equipment input terminal is connected with the second input terminal of the target Acquisition Circuit；The data-signal processing is single
Member is connected with selection output circuit described in the digital signal detecting device；
The first equipment input terminal, for receiving clock signal or data-signal；
The second equipment input terminal, for receiving data signal or clock signal；
The digital signal detecting device, for what is inputted in the first equipment input terminal and the second equipment input terminal
Correct data-signal is selected to be sent to the data signal processing unit in signal；
The data signal processing unit, for handling the received data-signal.
7. MIPI RFFE according to claim 6 is from equipment, which is characterized in that the data-signal specifically: 13
Command frame, wherein the 0th~3 of the command frame is from device address, and 4-11 of the command frame are RFFE order,
The 12nd of the command frame is parity check bit；
The data signal processing unit specifically includes: Frame processes unit and state machine and file register；
The Frame processes unit and state machine, for receiving the RFFE order in the command frame, and to described
RFFE order is handled；
The file register, for described in receiving in the command frame from device address, and to received described from equipment
Address is handled.
8. MIPI RFFE according to claim 7 is from equipment, which is characterized in that will be in the digital signal detecting device
Two Acquisition Circuits in two clocks, the Frame processes unit and state machine and the file register in when
It is synchronous that clock carries out clock.
9. a kind of MIPI RFFE system characterized by comprising MIPI RFFE main equipment, two such as claim 7-8 are any
MIPI RFFE described in is from equipment；First MIPI RFFE is identical from equipment and second MIPI RFFE from equipment
Two equipment of the identical type that manufacturer produces；
Wherein, the clock end of the MIPI RFFE main equipment is respectively with first MIPI RFFE from the first equipment of equipment
The the second equipment input terminal of input terminal and second MIPI RFFE from the device is connected, and the MIPI RFFE master sets
Standby data terminal is respectively with first MIPI RFFE from the second equipment input terminal and second MIPI of equipment
The the first equipment input terminal of RFFE from the device is connected.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201820905915.0U CN208369547U (en) | 2018-06-12 | 2018-06-12 | Digital signal detecting device, MIPI RFFE are from equipment and system |
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| CN201820905915.0U CN208369547U (en) | 2018-06-12 | 2018-06-12 | Digital signal detecting device, MIPI RFFE are from equipment and system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108718192A (en) * | 2018-06-12 | 2018-10-30 | 江苏卓胜微电子股份有限公司 | Digital signal detecting device, MIPI RFFE equipment and system |
| CN117608909A (en) * | 2024-01-22 | 2024-02-27 | 南京国兆光电科技有限公司 | MIPI data line conflict logic detection circuit |
-
2018
- 2018-06-12 CN CN201820905915.0U patent/CN208369547U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108718192A (en) * | 2018-06-12 | 2018-10-30 | 江苏卓胜微电子股份有限公司 | Digital signal detecting device, MIPI RFFE equipment and system |
| WO2019238144A1 (en) * | 2018-06-12 | 2019-12-19 | 江苏卓胜微电子股份有限公司 | Data signal detection apparatus, and mobile industry processor interface radio frequency front-end slave device and system |
| US11381377B2 (en) | 2018-06-12 | 2022-07-05 | Maxscend Microelectronics Company Limited | Data signal detection apparatus, and mobile industry processor interface radio frequency front-end slave device and system |
| CN108718192B (en) * | 2018-06-12 | 2024-03-05 | 江苏卓胜微电子股份有限公司 | Data signal detection device, MIPI RFFE equipment and system |
| CN117608909A (en) * | 2024-01-22 | 2024-02-27 | 南京国兆光电科技有限公司 | MIPI data line conflict logic detection circuit |
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