CN208298832U - Three-dimensional storage - Google Patents
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- CN208298832U CN208298832U CN201820962326.6U CN201820962326U CN208298832U CN 208298832 U CN208298832 U CN 208298832U CN 201820962326 U CN201820962326 U CN 201820962326U CN 208298832 U CN208298832 U CN 208298832U
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Abstract
The utility model provides a kind of three-dimensional storage, comprising: substrate；Stack layer on the substrate, the stack layer include along the spaced several layers grid layer in direction perpendicular to the substrate；Across the channel hole of the stack layer；Channel layer and drain electrode in the channel hole；The drain electrode is located on the channel layer, and radially outward direction of the drain electrode along the channel hole protrudes from the channel layer.Three-dimensional storage provided by the utility model, so the probability to misplace between its electroconductive contact holes and drain electrode is lower, can have preferable yield due to having the radially outward direction along channel hole to protrude from the drain electrode of channel layer in process of production.
Description
Technical field
The utility model relates generally to technical field of semiconductors more particularly to a kind of three-dimensional storage.
Background technique
With the continuing emphasis to highly integrated electronic device, to higher speed and lower Power operation and having
There are lasting demands for the semiconductor storage unit of the device density of increase.To reach this purpose, having been developed has more
The device of small size and multilayer device with the transistor unit arranged with horizontal and vertical array.Three-dimensional is that industry is researched and developed
The emerging flash type of one kind, 2D is solved by vertical stacking multi-layer data charge-trapping or plane nand flash memory is brought
Limitation, have brilliant precision, support to receive higher memory capacity in smaller space content, memory capacity can be created
It than the storage equipment that similar NAND technology is up to several times, and then effectively reduces cost and energy consumption, can meet comprehensively numerous consumer
Mobile device and the demand for requiring most harsh enterprise's deployment.
Drain electrode is the electrode for the circuit in channel hole to be connect with external circuit.By channel pore radius and memory
The restriction of the factors such as film thickness, in current nand memory, the size in the horizontal direction of drain electrode is smaller.Horizontal direction size
Lesser drain electrode will cause the tungsten electrode formed in tungsten fill process cannot be with the risk of drain electrode connection.Tungsten electrode and drain electrode connect
Connecing cannot connect and device will be caused in turn unavailable.Therefore it is generally required at present when making tungsten electrode more high-precision using having
The litho machine (such as Immersion litho machine) costly of degree.
It is therefore desirable to provide a kind of three-dimensional storage with larger-size drain electrode in the horizontal direction.
Utility model content
The technical problems to be solved in the utility model includes a kind of three with larger-size drain electrode in the horizontal direction
Tie up memory and preparation method thereof.
At least part in solve above-mentioned technical problem, at least one embodiment of the utility model provide one kind three
Tie up memory, comprising:
Substrate；
Stack layer on the substrate, the stack layer include along the spaced several layers in direction perpendicular to the substrate
Grid layer；
Across the channel hole of the stack layer；
Channel layer and drain electrode in the channel hole；
The drain electrode is located on the channel layer, and radially outward direction of the drain electrode along the channel hole protrudes from the channel
Layer.
At least one embodiment according to the present utility model, three-dimensional storage further include: the storage in the channel hole
Device film, around the channel layer, at least part of the drain electrode is located in the memory film at least part of the memory film.
At least one embodiment according to the present utility model, the model of height of the drain electrode on the direction perpendicular to the substrate
Enclose 50 nanometers to 500 nanometers.
At least one embodiment according to the present utility model, the memory film layer include along the radially inward of the channel hole
Barrier oxide layer that direction sequentially forms, electric charge capture layer, tunnel oxide；
Wherein the material of the electric charge capture layer is silicon nitride, and the material of the barrier oxide layer and the tunnel oxide is oxidation
Silicon.
At least one embodiment according to the present utility model, further includes the silicon layer positioned at the channel hole bottom, the silicon layer with
The channel layer is in electrical contact.
At least one embodiment according to the present utility model, the material of the drain electrode include polysilicon.
At least one embodiment according to the present utility model, the material of the channel layer include polysilicon.
The three-dimensional storage of the utility model, since the drain electrode of three-dimensional storage can be made in the radial direction along channel hole
On the size that protrudes outward in channel layer, along (the hereinafter referred to as horizontal direction) in the radial direction in channel hole it is larger.So this
The probability to misplace between the electroconductive contact holes and drain electrode of the three-dimensional storage of utility model is lower, in process of production can
With preferable yield.
Detailed description of the invention
Fig. 1 is the preparation method flow chart of the three-dimensional storage of one embodiment according to the present utility model；
Fig. 2 is the preparation method flow chart of the three-dimensional storage of another embodiment according to the present utility model；
Fig. 3 A-3I is the step of preparation process schematic diagram of the three-dimensional storage of one embodiment of the utility model.
Description of symbols
1- substrate:
2- channel hole；
The first insulating layer of 3-；
4- grid layer；
5- stack layer；
6- hard mask layer；
7- the first hard mask material layer layer；
8- the second hard mask material layer layer；
9- silicon layer；
10- memory film material layer；
110- memory film；
12- layer of channel material；
120 channel layers；
The top of 121- layer of channel material；
13- insulating core membrane layers；
130- insulating core film；
The first groove of 14-；
The second groove of 140-；
16- drain material layer；
160- drain electrode；
17- cap rock；
171- through-hole；
18- electroconductive contact holes.
Specific embodiment
It is practical to this below in conjunction with attached drawing for the above objects, features, and advantages of the utility model can be clearer and more comprehensible
Novel specific embodiment elaborates.
Many details are explained in the following description in order to fully understand the utility model, but this is practical new
Type can also be implemented using other different from other way described herein, therefore the utility model is not by following public tool
The limitation of body embodiment.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
Carry out the preparation of three-dimensional storage in one embodiment to the utility model below with reference to Fig. 1 and Fig. 3 A, 3F and 3H
Method is illustrated.In this embodiment, the preparation method of three-dimensional storage mainly comprises the steps that
With reference to Fig. 3 A, in step 100, semiconductor structure is provided.The semiconductor structure include substrate 1 and be located at the lining
Stack layer 5 on bottom.The stack layer 5 includes along the direction (i.e. vertical direction in Fig. 3 A) perpendicular to substrate 1 to be spaced apart from each other
Form arrangement several layers grid layer 4.Substrate 1 is made in the ongoing illustrated embodiment with monocrystalline silicon.In other examples,
Substrate 1 is made of other suitable materials, these suitable materials include but is not limited to polysilicon, SiGe, germanium, insulator
Silicon-on (SOI).In some embodiments, doped region (not shown) is also formed on substrate 1.
With continued reference to Fig. 3 A, in step 200, formed across the channel hole 2 of stack layer 5.
With reference to Fig. 3 F, in step 300, the channel layer 120 being located in channel hole 2 is formed.The top of the channel layer 120 of formation
Surface is lower than the opening in channel hole 2.
With reference to Fig. 3 H, the drain electrode 160 being located in channel hole 2 is formed.The drain electrode 160 is located on channel layer 120, and the leakage
Pole 160 protrudes outward (i.e. in horizontal direction in Fig. 3 H) in channel layer 120 in the radial direction channel hole 2.
Although the preparation method of three-dimensional storage is as described above, still practical at this in one embodiment of the utility model
In novel other embodiments, what the preparation method of three-dimensional storage in many aspects can be various relative to above-described embodiment
Variation.At least part in these variations is illustrated with some embodiments below.
Carry out the preparation of the three-dimensional storage to another embodiment of the utility model below with reference to Fig. 2 and Fig. 3 A to Fig. 3 I
Method is illustrated.In this embodiment, the preparation method of three-dimensional storage mainly comprises the steps that
With reference to Fig. 3 A, in step 100, semiconductor structure is provided.The semiconductor structure include substrate 1 and be located at the lining
Stack layer 5 on bottom.The stack layer 5 includes along the direction (i.e. vertical direction in Fig. 3 A) perpendicular to substrate 1 to be spaced apart from each other
Form arrangement several layers grid layer 4.In the ongoing illustrated embodiment, the first insulating layer 3 is provided between grid layer 4.Change speech
It, in stack layer 5, multiple first insulating layers 3 and multiple grid layers 4 are arranged in a manner of interval two-by-two, so that several layers grid
Pole layer 4 is spaced apart from each other.
With continued reference to Fig. 3 A, in step 200, formed across the channel hole 2 of stack layer 5.The channel hole 2 can be a moment
What the methods of erosion was formed.
With reference to Fig. 3 B, in step 301, the memory film material layer 10 being located in channel hole 2 is formed.The memory membrane material
The bed of material 10 at least covers the side wall in channel hole 2.In the ongoing illustrated embodiment, which also covers channel hole 2
Bottom.The memory film material layer 10 can be made into subsequent steps as memory film 110.
The structure of memory film material layer 10 can be multiplicity.In some embodiments, memory film material layer 10 is wrapped
Include but in being not limited to the barrier oxide layer sequentially formed outside, electric charge capture layer, tunnel oxide is (due to memory film 110
Thickness very little, to avoid attached drawing is excessively complicated from no longer being marked one by one to barrier oxide layer, electric charge capture layer, tunnel oxide
Note).
In some embodiments, tunnel oxide can be with made of insulating materials, which includes but unlimited
In the combination of silica, silicon nitride or silicon oxynitride or above-mentioned material.In some embodiments, tunnel oxide with a thickness of
5-15nm.In some embodiments, electric charge capture layer can be used for storing charge, the storage of the charge in electric charge capture layer or
Remove the switch state for determining channel semiconductor.The material of electric charge capture layer includes but is not limited to silicon nitride, silicon oxynitride, silicon
Or the combination of the above material.In some embodiments, electric charge capture layer with a thickness of 3-15nm.In some embodiments, it hinders
Barrier material is the combination of silica, silicon nitride, high dielectric constant insulating material or a variety of above materials.A such as oxidation
The composite layer with a thickness of 4-15nm of silicon layer or one comprising three layers of silicon oxide/silicon nitride/silicon oxide (ONO).In some implementations
In example, barrier layer may further include a high k dielectric layer (such as aluminium oxide with a thickness of 1-5nm).
With reference to Fig. 3 C, in step 302, the layer of channel material 12 being located in channel hole 2 is formed.Wherein, at least part
The memory film material layer 10 be located at the periphery of layer of channel material 12.The material of layer of channel material 12 can be noncrystalline, more
It is selected in the materials such as crystallization, monocrystalline silicon.Thin film deposition technique can be used in the technique for forming layer of channel material 12.The film
Depositing technology includes but is not limited to chemical vapour deposition technique (CVD), physical vaporous deposition (PVD) or atomic layer deposition method
(ALD) the perhaps combination of above-mentioned technique or other suitable methods.
With continued reference to Fig. 3 C, in step 303, insulating core membrane layers 13 are formed.The material of the insulating core membrane layers 13
Material can choose the various materials for being suitable for insulating core film such as silica.On the other hand, the insulating core membrane layers 13 are formed
Specific method can be atomic layer deposition method (ALD), spin coating dielectric method (Spin-on dielectric, SOD) or
The combination of above-mentioned technique or other suitable methods.
With reference to Fig. 3 D, in step 304, the top of insulating core membrane layers 130 is removed.Form first groove 14.
The side wall at the top 121 of first groove exposure layer of channel material 12.
With reference to Fig. 3 E, the top of layer of channel material 12 is removed for the first time in step 305.Optionally, in this step, it goes
What is removed is the top 121 for the layer of channel material 12 being exposed in step 304.In other examples, channel material is removed
The top of the bed of material can also include a part of layer of channel material 12 below of top 121 for the road material layer 12 being exposed.It can
Choosing, in this step, with the top of wet etching removal layer of channel material 12.
With reference to Fig. 3 F, within step 306, memory film 110 is formed on the top of removal memory film material layer 10.At this
In step, channel layer 120 is formed on the top for also removing layer of channel material 12 again.The step for after the completion of will form the second groove
140.At least part of second groove 140 is located at the top of 110 top surface of memory film.It is such to be arranged so that subsequent step
At least part of the drain electrode 160 formed in rapid can be located at the top of the memory film 110.Optionally, in this step
Insulating core film 130 is formed on the top for also removing insulating core membrane layers 13 again.
With continued reference to Fig. 3 F, in the ongoing illustrated embodiment, the step in the top of memory film material layer 10, insulation
The removal amount at the top of core membrane layers 13 is larger, smaller to the removal amount at the top except layer of channel material 12.This is because
In the present embodiment, although in the step being top and the insulating core membrane material realized with same step to memory film material layer 10
The top of layer 13, and the step for also lead to removal to the top except layer of channel material 12, but in this step, channel
The removal amount of the top of material layer 12 in the vertical direction not necessarily and arrive insulating core membrane layers 13 and memory film material layer
The removal amount of 10 top in the vertical direction is identical or close.In other words, in some embodiments, which carves
Erosion to the etch rate of memory film material layer 10 and can be set to greatly the etch rate of insulating core membrane layers 13
In or equal to the etch rate of layer of channel material 12.
It is worth noting that, to the removal amount at the top of memory film material layer 10, the top of insulating core membrane layers 13
It is larger, division result only is gone to step 306 to this lesser etching result of removal amount at the top except layer of channel material 12
Citing, do not represent after completing this step, it is necessary to so that the top of channel layer 120 be higher than 110 top surface of memory film.
In fact, in other examples, can choose with the other modes such as dry etching to the top of memory film material layer 10,
Except the top of layer of channel material 12 and the top of insulating core membrane layers 13 are removed, and to memory film material layer 10
The step of top at top, the top except layer of channel material 12 and insulating core membrane layers 13 is removed is also possible to by more
Secondary removal (such as multiple etching) is come what is realized.On the other hand, after this step, the top of channel layer 120 and memory
What 110 top surface of film was also possible to flush.
In step 400, drain electrode 160 is formed.The step of formation drain electrode 160, can be being also possible to of disposably being formed
It is divided into multiple sub-steps to carry out.Illustrate a kind of method of optional formation drain electrode 160 with Fig. 3 G and Fig. 3 H below.
With reference to Fig. 3 G, in the optional method that one forms drain electrode 160, first entire for making the half of three-dimensional storage
Drain material layer 16 is formed at the top of conductor structure.The concrete form of this forming step can multiplicity.For example, the drain electrode material
The material of the bed of material 16 can be polysilicon, monocrystalline silicon etc..The specific method for forming the drain material layer 16 can be gas phase and sink
Area method (Chemical Vapor Deposition, CVD), physical vaporous deposition (Physical Vapor Deposition,
) or the methods of atomic layer deposition method (Atomic Layer Deposition, ALD) PVD.The formation drain material layer 16 of formation
Top can not be smooth, such as in the ongoing illustrated embodiment, the top of the drain material layer 16 of formation has and channel
The corresponding protrusion of material layer 12.
Drain material layer 16 is planarized, the planarization process after forming drain material layer 16 with reference to Fig. 3 H
It can be and realized in the mode of chemical mechanical grinding (Chemical-Mechanical planarization, CMP), it can also
With what is realized with other planarization methods.Planarisation step removal is located at the drain material layer 16 other than the second groove, in turn
Form drain electrode 160.
The preparation method of the three-dimensional storage of the present embodiment, since the drain electrode 160 of three-dimensional storage can be made along channel
Hole 2 in the radial direction, is protruded outward in channel layer 120.So the preparation method of the three-dimensional storage of the present embodiment to leak
Size in the radial direction (i.e. the horizontal direction of Fig. 3 A to Fig. 3 H in) of the pole 160 in channel hole 2 is larger.Horizontal size is biggish
Drain electrode 160 can reduce the risk that the tungsten electrode formed in subsequent tungsten fill process cannot be connect with drain electrode 160, Jin Erneng
Enough improve the production yield of three-dimensional storage.
Although above-described embodiment gives some variations of the preparation method of three-dimensional storage.But in other embodiments
In, many aspects of the preparation method of three-dimensional storage also have more variations.Continued below with some more embodiments
At least part in the optional variation of the preparation method of three-dimensional storage is illustrated.
With reference to Fig. 3 A, in some embodiments, stack layer 5 also wraps other than including grid layer 4 and the first insulating layer 3
Include the hard mask layer 6 of the top layer positioned at stack layer 5.The hard mask layer 6 can be single layer structure and be also possible to multilayered structure.Continue
With reference to Fig. 3 A, in one embodiment, the hard mask layer 6 further comprise the first hard mask material layer layer 7 and be located at this first
Second hard mask material layer layer 8 of 7 top of hard mask material layer layer.Wherein the first hard mask material layer layer 7 and second is covered firmly
The material of film material layer 8 is different, and the material packet of the first hard mask material layer layer 7 and the second hard mask material layer layer 8
Include but be not limited to the combination of silica, silicon nitride or silicon oxynitride or a variety of above materials.
Optionally, in some embodiments, at least part of the hard mask layer 6 removes in subsequent steps.With reference to
Fig. 3 E and Fig. 3 F, in some embodiments, in the step of memory film 110 are formed on the top for removing memory film material layer 10
In, channel layer 120 is formed on the top for not only removing layer of channel material 12 again, removes the top of insulating core membrane layers 13 again
Insulating core film 130 is formed, also together removes hard mask layer 6.
Hard mask layer 6, electric charge capture layer, barrier oxide layer, tunnel oxide and insulating core membrane layers 13 material can
To be selected as needed.In some embodiments, at least part of material of hard mask layer 6 and the material of electric charge capture layer
Expect identical, barrier oxide layer, tunnel oxide, the material of insulating core membrane layers 13 are identical.
In some embodiments, hard mask layer 6, electric charge capture layer any layer be made of the first material, barrier oxide layer,
Any layer in tunnel oxide, insulating core membrane layers 13 is made of the second material.Wherein first material and the second material
Between etching selection ratio be equal to 1.The specific choices of those materials is it may is that multiplicity, such as in one embodiment,
The material of hard mask layer 6 and electric charge capture layer is silicon nitride.Barrier oxide layer, tunnel oxide and insulating core membrane layers 13
Material is then silica.
The height that is size be defined as drain electrode 160 of the drain electrode 160 on the direction perpendicular to substrate.The height of the drain electrode 160
Degree can select in a certain range.With reference to Fig. 3 H, in some embodiments, 160 range of height of draining is 50 to receive
Rice is to 500 nanometers.
Although the step of being not described in after forming drain electrode 160 in the foregoing embodiments.But in fact, practical at this
In novel some embodiments, more steps can also be had later by forming drain electrode 160.It is practical new to this below with reference to Fig. 3 I
The some of type are that embodiment is illustrated.In these embodiments, except include in any one aforementioned embodiment formation drain electrode
Except all or part of step before 160, also comprise the steps of:
Step 500, the cap rock 17 of covering semiconductor structure and drain electrode 160 is formed.It is formed in the cap rock 17 and drain electrode 160
The through-hole 171 of alignment.The shape of the through-hole 171 either funnel shaped as shown in Fig. 3 I, be also possible to column etc. its
His shape.
Step 600, metal filling is carried out to through-hole 171, so that the metal of filling and drain electrode 160 form electroconductive contact holes.
Wherein being filled metal used to through-hole 171 can be tungsten or other conductive metals.
Although previous embodiment is all the preparation method about three-dimensional storage, these embodiments are only deposited with three-dimensional
Illustrate the spirit of the utility model for reservoir.The utility model is in fact not limited to the preparation method field of three-dimensional storage.
Some embodiments of the utility model is to describe for convenience about the method for making drain electrode on sunk structure and reduce attached drawing number
Amount, below still with attached drawing 3A, Fig. 3 F and Fig. 3 H to production drains on sunk structure in some embodiments of the utility model
Method be illustrated.It is worth noting that, not represented using these attached drawings merely to just describe and reduce attached drawing quantity
Whole labels in these attached drawings are all necessary.
In these embodiments, the method for making drain electrode mainly comprises the steps that
Referring initially to Fig. 3 A, the semiconductor structure with sunk structure 2 is provided.The semiconductor structure can be used to make
The semiconductor structure for making three-dimensional storage is also possible to be used to make the semiconductor structure of other chips, memory.The recess
Structure 2 is also possible to other sunk structures such as groove either channel hole.
With reference to Fig. 3 F, the channel layer 120 being located in the sunk structure 2 is formed.The top surface of the channel layer 120 is lower than recess
The opening of structure 2.
With reference to Fig. 3 H, the drain electrode 160 being located in sunk structure 2 is formed.The drain electrode 160 is located on the channel layer, and
The channel layer is protruded from along the radially outward direction of the sunk structure.
Although make drain electrode method one embodiment as described above, but in some other embodiments, production leakage
The method of pole include thes steps that more.It is illustrated below with reference to Fig. 3 B to Fig. 3 F come the step more to these.These are more
More steps specifically include that
With reference to Fig. 3 B, the memory film material layer 10 being located in sunk structure 2 is formed.
The layer of channel material 12 being located in memory film material layer 10 is formed with reference to Fig. 3 C.Wherein at least a part of memory
Membrane layers 10 are located at the periphery of layer of channel material 12.
With continued reference to Fig. 3 C, the insulating core membrane layers 13 being located inside sunk structure 2 are formed.The wherein at least ditch of part
Road material layer 12 is located at the periphery of insulating core membrane layers 13.
With reference to Fig. 3 D, the top of insulating core membrane layers 13 is removed.The step for after the completion of can expose layer of channel material 12
Top.
With reference to Fig. 3 E, the top of layer of channel material 12 is removed for the first time.
With reference to Fig. 3 F, the top of memory film material layer 10 is removed, and removes the top of layer of channel material 12 again simultaneously.
Some more embodiments of the utility model are about three-dimensional storage, below with reference to Fig. 3 I to originally practical new
The three-dimensional storage of some embodiments of type is illustrated.In these embodiments, three-dimensional storage includes: substrate 1, channel hole
2 and stack layer 5.Wherein stack layer 5 is located at the top of substrate 1, and channel hole 2 then passes through stack layer 5.Wherein stack layer 5 is further
Including along the spaced stacked gate layer 4 in direction perpendicular to substrate.In some embodiments, being stacked into 5 further includes multilayer
First insulating layer 3, first insulating layer of multilayer 3 and stacked gate layer 4 are arranged alternately so that the first insulation between stacked gate layer 4
Layer 3 is spaced.
The three-dimensional storage of the present embodiment also has channel layer 120 and drain electrode 160.Wherein channel layer 102 and drain electrode be 160 all
Positioned at the inside in channel hole 2, and 160 are drained positioned at the top of channel layer 120.Channel hole 2 in the radial direction, drain electrode 160
It protrudes outward relative to channel layer 120 in channel layer 120.
In some embodiments, three-dimensional storage further includes the memory film 110 in channel hole 2.Wherein memory
Film 110 is located at the outside of channel layer 120 and around channel layer 120, and 160 at least part of drain electrode are located at the upper of memory film 110
Side.
In some embodiments, the drain electrode 160 of three-dimensional storage is size be defined as on the direction perpendicular to substrate 1
The height of drain electrode 160.The height of the drain electrode 160 can select in a certain range.With reference to Fig. 3 H, in some embodiments
In, 160 range of height of draining is 50 nanometers to 500 nanometers.
In some embodiments, the memory film 110 of three-dimensional storage includes the radially inward side along the channel hole 2
To barrier oxide layer, electric charge capture layer and the tunnel oxide sequentially formed.The wherein barrier oxide layer, electric charge capture layer and tunnel
The material for wearing oxide layer can be multiplicity.In some embodiments, the material of electric charge capture layer is silicon nitride, barrier oxide layer
Material with tunnel oxide is silica.
Other positions of three-dimensional storage also can have the variation of multiplicity.In some embodiments, three-dimensional storage is also
Including silicon layer 9.The silicon layer 9 is located at the bottom in channel hole 2, and the silicon layer 9 and channel layer 120 are in electrical contact.On the other hand, three
Tie up memory drain electrode 160 material can be it is changeable, in some embodiments, the material of the drain electrode 160 of the three-dimensional storage
Material includes polysilicon.Similar, the material of the channel layer 120 of the three-dimensional storage is also possible to multiplicity.In some embodiments
In, the material of the channel layer 12 of the three-dimensional storage includes polysilicon.
Although the utility model is described with reference to current multiple specific embodiments, in the art common
It should be recognized by those skilled in the art that above embodiment is intended merely to illustrate the utility model, in no disengaging the utility model
Various equivalent change or replacement can be also made in the case where spirit.Therefore, if the utility model spirit
Interior variation, modification to above-described embodiment will all be fallen in the range of following claims.
Claims (7)
1. a kind of three-dimensional storage characterized by comprising
Substrate；
Stack layer on the substrate, the stack layer include spaced several along the direction perpendicular to the substrate
Layer grid layer；
Across the channel hole of the stack layer；
Channel layer and drain electrode in the channel hole；
The drain electrode is located on the channel layer, and radially outward direction of the drain electrode along the channel hole protrudes from described
Channel layer.
2. three-dimensional storage as described in claim 1, which is characterized in that further include: the memory in the channel hole
Film, at least part of the memory film around the channel layer, at least part of the drain electrode is located at the memory
On film.
3. three-dimensional storage according to claim 1, it is characterised in that: the drain electrode is in the direction perpendicular to the substrate
On 50 nanometers to 500 nanometers of range of height.
4. three-dimensional storage according to claim 1, it is characterised in that: the memory film layer includes along the channel hole
The barrier oxide layer radially inwardly sequentially formed, electric charge capture layer, tunnel oxide；
Wherein the material of the electric charge capture layer is silicon nitride, and the material of the barrier oxide layer and the tunnel oxide is oxygen
SiClx.
5. three-dimensional storage according to claim 1, it is characterised in that: further include the silicon positioned at channel hole bottom
Layer, the silicon layer and the channel layer are in electrical contact.
6. three-dimensional storage according to any one of claims 1 to 5, it is characterised in that: the material of the drain electrode includes more
Crystal silicon.
7. such as three-dimensional storage described in any one of claim 1 to 5, which is characterized in that the material of the channel layer includes more
Crystal silicon.
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| CN201820962326.6U CN208298832U (en) | 2018-06-21 | 2018-06-21 | Three-dimensional storage |
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|---|---|---|---|---|
| CN108598085A (en) * | 2018-06-21 | 2018-09-28 | 长江存储科技有限责任公司 | Three-dimensional storage and preparation method thereof, the method that drain electrode is made on sunk structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108598085A (en) * | 2018-06-21 | 2018-09-28 | 长江存储科技有限责任公司 | Three-dimensional storage and preparation method thereof, the method that drain electrode is made on sunk structure |
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