CN208271904U - Power semiconductor element - Google Patents
Power semiconductor element Download PDFInfo
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- CN208271904U CN208271904U CN201820791965.0U CN201820791965U CN208271904U CN 208271904 U CN208271904 U CN 208271904U CN 201820791965 U CN201820791965 U CN 201820791965U CN 208271904 U CN208271904 U CN 208271904U
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- electrode
- epitaxial layer
- power semiconductor
- resistive element
- current potential
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000005611 electricity Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The utility model provides a power semiconductor component, include: the device comprises a substrate, a first epitaxial layer and a second epitaxial layer. The substrate defines an active region and a termination region. The termination region surrounds the active region. The first epitaxial layer is disposed on the substrate in the active region and the termination region. The second epitaxial layer is disposed between the substrate and the first epitaxial layer. The second epitaxial layer includes: a first termination trench and a second termination trench. The first termination trench has a first electrode disposed in the termination region and adjacent to the active region. The second termination trench has a second electrode disposed in the termination region. The potential of the first electrode and the potential of the second electrode are between the source potential and the drain potential. The utility model provides a power semiconductor component, the accessible improves the electric field distortion phenomenon of trench electrode edge in the terminal area, and then promotes power semiconductor component's breakdown voltage.
Description
Technical field
The utility model relates to a kind of semiconductor element more particularly to a kind of power semiconductors.
Background technique
Power semiconductor is a kind of semiconductor element for being widely used in analogous circuit.Due to power semiconductor
With low-down conducting resistance and very fast switch speed, therefore, power semiconductor can be applicable to power supply switching
On (Power switch) circuit, so that power management techniques (power management techniques) are more efficiently.
With scientific and technological progress, electronic component is towards lightening trend development.Since the size of electronic component constantly contracts
It is small, maintain low conduction impedance (Conductance Resistance), the high-breakdown-voltage of power semiconductor
(Breakdown voltage) also more difficult.Therefore, how to improve power semiconductor under certain component size
Conduction impedance and breakdown voltage are inscribed an important subject is become.
Utility model content
The utility model provides a kind of power semiconductor, in being configured with two layers of epitaxial layer on substrate, and makes end
The current potential of at least two trench electrodes improves groove in termination environment between source potential and drain potential whereby in petiolarea
Electric field distorting phenomenon at electrode edge, and then the breakdown voltage of hoisting power semiconductor element.
It includes: substrate, the first epitaxial layer and the second epitaxial layer that the utility model, which provides a kind of power semiconductor,.Base
Bottom definition has active area and termination environment.Termination environment surrounds active area.First epitaxial layer configures the substrate in active area and termination environment
On.Second epitaxial layer configures between substrate and the first epitaxial layer.It include: that first terminal groove and second are whole in second epitaxial layer
Hold groove.First terminal groove has first electrode, and configuration is in the termination region and adjacent active regions.Second terminal groove has
Second electrode, configuration is in the termination region.The current potential of first electrode and the current potential of second electrode are between source potential and drain electrode electricity
Between position.
In an embodiment of the utility model, the current potential of first electrode between second electrode current potential and source potential it
Between.
In an embodiment of the utility model, power semiconductor further includes third terminal groove, with third
Electrode, and configure between first terminal groove and second terminal groove.Current potential of the current potential of third electrode between first electrode
Between the current potential of second electrode.
In an embodiment of the utility model, power semiconductor further includes resistive element, configuration source electrode with
Between drain electrode, and it is electrically connected first electrode and second electrode.
In an embodiment of the utility model, resistive element is the multiple resistance being cascaded, first electrode and
The node between multiple resistance is electrically connected in second electrode.
In an embodiment of the utility model, resistive element is linear, circular termination environment.
In an embodiment of the utility model, resistive element is configured in the groove in the first epitaxial layer.
In an embodiment of the utility model, resistive element is conductive layer, is configured on the first epitaxial layer.Conductive layer
It is electrically isolated with the first epitaxial layer.
In an embodiment of the utility model, resistive element is the doped region in the first epitaxial layer, doped region
Conductivity type is different from the conductivity type of the first epitaxial layer.
In an embodiment of the utility model, the doping that the doping concentration of the first epitaxial layer is greater than the second epitaxial layer is dense
Degree.
Based on above-mentioned, the utility model is reduced by double extension structure (double epitaxial structure)
The conduction impedance of power semiconductor.In addition, again by the current potential of at least two trench electrodes in termination environment between source electrode electricity
Between position and drain potential, slows down whereby, even is eliminated the electric field distorting phenomenon of the edge of the trench electrode in termination environment,
So as to improve the breakdown voltage of power semiconductor.In this way, which the power semiconductor of the utility model can be certain
Component size under have good element characteristic.
In order to make the above-mentioned features and advantages of the utility model more obvious and understandable, special embodiment below, and cooperate attached drawing
It is described in detail below.
Detailed description of the invention
Fig. 1 is the upper schematic diagram according to a kind of power semiconductor of an embodiment of the present invention；
Fig. 2 is the diagrammatic cross-section of the line I-I ' of Fig. 1；
Fig. 3 is the diagrammatic cross-section of the line II-II ' of Fig. 1；
Fig. 4 is the diagrammatic cross-section of the line II-II ' of Fig. 1；
Fig. 5 is the diagrammatic cross-section of the line I-I ' of Fig. 1.
Specific embodiment
Referring to the attached drawing of the present embodiment more fully to illustrate the utility model.However, the utility model also can be with various
Different forms embodies, and should not necessarily be limited by embodiment herein.The thickness of layer and region in attached drawing can be for the sake of clarity
And amplify.The same or similar label indicates the same or similar element, and following paragraphs will be repeated no longer one by one.
Fig. 1 is the upper schematic diagram according to a kind of power semiconductor of an embodiment of the present invention.Fig. 2 is Fig. 1
Line I-I ' diagrammatic cross-section.It below in an example, is using the first conductive type as N-type, the second conductive type is for p-type
Illustrate, but the utility model is not limited thereto.It will be understood by a person skilled in the art that the first conductive type may be p-type, and
The second conductive type is N-type.
Fig. 1 and Fig. 2 are please referred to, the power semiconductor 1 of an embodiment of the present invention includes substrate 100, definition
There are active area AR and termination environment TR.Termination environment TR is around active area AR, generation the phenomenon that prevent voltage breakdown.In the present embodiment
In, substrate 100 is the semiconductor base with the first conductive type, such as the silicon base of n-type doping.
As shown in Fig. 2, the configuration of epitaxial layer 102 is in the substrate 100 of active area AR and termination environment TR.In one embodiment,
Epitaxial layer 102 is the epitaxial layer with the first conductive type, e.g. the epitaxial layer that is lightly doped of N-type.Epitaxial layer 104 is configured in extension
On layer 102.That is, epitaxial layer 102 (also referred to as the second epitaxial layer) configuration (can also claim in substrate 100 and epitaxial layer 104
For the first epitaxial layer) between.In one embodiment, epitaxial layer 104 is the epitaxial layer with the first conductive type, and e.g. N-type is light
The epitaxial layer of doping.The doping concentration of epitaxial layer 104 is greater than the doping concentration of epitaxial layer 102, to form double extension structure.This
The conduction impedance of double extension structure cpable of lowering power semiconductor element 1.
As shown in Figure 1, active area AR has multiple active grooves 10.Multiple configurations of active groove 10 are in the outer of active area AR
Prolong (not shown) in layer 104.Active groove 10 includes strip-shaped grooves 10a and annular ditch groove 10b.Strip-shaped grooves 10a is along first party
Extend to D1 and D2 is arranged in a second direction.As shown in Figure 1, annular ditch groove 10b surround strip-shaped grooves 10a, by strip-shaped grooves
The end of 10a links together.In one embodiment, strip-shaped grooves 10a is arranged in a manner of equidistant, and disconnected from each other.?
In one embodiment, an at least end face of strip-shaped grooves 10a is substantially to be aligned.In alternative embodiments, active groove 10 is also
Strip-shaped grooves 10a can be only included, without annular ditch groove 10b.First direction D1 intersects with second direction D2.In an embodiment
In, first direction D1 is perpendicular to second direction D2.Although Fig. 1 is not shown with Fig. 2, in some embodiments, each active groove
Insulating layer in 10 with conductive layer and encirclement conductive layer, to form trench gate structure.
As shown in Figure 1, there are three terminal trenches 20 for termination environment TR tool.Termination environment TR includes first terminal groove 22, second
Terminal trenches 24 and third terminal groove 26.First terminal groove 22, second terminal groove 24 and third terminal groove 26
It is separated from each other and is not attached to.First terminal groove 22 configures in the epitaxial layer 104 of termination environment TR.First terminal groove 22 is surround
Active groove 10 in active area AR, to form enclosed ring-shaped groove.As shown in Figure 1, first terminal groove 22 is neighbouring to be had
It the active groove 10 of source region AR and is separated from each other, and is not attached to active groove 10.In the present embodiment, active groove 10 can be used
With as element groove (cell trench) to accommodate trench gate structure；And first terminal groove 22, second terminal groove 24
And third terminal groove 26 all can be used to accommodate terminal structure.Although Fig. 1 shows three terminal trenches 20, this is practical new
Type is not limited.In other embodiments, termination environment TR can only include two terminal trenches 20 (such as first terminal groove 22
With second terminal groove 24).In alternative embodiments, termination environment TR also may include three or more terminal trenches 20, e.g. 4
A, 5 or more terminal trenches 20.
As shown in Fig. 2, there is first electrode 122 and insulating layer 118, to form terminal structure in first terminal groove 22.
Insulating layer 118 is around first electrode 122, with first electrode 122 and the epitaxial layer 104 of being electrically insulated.In one embodiment, the first electricity
The material of pole 122 includes DOPOS doped polycrystalline silicon.The material of insulating layer 118 includes silica.
As shown in Figure 1, the configuration of second terminal groove 24 is sealed in the TR of termination environment and around first terminal groove 22 with being formed
The ring-shaped groove of enclosed.Third terminal groove 26 configures between first terminal groove 22 and second terminal groove 24, also shape
At enclosed ring-shaped groove.
As shown in Fig. 2, there is second electrode 124 and insulating layer 118, to form terminal structure in second terminal groove 24.
In one embodiment, insulating layer 118 is around second electrode 124, with second electrode 124 and the epitaxial layer 104 of being electrically insulated.It is similar
Ground has third electrode 126 and insulating layer 118 in third terminal groove 26, to form terminal structure.In one embodiment, absolutely
Edge layer 118 is around third electrode 126, with third electrode 126 and the epitaxial layer 104 of being electrically insulated.In one embodiment, second electrode
124 respectively include DOPOS doped polycrystalline silicon with the material of third electrode 126.The material of insulating layer 118 includes silica.
As shown in Figure 1, the power semiconductor 1 of the utility model further includes resistive element 30, it is coupled to source S and leakage
Between the D of pole.Resistive element 30 and first electrode 122, second electrode 124 and third electrode 126 are electrically connected, as shown in Figure 2.
Specifically, resistive element 30 can be multiple resistance R1, R2, R3, the R4 being cascaded.First electrode 122 is electrically connected
To the node N1 between resistance R1, R2；Second electrode 124 is electrically connected to the node N2 between resistance R3, R4；Third electrode
126 are electrically connected to the node N3 between resistance R2, R3.Under this arrangement, i.e., make the first electricity using the mode of electric resistance partial pressure
The current potential V3 of the current potential V1 of pole 122, the current potential V2 of second electrode 124 and third electrode 126 are between source potential and drain electrode electricity
Between position.In this way, which the power line in the TR of termination environment can be evenly distributed, to slow down, it even is eliminated third electrode 126
The electric field distorting phenomenon of edge, and then improve the breakdown voltage of power semiconductor 1.
In one embodiment, as shown in Fig. 2, first electrode 122 is close to source S；And second electrode 124 is close to drain D.Cause
This, the current potential V1 of first electrode 122 is between the current potential V2 and source potential of second electrode 124.In addition, third electrode 126
Between first electrode 122 and second electrode 124.Similarly, the current potential V3 of third electrode 126 is then between first electrode 122
Current potential V1 and second electrode 124 current potential V2 between.That is, the current potential of the trench electrode in the TR of termination environment is by source S
Toward the direction gradual change of drain D.In the present embodiment, direction of the current potential of the trench electrode in the TR of termination environment from source S toward drain D
Increase.In other words, the current potential V2 of second electrode 124 is greater than the current potential V3 of third electrode 126, and the current potential V3 of third electrode 126
Greater than the current potential V1 of first electrode 122.But the utility model is not limited.
In one embodiment, from the point of view of upward angle of visibility degree, resistive element 30 can be it is linear, along a spirality path ring
Around termination environment TR, as shown in Figure 1.First electrode 122, second electrode 124 and third electrode 126 can be at different line segments and electric
Resistance element 30 is connected.The utility model can adjust the resistance of resistance R1, R2, R3, R4 by the length of linear resistive element 30
Value.In detail, when the length of linear resistive element 30 is longer, then its resistance value is then higher.In one embodiment, resistance member
The material of part 30 can be for example DOPOS doped polycrystalline silicon or un-doped polysilicon.
Fig. 3 is the diagrammatic cross-section of the line II-II ' of Fig. 1.
Referring to figure 3., referring to figure 4. with Fig. 3, substantially, the power of the power semiconductor 1a and Fig. 2 of Fig. 3 are partly led
Volume elements part 1 is similar.It is both above-mentioned the difference is that: power semiconductor 1a further includes the configuration of groove 28 in epitaxial layer 104
In.In one embodiment, groove 28 can be with first terminal groove 22, second terminal groove 24 and third terminal groove 26 simultaneously
It is formed, but the utility model is not limited.In other embodiments, the bottom surface of groove 28 can be higher or lower than first terminal ditch
The bottom surface of the bottom surface of slot 22, the bottom surface of second terminal groove 24 and third terminal groove 26.In addition, groove 28 and second terminal
The distance between groove 24 d can be adjusted according to the demand of the operation voltage of element, and the utility model is not limited.
As shown in figure 3, there is conductive layer 128 and insulating layer 118, to form resistive element 30a in groove 28.Insulating layer
118 around conductive layer 128, so that conductive layer 128 is electrically isolated with epitaxial layer 104.In one embodiment, the material of conductive layer 128
Material can be for example DOPOS doped polycrystalline silicon or un-doped polysilicon.The material of insulating layer 118 includes silica.On the other hand, such as Fig. 1 institute
Show, resistive element 30a is along a spirality path around second terminal groove 24.In one embodiment, resistive element 30a can match
It is placed in the periphery of termination environment TR.But the utility model is not limited, and in other embodiments, resistive element 30a also can configure
In the TR of termination environment.In addition, the distance between resistive element 30a (or conductive layer 128) and second terminal groove 24 d can be according to elements
The demand of operation voltage adjust, the utility model is not limited.Although in addition, not showing that resistance on the section of Fig. 3
Element 30a (or conductive layer 128) and first electrode 122, second electrode 124 or third electrode 126 are electrically connected, but at other
On section, resistive element 30a can at node N1, N2, N3 respectively with first electrode 122, second electrode 124 and third electrode
126 are electrically connected.
Fig. 4 is the diagrammatic cross-section of the line II-II ' of Fig. 1.
Referring to figure 4. with Fig. 3, substantially, the power semiconductor 1a phase of power semiconductor 1b and Fig. 3 of Fig. 4
Seemingly.It is both above-mentioned the difference is that: the power semiconductor 1b of Fig. 4 is taken with the doped region 228 with the second conductive type
For the resistive element 30a of Fig. 3.That is, doped region 228 is a kind of resistive element 30b, configure in epitaxial layer 104.?
In one embodiment, doped region 228 can be P-doped zone, have different conductivity types from epitaxial layer 104.Although shown by Fig. 4
The bottom surface of doped region 228 be higher than the bottom surface of first terminal groove 22, the bottom surface of second terminal groove 24 and third terminal ditch
The bottom surface of slot 26.But the utility model is not limited, on the other hand, as shown in Figure 1, resistive element 30b can be along a spiral
Shape path is around second terminal groove 24.In one embodiment, resistive element 30b is configured in the periphery of termination environment TR.But this
Utility model is not limited, and in other embodiments, resistive element 30b is also configured in the TR of termination environment.In addition, though figure
Resistive element 30b (or doped region 228) and first electrode 122, second electrode 124 or third electricity are not showed that on 4 section
Pole 126 is electrically connected, but on other sections, resistive element 30b can at node N1, N2, N3 respectively with first electrode 122,
Second electrode 124 and third electrode 126 are electrically connected.
Fig. 5 is the diagrammatic cross-section of the line I-I ' of Fig. 1.
Referring to figure 5. with Fig. 2, substantially, 1 phase of power semiconductor of power semiconductor 1c and Fig. 2 of Fig. 5
Seemingly.It is both above-mentioned the difference is that: the power semiconductor 1c of Fig. 5 further includes dielectric layer 318, conductive layer 328 and inserts
Plug 320.Specifically, the configuration of dielectric layer 318 is on epitaxial layer 104, covers the top surface of epitaxial layer 104, first electrode 122
The top surface of top surface, the top surface of second electrode 124 and third electrode 126.In one embodiment, the material of dielectric layer 318 includes
Silica.Conductive layer 328 configures on dielectric layer 318, passes through 124 electrical property of plug 320 and second electrode in dielectric layer 318
Connection.In the present embodiment, the combination of conductive layer 328 and plug 320 can be considered as resistive element 30c, configure in epitaxial layer
On 104, and electrically isolated with epitaxial layer 104.In other words, resistive element 30c and first electrode 122, second electrode 124 and the
Three electrodes 126 are configurable on different level.
In one embodiment, since resistive element 30c configuration is on epitaxial layer 104, resistive element 30c can be via
On the epitaxial layer 104 that the mode of wiring (route) or intraconnections (interconnect) configured in termination environment TR, more even exist
On the epitaxial layer 104 of active area AR.In addition, though plug 320 illustrated in fig. 5 is only configured in conductive layer 328 and second electrode
Between 124, it is electrically connected conductive layer 328 and second electrode 124 whereby.But on other sections, still there are other plugs (not show
Configuration is between conductive layer 328 and first electrode 122 or third electrode 126 out).In the case, plug 320 can be considered node
N2。
In conclusion the utility model reduces the conduction impedance of power semiconductor by double extension structure.Separately
Outside, then by the current potential of at least two trench electrodes in termination environment between source potential and drain potential, slow down whereby,
It even is eliminated the electric field distorting phenomenon of the edge of the trench electrode in termination environment, so as to improve the breakdown of power semiconductor
Voltage.In this way, which the power semiconductor of the utility model can have good element special under certain component size
Property
Although the utility model is disclosed as above with embodiment, so it is not intended to limit the utility model, any affiliated
Technical staff in technical field, without departing from the spirit and scope of the utility model, when can make a little change and retouching, therefore
Subject to the protection scope of the utility model ought be defined depending on claim.
Claims (10)
1. a kind of power semiconductor characterized by comprising
Substrate, definition have active area and termination environment, and the termination environment surrounds the active area；
First epitaxial layer configures in the substrate of the active area Yu the termination environment；And
Second epitaxial layer configures between the substrate and first epitaxial layer；
Wherein include: in second epitaxial layer
First terminal groove has first electrode, and configuration is in the termination environment and adjacent to the active area；And
Second terminal groove, have second electrode, configure in the termination environment, wherein the current potential of the first electrode with it is described
The current potential of second electrode is between source potential and drain potential.
2. power semiconductor according to claim 1, which is characterized in that the current potential of the first electrode between
Between the current potential and the source potential of the second electrode.
3. power semiconductor according to claim 1, which is characterized in that further include third terminal groove, have the
Three electrodes configure between the first terminal groove and the second terminal groove, wherein the current potential of the third electrode is situated between
Between the current potential of the first electrode and the current potential of the second electrode.
4. power semiconductor according to claim 1, which is characterized in that further include resistive element, configure in source electrode
Between drain electrode, it is electrically connected the first electrode and the second electrode.
5. power semiconductor according to claim 4, which is characterized in that the resistive element is cascaded
The node between the multiple resistance is electrically connected in multiple resistance, the first electrode and the second electrode.
6. power semiconductor according to claim 4, which is characterized in that the resistive element is linear, circular institute
State termination environment.
7. power semiconductor according to claim 4, which is characterized in that the resistive element configuration is described first
In groove in epitaxial layer.
8. power semiconductor according to claim 4, which is characterized in that the resistive element is conductive layer, configuration
In on first epitaxial layer, wherein the conductive layer is electrically isolated with first epitaxial layer.
9. power semiconductor according to claim 4, which is characterized in that the resistive element is positioned at described first
The conductivity type of doped region in epitaxial layer, the miscellaneous area of doped region is different from the conductivity type of first epitaxial layer.
10. power semiconductor according to claim 1, which is characterized in that the doping concentration of first epitaxial layer
Greater than the doping concentration of second epitaxial layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107205029U TWM565404U (en) | 2018-04-18 | 2018-04-18 | Power semiconductor device |
| TW107205029 | 2018-04-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208271904U true CN208271904U (en) | 2018-12-21 |
Family
ID=63961300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820791965.0U Active CN208271904U (en) | 2018-04-18 | 2018-05-25 | Power semiconductor element |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN208271904U (en) |
| TW (1) | TWM565404U (en) |
-
2018
- 2018-04-18 TW TW107205029U patent/TWM565404U/en unknown
- 2018-05-25 CN CN201820791965.0U patent/CN208271904U/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TWM565404U (en) | 2018-08-11 |
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190731 Address after: Taiwan Hsinchu County China jhubei City, Taiwan 5 yuan a Street No. 9 Building 1 Patentee after: Upi Semiconductor Corp. Address before: 6, No. 5, Taiyuan street, No. 5, Taiyuan street, bamboo North City, county Patentee before: UBIQ Semiconductor Corp. |
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| TR01 | Transfer of patent right |