CN208172162U - It is a kind of reduce semiconductor chip electrostatic test during electrostatic friction device - Google Patents
It is a kind of reduce semiconductor chip electrostatic test during electrostatic friction device Download PDFInfo
- Publication number
- CN208172162U CN208172162U CN201820584583.0U CN201820584583U CN208172162U CN 208172162 U CN208172162 U CN 208172162U CN 201820584583 U CN201820584583 U CN 201820584583U CN 208172162 U CN208172162 U CN 208172162U
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- China
- Prior art keywords
- block
- semiconductor chip
- carrier band
- electrostatic
- pressing plate
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Abstract
The utility model disclose it is a kind of reduction semiconductor chip electrostatic test during electrostatic friction device, including the block one and block two to link together, arc-shaped carrier band slot is provided on block one, block two is equipped with the pressing plate being slidably connected with block two, pressing plate is slidably to the top for carrying slot, and the face of pressing plate towards carrier band slot be it is identical arc-shaped with carrier band groove shape, carrying to be provided on slot can make thimble pass through the centre hole that ejects semiconductor chip.The utility model can reduce the electrostatic friction during semiconductor chip electrostatic test, prevent semiconductor chip failure.
Description
Technical field
The utility model relates to a kind of devices of electrostatic friction during reduction semiconductor chip electrostatic test, for partly leading
In the electrostatic test test of body chip.
Background technique
Since phase mutual friction can generate electrostatic between object and object, electronic component Electronic Performance is be easy to cause under electric shock
Failure, therefore in the production process of semiconductor chip, it needs to carry out electrostatic test to semiconductor chip.Now to semiconductor core
All it is directly to clamp semiconductor chip from carrier band with electrostatic-resisting tweezers when piece progress electrostatic test, is then put into test device
Test.Originally carrier band is put around overlapping together, during the test, since there are phase mutual friction between carrier band, so can generate
Electrostatic causes semiconductor chip failure.
Summary of the invention
In view of the drawbacks of the prior art, the utility model provides electrostatic during a kind of reduction semiconductor chip electrostatic test
The device of friction, it is possible to reduce the electrostatic friction during semiconductor chip electrostatic test prevents semiconductor chip failure.
In order to solve the technical problem, the technical solution adopted in the utility model is：A kind of reduction semiconductor chip is quiet
The device of electrostatic friction in Electrical Test Procedure is provided with arc-shaped including the block one and block two to link together on block one
Carrier band slot, block two is equipped with the pressing plate that is slidably connected with block two, and pressing plate is slidably to the top for carrying slot, and pressing plate court
Face to carrier band slot be it is identical arc-shaped with carrier band groove shape, carrying to be provided on slot can make thimble by by semiconductor chip top
Centre hole out.
The device of electrostatic friction during reduction semiconductor chip electrostatic test described in the utility model, pressing plate is equipped with tight
Fixing bolt is provided with the threaded hole to match with fastening bolt on block two, strip-shaped hole is provided on pressing plate, fastening bolt passes through bar shaped
Hole screws in threaded hole.
The device of electrostatic friction, block one and block during reduction semiconductor chip electrostatic test described in the utility model
Two are bolted together by connection, pass through the width of the adjustable carrier band slot of rotation connection bolt.
The device of electrostatic friction, carries the both ends of slot during reduction semiconductor chip electrostatic test described in the utility model
It is provided with circular arc chamfering.
The device described in the utility model for reducing electrostatic friction during semiconductor chip electrostatic test, is also opened on block one
There is arc groove, rectangular channel is also provided on block two, arc groove and rectangular channel are located at the two sides of carrier band slot.
The beneficial effects of the utility model：The utility model constrains in the carrier band equipped with chip in carrier band slot, makes chip
Between no longer phase mutual friction prevent semiconductor chip from failing because of electrostatic to reduce the generation of electrostatic.It carries and is equipped with pressure above slot
Plate, pressing plate can prevent it is secondary tear open conjunction carrier band when caused by chip fly out, thus effectively control chip fly out.Block one and block
Body two is by being bolted together, by the gap between the adjustable block one of rotation bolt and block two, to adjust
The width for carrying slot, is adapted to the carrier band of different in width.
Detailed description of the invention
Fig. 1 is the schematic perspective view of the utility model；
Fig. 2 is the schematic view of the front view of the utility model；
Fig. 3 is the overlooking structure diagram of the utility model；
Fig. 4 is the structural schematic diagram that Fig. 3 removes fastening bolt；
In figure：1, block one, 2, block two, 3, carrier band slot, 4, pressing plate, 5, fastening bolt, 6, connection bolt, 7, circular arc
Slot, 8, rectangular channel, 9, centre hole, 10, threaded hole, 11, strip-shaped hole.
Specific embodiment
The present invention is further illustrated in the following with reference to the drawings and specific embodiments.
As shown in Figure 1, 2, 3, it is a kind of reduce semiconductor chip electrostatic test during electrostatic friction device, including connection
Block 1 and block 22 together are provided with arc-shaped carrier band slot 3 on block 1, and block 22 is equipped with and block 22
The pressing plate 4 being slidably connected, pressing plate 4 slidably to carry slot 3 top, and pressing plate 4 towards carrier band slot 3 face be and carrier band slot 3
Shape is identical arc-shaped, and carrying to be provided on slot 3 can make thimble pass through the centre hole 9 that ejects semiconductor chip.
As shown in figure 4, pressing plate 4 is equipped with fastening bolt 5, the threaded hole to match with fastening bolt 5 is provided on block 22
10, strip-shaped hole 11 is provided on pressing plate 4, fastening bolt 5 is screwed in threaded hole by strip-shaped hole 11.It, can by screwing fastening bolt 5
To compress pressing plate 4, when unclamping fastening bolt 5, the position of pressing plate can be adjusted with sliding clamp 4.
In the present embodiment, block 1 is linked together with block 22 by connecting bolt 6, connects bolt 6 by rotation
The gap of adjustable block 1 and block 22, to adjust the width of carrier band slot 3.
In order to protect carrier band, the both ends of carrier band slot 3 are provided with circular arc chamfering, prevent that scratch will be carried.
Anti- carrier band and chip are taken for convenience, and arc groove 7 is also provided on block 1, is also provided with rectangular channel 8 on block 22,
Arc groove 7 and rectangular channel 8 are located at the two sides of carrier band slot 3.
Using described in the present embodiment reduction semiconductor chip electrostatic test during electrostatic friction device when, first will carry
Band is placed in carrier band slot 3, and then rotation connection bolt 6, adjusts the gap between block 1 and block 22, i.e. adjustment carrier band
The width of slot 3 fits closely the two sides of carrier band with carrier band slot 3, and carrier band is fixed in carrier band slot 3, then unclamps fastening bolt
5, pressing plate 4 is slid into carrier band top, then again tightens fastening bolt 5, pressing plate 4 is made to be pressed in carrier band top, then with top
Needle is ejected chip by centre hole 9
The utility model constrains in the carrier band equipped with chip in carrier band slot 3, makes no longer phase mutual friction between chip, thus
The generation for reducing electrostatic prevents semiconductor chip from failing because of electrostatic.It carries and is equipped with pressing plate 4 above slot 3, pressing plate 4 can prevent two
It is secondary tear open conjunction carrier band when caused by chip fly out, thus effectively control chip fly out.Block 1 and block 22 pass through connection spiral shell
Bolt 6 links together, by the gap between the rotation connection adjustable block 1 of bolt 6 and block 22, to adjust load
The width of trough of belt 3 is adapted to the carrier band of different in width.
Described above is only the basic principle and preferred embodiment of the utility model, and those skilled in the art are according to this reality
With the novel improvement and replacement made, belong to the protection scope of the utility model.
Claims (5)
1. the device of electrostatic friction during a kind of reduction semiconductor chip electrostatic test, it is characterised in that：Including being connected to one
The block one and block two risen, be provided with arc-shaped carrier band slot on block one, and block two is equipped with to be slidably connected with block two
Pressing plate, pressing plate slidably to carry slot top, and pressing plate towards carrier band slot face be with carrier band groove shape it is identical arc-shaped,
Being provided on carrier band slot can make thimble pass through the centre hole that ejects semiconductor chip.
2. the device of electrostatic friction, feature exist during reduction semiconductor chip electrostatic test according to claim 1
In：Pressing plate is equipped with fastening bolt, is provided with the threaded hole to match with fastening bolt on block two, is provided with strip-shaped hole on pressing plate,
Fastening bolt is screwed in threaded hole by strip-shaped hole.
3. the device of electrostatic friction, feature exist during reduction semiconductor chip electrostatic test according to claim 1
In：Block one is bolted together with block two by connection, and the width of the adjustable carrier band slot of connection rotation bolt is passed through.
4. the device of electrostatic friction, feature exist during reduction semiconductor chip electrostatic test according to claim 1
In：The both ends of carrier band slot are provided with circular arc chamfering.
5. the device of electrostatic friction, feature exist during reduction semiconductor chip electrostatic test according to claim 1
In：It is also provided with arc groove on block one, rectangular channel is also provided on block two, arc groove and rectangular channel are located at the two of carrier band slot
Side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820584583.0U CN208172162U (en) | 2018-04-24 | 2018-04-24 | It is a kind of reduce semiconductor chip electrostatic test during electrostatic friction device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820584583.0U CN208172162U (en) | 2018-04-24 | 2018-04-24 | It is a kind of reduce semiconductor chip electrostatic test during electrostatic friction device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208172162U true CN208172162U (en) | 2018-11-30 |
Family
ID=64370371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820584583.0U Active CN208172162U (en) | 2018-04-24 | 2018-04-24 | It is a kind of reduce semiconductor chip electrostatic test during electrostatic friction device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208172162U (en) |
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2018
- 2018-04-24 CN CN201820584583.0U patent/CN208172162U/en active Active
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