CN208126877U - The high-speed receiver circuit of DDR4 standard - Google Patents
The high-speed receiver circuit of DDR4 standard Download PDFInfo
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- CN208126877U CN208126877U CN201820634282.4U CN201820634282U CN208126877U CN 208126877 U CN208126877 U CN 208126877U CN 201820634282 U CN201820634282 U CN 201820634282U CN 208126877 U CN208126877 U CN 208126877U
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- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 title claims abstract description 22
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Abstract
The utility model provides a kind of input sink circuit of DDR4 standard, including the first transistor MP1, second transistor MP2, third transistor MP3, the 4th transistor MP4, the 5th transistor MP5, the 6th transistor MN1, the 7th transistor MN2, the 8th transistor MN3, the 9th transistor MN4, the first phase inverter, the second reverser, third phase inverter and the 4th phase inverter, wherein MN4, MP5 form duty ratio adjusting circuit, for improving output duty cycle.The DDR4 standard high-speed receiver circuit of the utility model has many advantages, such as that structure is simple, transmission bandwidth is high, transmission delay is small.
Description
Technical field
The utility model relates to IC design technology more particularly to a kind of high-speed receiver circuits of DDR4 standard.
Background technique
High density dynamic memory（DRAM）The bandwidth and interface rate of bus are to measure the important indicator of system performance, work
The boundary of the continuous moving system design limitation of industry, to realize higher memory interface message transmission rate.DDR4 SDRAM
It all improves a lot than DDR3 SDRAM before in capacity, rate and compatibility, is widely used in many fields,
But there are still many problems for the design of DDR4 acceptor circuit, such as：Due to the difference and transmission rate of level standard
It improves, traditional DDR3 criteria receiver circuit structure has not been suitable for the design of DDR4 criteria receiver；What other people designed
The circuit structure of DDR4 criteria receiver is complex, amplifies processing to input signal using multiple differential amplifier, and
Additional bias-voltage generating circuit is needed to have, haves the shortcomings that chip area is big, delay is big and power consumption is high, and output signal
Duty ratio is affected by process deviation, temperature change and voltage fluctuation.
Utility model content
The DDR4 standard that the purpose of this utility model is to provide a kind of structures is simple, transmission bandwidth is high, transmission delay is small
High-speed receiver circuit.
The technical solution for realizing the aim of the invention is as follows：A kind of input sink circuit of DDR4 standard, including first
Transistor MP1, second transistor MP2, third transistor MP3, the 4th transistor MP4, the 5th transistor MP5, the 6th transistor
MN1, the 7th transistor MN2, the 8th transistor MN3, the 9th transistor MN4, the first phase inverter, the second reverser, third reverse phase
Device and the 4th phase inverter, wherein the first transistor MP1 grid, which connects, makes can control the end IE, and drain electrode meets third transistor MP3, the 6th crystalline substance
Body pipe MN1 drain electrode, source electrode meet supply voltage VDD；Second transistor MP2 grid, which connects, makes can control the end IE and the input of the 4th phase inverter
End, drain electrode connects the 4th transistor MP4, the 7th transistor MN2 drain electrode and the first inverter input, source electrode meet supply voltage VDD；
After third transistor MP3 grid and drain electrode are shorted, the first transistor MP1, the 7th transistor MN2 drain electrode are connect, source electrode connects power supply electricity
Press VDD；4th transistor MP4 grid connects third transistor MP3 grid, and drain electrode meets second transistor MP2, the 7th transistor MN2
Drain electrode and the first inverter input, source electrode meet supply voltage VDD；5th transistor MP5 grid connects the 4th inverter output,
Drain electrode connects the 9th transistor MN4 drain electrode, and source electrode meets supply voltage VDD；6th transistor MN1 grid connects INN input, and drain electrode connects the
One transistor MP1, third transistor MP3 drain electrode, source electrode connect the 7th transistor MN2 source electrode and the 8th transistor MN3 drain electrode；7th
Transistor MN2 grid connects INP input, and drain electrode connects second transistor MP2, the 4th transistor MP4 drain electrode and the input of the first phase inverter
End, source electrode connect the 6th transistor MN1 source electrode and the 8th transistor MN3 drain electrode；8th transistor MN3 grid connects the port IE, drain electrode
Connect the 6th transistor MN1, the 7th transistor MN2 source electrode, source electrode ground connection；9th transistor MN4 grid connects the input of first direction device
End, drain electrode connect the 5th transistor MP5 drain electrode, and source electrode connects the second inverter output and third inverter input, the first reverse phase
Device output the second inverter input of termination.
Further, the first transistor MP1, second transistor MP2, third transistor MP3, the 4th transistor MP4,
5th transistor MP5 is P-type transistor.
Further, the first transistor MP1, second transistor MP2, third transistor MP3, the 4th transistor
MP4 is the thin grid P-type transistor in core power domain, and circuit transmission bandwidth can be improved, and reduces transmission delay.
Further, the 6th transistor MN1, the 7th transistor MN2, the 8th transistor MN3, the 9th transistor MN4
It is N-type transistor.
Further, the 6th transistor MN1, the 7th transistor MN2 are the thick grid N-type transistor of I/O power domain,
It can guarantee that circuit can be worked normally in high voltage domain（The domain IO）.
Further, first phase inverter, the second phase inverter and third phase inverter are CMOS inverter.
Further, the 4th phase inverter is TTL not circuit.
Compared with prior art, remarkable advantage is the utility model：1）The DDR4 circuit structure of the utility model is simple,
Reduce number of elements and chip area；2）A pair of of difference pipe N pipe in the utility model difference amplifier uses I O power supply domain
Thick gate transistor, P pipe use the thin gate transistor of kernel low voltage domain, and I O power supply domain thickness grid difference N pipe guarantees that circuit can normal work
Make in high voltage domain（The domain IO）, the thin gate transistor of kernel low voltage domain can be improved circuit transmission bandwidth, reduces transmission delay；3）
Duty ratio, which is added, in the utility model between signal wire OUT1 and OUT3 improves circuit, makes entire circuit in technological parameter, environment temperature
In the case that degree and supply voltage change, it is still able to maintain more stable duty ratio, improves memory reading performance.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the high-speed receiver circuit of the utility model DDR4 standard.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the utility model is further illustrated.
The high-speed receiver circuit of DDR4 standard provided by the utility model, including difference amplifier, buffer, duty ratio
Circuit and output four parts of phase inverter are adjusted, wherein：
（1）Difference amplifier includes forming two groups of mirror current sources by the thin grid P-type transistor in four core power domains, by
Thick grid N-type transistor MN1, MN2 of two I/O power domains forms basic differential pair（Coupling pair）, and by a N-type transistor
Pipe MN3 forms tail current source, for providing bias current for differential pair, inhibits the variation of input common mode electrical level to MN1, MN2
Work and the influence of output level.
（2）Buffer：It is made of two groups of phase inverters, plays the role of buffering, delay.
（3）Duty ratio adjusting circuit：It is made of MN4, MP5, for improving output duty cycle.
（4）Phase inverter is exported, for amplifying the high potential signal from circuit output, it is ensured that output circuit there are enough drives
It is dynamic.
The high-speed receiver circuit particular circuit configurations of DDR4 standard are as shown in Figure 1, include the first transistor MP1, second
Transistor MP2, third transistor MP3, the 4th transistor MP4, the 5th transistor MP5, the 6th transistor MN1, the 7th transistor
MN2, the 8th transistor MN3, the 9th transistor MN4, the first phase inverter, the second reverser, third phase inverter and the 4th phase inverter,
Wherein the first transistor MP1 grid, which connects, makes can control the end IE, and drain electrode connects third transistor MP3, the 6th transistor MN1 drain electrode, source
Pole meets supply voltage VDD；Second transistor MP2 grid, which connects, makes can control the end IE and the 4th inverter input, and drain electrode connects the 4th
Transistor MP4, the 7th transistor MN2 drain electrode and the first inverter input, source electrode meet supply voltage VDD；Third transistor MP3
After grid and drain electrode are shorted, the first transistor MP1, the 7th transistor MN2 drain electrode are connect, source electrode meets supply voltage VDD；4th crystal
Pipe MP4 grid connects third transistor MP3 grid, and drain electrode connects second transistor MP2, the 7th transistor MN2 drain electrode and the first reverse phase
Device input terminal, source electrode meet supply voltage VDD；5th transistor MP5 grid connects the 4th inverter output, and drain electrode connects the 9th crystal
Pipe MN4 drain electrode, source electrode meet supply voltage VDD；6th transistor MN1 grid connects INN input, and drain electrode meets the first transistor MP1, the
Three transistor MP3 drain electrode, source electrode connect the 7th transistor MN2 source electrode and the 8th transistor MN3 drain electrode；7th transistor MN2 grid
INP input is connect, drain electrode connects second transistor MP2, the 4th transistor MP4 drain electrode and the first inverter input, source electrode connect the 6th
Transistor MN1 source electrode and the 8th transistor MN3 drain electrode；8th transistor MN3 grid connects the port IE, and drain electrode connects the 6th transistor
MN1, the 7th transistor MN2 source electrode, source electrode ground connection；9th transistor MN4 grid connects first direction device input terminal, and drain electrode connects the 5th
Transistor MP5 drain electrode, source electrode connect the second inverter output and third inverter input, and the first inverter output connects second
Inverter input.The utility model MP4 grid end connects OU1 signal wire, and source connects the output of second level phase inverter, i.e. OUT3 signal
Line, being added between signal wire OUT1 and OUT3 improves circuit by the duty ratio that MN4, MP5 are formed, in differential amplification output signal
After OUT1, signal is divided into two-way：The first via passes through two-stage inverter drive OUT3 point, and the second tunnel directly drives the N pipe of pull-up,
The level of OUT3 point is drawn high in the delay of two-stage phase inverter in advance in advance, reaches the function of improving duty ratio；Meanwhile duty ratio mentions
The delay of increasing degree degree and two-stage phase inverter is directly proportional, if you need to increase the ability of duty cycle adjustment, can increase between OUT1 to OUT3
The series of phase inverter.
Wherein, the first transistor MP1, second transistor MP2, third transistor MP3, the 4th transistor MP4, the 5th crystal
Pipe MP5 is P-type transistor.The first transistor MP1, second transistor MP2, third transistor MP3, the 4th transistor MP4 are interior
Circuit transmission bandwidth can be improved in the thin grid P-type transistor of nuclear power source domain, reduces transmission delay.6th transistor MN1, the 7th
Transistor MN2, the 8th transistor MN3, the 9th transistor MN4 are N-type transistors.6th transistor MN1, the 7th transistor MN2
For the thick grid N-type transistor of I/O power domain, it is ensured that circuit can be worked normally in high voltage domain（The domain IO）.First phase inverter,
Second phase inverter and third phase inverter are CMOS inverter.4th phase inverter is TTL not circuit.
The working principle of the utility model is as follows：
INN=Vref provides reference voltage to INP, guarantees that MN1 is in the open state always；
When IE=0, MP1, MP2 are opened, and MP5 is closed, and MN3 is closed, and circuit can not work normally, and no matter what INP, which takes over, is believed
Number, output end OUT is not impacted, OUT perseverance is 0；
When IE=1, MP1, MP2 are closed, and MN3 is opened, and circuit is in running order；
When INP=0, MN2 is closed, and MP3 is opened, and MP4 is closed, and MN3 is closed, signal wire OUT1=0, by two groups of phase inverters,
Output end OUT=0；
When INP=1, MN2 is opened, and MP3 is closed, and MP4 is opened, and MN3 is opened, signal wire OUT1=1, by two groups of phase inverters,
Output end OUT=1.
Claims (7)
1. a kind of high-speed receiver circuit of DDR4 standard, which is characterized in that including the first transistor MP1, second transistor
MP2, third transistor MP3, the 4th transistor MP4, the 5th transistor MP5, the 6th transistor MN1, the 7th transistor MN2,
Eight transistor MN3, the 9th transistor MN4, the first phase inverter, the second reverser, third phase inverter and the 4th phase inverter, wherein the
One transistor MP1 grid, which connects, makes can control the end IE, and drain electrode connects third transistor MP3, the 6th transistor MN1 drain electrode, and source electrode connects electricity
Source voltage VDD；Second transistor MP2 grid, which connects, makes can control the end IE and the 4th inverter input, and drain electrode connects the 4th transistor
MP4, the 7th transistor MN2 drain electrode and the first inverter input, source electrode meet supply voltage VDD；Third transistor MP3 grid and
After drain electrode is shorted, the first transistor MP1, the 7th transistor MN2 drain electrode are connect, source electrode meets supply voltage VDD；4th transistor MP4
Grid connects third transistor MP3 grid, and drain electrode connects second transistor MP2, the 7th transistor MN2 drain electrode and the input of the first phase inverter
End, source electrode meet supply voltage VDD；5th transistor MP5 grid connects the 4th inverter output, and drain electrode meets the 9th transistor MN4
Drain electrode, source electrode meet supply voltage VDD；6th transistor MN1 grid connects INN input, and it is brilliant that drain electrode connects the first transistor MP1, third
Body pipe MP3 drain electrode, source electrode connect the 7th transistor MN2 source electrode and the 8th transistor MN3 drain electrode；7th transistor MN2 grid meets INP
Input, drain electrode connects second transistor MP2, the 4th transistor MP4 drain electrode and the first inverter input, source electrode connect the 6th transistor
MN1 source electrode and the 8th transistor MN3 drain electrode；8th transistor MN3 grid connects the port IE, and drain electrode meets the 6th transistor MN1, the 7th
Transistor MN2 source electrode, source electrode ground connection；9th transistor MN4 grid connects first direction device input terminal, and drain electrode connects the 5th transistor
MP5 drain electrode, source electrode connect the second inverter output and third inverter input, and the first inverter output connects the second reverser
Input terminal.
2. the high-speed receiver circuit of DDR4 standard according to claim 1, which is characterized in that the first transistor
MP1, second transistor MP2, third transistor MP3, the 4th transistor MP4 and the 5th transistor MP5 are P-type transistors.
3. the high-speed receiver circuit of DDR4 standard according to claim 1, which is characterized in that the first transistor
MP1, second transistor MP2, third transistor MP3 and the 4th transistor MP4 are the thin grid P-type transistor in core power domain.
4. the high-speed receiver circuit of DDR4 standard according to claim 1, which is characterized in that the 6th transistor
MN1, the 7th transistor MN2, the 8th transistor MN3 and the 9th transistor MN4 are N-type transistors.
5. the high-speed receiver circuit of DDR4 standard according to claim 1, which is characterized in that the 6th transistor
MN1 and the 7th transistor MN2 is the thick grid N-type transistor of I/O power domain.
6. the high-speed receiver circuit of DDR4 standard according to claim 1, which is characterized in that first phase inverter,
Second phase inverter and third phase inverter are CMOS inverter.
7. the high-speed receiver circuit of DDR4 standard according to claim 1, which is characterized in that the 4th phase inverter is
TTL not circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820634282.4U CN208126877U (en) | 2018-04-29 | 2018-04-29 | The high-speed receiver circuit of DDR4 standard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820634282.4U CN208126877U (en) | 2018-04-29 | 2018-04-29 | The high-speed receiver circuit of DDR4 standard |
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| Publication Number | Publication Date |
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| CN208126877U true CN208126877U (en) | 2018-11-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201820634282.4U Withdrawn - After Issue CN208126877U (en) | 2018-04-29 | 2018-04-29 | The high-speed receiver circuit of DDR4 standard |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108305648B (en) * | 2018-04-29 | 2023-12-19 | 山东泉景胜跃信息技术有限公司 | DDR4 standard high-speed receiver circuit |
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2018
- 2018-04-29 CN CN201820634282.4U patent/CN208126877U/en not_active Withdrawn - After Issue
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108305648B (en) * | 2018-04-29 | 2023-12-19 | 山东泉景胜跃信息技术有限公司 | DDR4 standard high-speed receiver circuit |
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