CN208092715U - A kind of ARM platform I/O Interface status detection devices based on CPLD - Google Patents
A kind of ARM platform I/O Interface status detection devices based on CPLD Download PDFInfo
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- CN208092715U CN208092715U CN201820350725.7U CN201820350725U CN208092715U CN 208092715 U CN208092715 U CN 208092715U CN 201820350725 U CN201820350725 U CN 201820350725U CN 208092715 U CN208092715 U CN 208092715U
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Abstract
A kind of ARM platform I/O Interface status detection devices based on CPLD disclosed by the utility model, its CPLD has the first I/O interfaces being connected with the I/O interfaces of ARM controller, the 2nd I/O interfaces, the GPI interface being connected with controlled device, signal judging unit is connect with the GPI interfaces of CPLD and the 2nd I/O interfaces respectively, serial shift register unit is connect with the first I/O interfaces, and ARM controller is connected by the GPO interfaces of itself, the GPI interfaces of CPLD with signal judging unit.The utility model carries out the I/O transmission and self-test of signal using CPLD, and when ARM platform output signal mistakes, which can be arrived using signal judging unit contrasting detection；And realization I/O controls are gone by software code due to not needing ARM platforms, the safety of I/O controls is greatly improved, the security isolation of I/O control and other software logic is realized.
Description
Technical field
The utility model belongs to detection circuit technical field, and in particular to a kind of ARM platform I/O interface shapes based on CPLD
State detection device.
Background technology
Complex Programmable Logic Devices (Complex Programmable Logic Device, abbreviation CPLD), be from
The device that PAL and GAL device developments come out.It is a kind of user according to respective the need and voluntarily digital integration of constitutive logic function
Code is transmitted in objective chip by download cable, realizes the digital display circuit of design by circuit.
ARM platforms are the processors based on ARM frameworks and the control operation platform designed, are widely used in intelligent hand at present
The fields such as machine, Industry Control, robot, artificial intelligence, embedded server, Internet of Things, special computer, ARM processing platforms
Have become one of the basal core of informationized society.
And input/output (Input/Output, abbreviation I/O) interface is then the control of all signals and acquisition is most basic connects
Mouth mode.
I/O interfaces have been commonly used as a kind of most basic one of control mode signal in various occasions.ARM is flat
The I/O interfaces that platform has using itself come realize the bottom signal control, greatly facilitate user based on ARM platforms to open
Send out, design the intelligent control system of various occasions.
But the input and output of I/O interfaces, due to extremely simple, on the one hand it has provided great convenience to the user, together
When on the other hand, in the environment of some high reliability requests, due to I/O interfaces do not have self detection self diagnosis energy
Power, when program software code logic error occur in I/O interfaces, whole system is all by the state in logic error, sternly
System crash is resulted even in the case of weight.In the field of certain high reliability requests, such as in nuclear power, aerospace, height
The relevant field of the life securities such as iron can cause serious social safety accident.
Utility model content
The ARM platform I/O Interface status detection devices based on CPLD that the purpose of this utility model is to provide a kind of solve
The I/O interfaces of existing ARM platforms lead to that the problem of logic error can not be found occurs due to cannot be self-detected.
Technical solution used by the utility model is：A kind of ARM platform I/O Interface status detection dress based on CPLD
It sets, including CPLD, the CPLD has the first I/O interfaces being connected with the I/O interfaces of ARM controller, is connected with controlled device
The 2nd I/O interfaces, GPI interfaces, the CPLD includes the connected signal judging unit of signal and serial shift register unit,
The signal judging unit is connect with the GPI interfaces of CPLD and the 2nd I/O interfaces respectively, the serial shift register unit with
First I/O interface signals connect, and the ARM controller is sentenced by the GPO interfaces of itself, GPI interfaces and the signal of CPLD
Disconnected unit is connected.
Further, the CPLD also has GPO interfaces, the GPO interfaces that the signal judging unit passes through the CPLD
Connection is connect with the GPI interface signals of ARM controller.
Further, when judging ARM platform I/O Interface status exceptions, the signal judging unit is connect by the 2nd I/O
Mouth control exports preset safety level signal.
Further, the CPLD also has enabling pulse interface, the signal judging unit and enabling pulse interface phase
Even, the ARM controller sends trigger signal by a GPO interface, enabling pulse interface to signal judging unit.
The utility model has the beneficial effects that：A kind of ARM platform I/O Interface status inspection based on CPLD of the utility model
It surveys device and solves the problems, such as that the I/O interfaces of existing ARM platforms cause generation logic error that can not find due to cannot be self-detected.
Due to carrying out the I/O transmission and self-test of signal using CPLD, when ARM platform output signal mistakes, which can profit
It is arrived with signal judging unit contrasting detection, to make system enter safe mode according to preset mode in time；And due to being not required to
It wants ARM platforms to go to realize I/O controls by software code, greatly improves the safety of I/O controls, realize I/O controls
With the security isolation of other software logic.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of the ARM platform I/O Interface status detection devices based on CPLD of the utility model.
In figure, 1.CPLD, 2.ARM controllers, 11. signal judging units, 12. shift register cells.
Specific implementation mode
The utility model is described in detail with reference to the accompanying drawings and detailed description.
A kind of ARM platform I/O Interface status detection devices based on CPLD provided by the utility model, structure such as Fig. 1
It is shown, including CPLD1, CPLD1 have the first I/O interfaces being connected with the I/O interfaces of ARM controller 2, be connected with controlled device
The 2nd I/O interfaces, universal input (General Purpose Input, abbreviation GPI) interface, CPLD1 include signal be connected
Signal judging unit 11 and serial shift register unit 12, signal judging unit 11 respectively with the GPI interfaces of CPLD1 and second
I/O interfaces connect, and serial shift register unit 12 is connect with the first I/O interface signals, and ARM controller 2 passes through the logical of itself
With the GPI interfaces and 11 phase of signal judging unit of output (General Purpose Output, abbreviation GPO) interface, CPLD1
Even.
Further, also there is CPLD1 GPO interfaces, signal judging unit 11 to pass through the GPO interfaces connection of CPLD1 and ARM
The GPI interface signals of controller 2 connect, and when signal judging unit 11 detects 2 output signal exception of ARM controller, then lead to
The signal link is crossed to be fed back to ARM controller 2.
Further, when judging ARM platform I/O Interface status exceptions, signal judging unit 11 passes through the 2nd I/O interfaces
Control exports preset safety level signal, which is preset high level or low level, signal judging unit
11, by exporting the safety level signal, avoid the error signal of ARM controller 2 being output to controlled device.
Further, also there is CPLD1 enabling pulse interface, signal judging unit 11 to be connected with enabling pulse interface, ARM
Controller 2 sends trigger signal by a GPO interface, enabling pulse interface to signal judging unit 11.To be controlled in ARM
When 2 transmission data of device processed, the pulse triggering signal not less than 100us, signal when triggering are sent to signal judging unit 11
Judging unit 11 is completed signal and is judged and according to judging structure output signal.
The data conversion that serial shift register unit 12 is responsible for inputting ARM controller 2 by I/O interface serials is at simultaneously
Row data are simultaneously transferred to signal judging unit 11, and signal judging unit 11 is logical by the GPI interfaces ARM controller 2 of CPLD1
The parallel data for crossing the output of its GPO interface is then responsible for comparing serial shift register unit 12 and the GPO from ARM controller 2
Whether the signal of interface input is consistent, illustrates that ARM controller 2 is working properly if consistent, then just by the 2nd I/O interfaces
Normal output signal；It is inputted if there is any Bits Serial shift register cell 12 and from the GPO interfaces of ARM controller 2
Signal mismatch then thinks there is exception, and the 2nd all output signals of I/O interfaces are switched to safety level state.
When the utility model is detected ARM platform I/O Interface status, GPI that ARM controller passes through its GPO, CPLD
Interface to signal judging unit export parallel data, by I/O interfaces, the first I/O interfaces to shift register cell output pair
The serial data and synchronizing signal answered, shift register cell convert serial data to parallel data transmission and judge list to signal
Member, while ARM controller exports one by the enabling pulse interface of an other GPO interface, CPLD to signal judging unit
The pulse signal of a triggering, the parallel data and shift register cell that trigger signal judging unit sends ARM controller pass
Defeated parallel data is compared, if data unanimously if judge transmit signal it is normal, signal judging unit is connect by the 2nd I/O
Mouthful to controlled device transmission signal；If it is inconsistent, judging abnormal signal, then signal judging unit is exported to controlled device
Safety level signal, at the same it is abnormal to ARM controller feedback signal by the GPI interfaces of the GPO interfaces of CPLD, ARM controller
Information.
CPLD is become the special hardware of a control I/O interface by the detection device of the utility model, because I/O connects
Mouthful control institute it is stateful have become cure after hardware device, do not need additional software program and go to control, from without
It wants ARM platforms to go to realize I/O controls by software code, greatly improves the safety of I/O controls, realize I/O controls
With the security isolation of other software logic.Moreover, after by the way that I/O controls are passed through CPLD Hardwares, in certain extreme feelings
Under condition, for example ARM platforms crash, restart, program crashing etc., and when there is the above extreme case, arm processor is to be in
Off position, at this point, the I/O states of ARM controller will be situation about being expected in an out of order or non-program, and ARM
I/O be to be interconnected with the I/O of CPLD, CPLD can monitor that the I/O of ARM is in an out of order state, so as to control
Output safety level signal processed, or so that system is entered and safe mode is set in CPLD by user in advance, for example controlled by CPLD
System restarts power supply or CPLD and the state of I/O is restored to factory mode etc..
The preferred embodiment of the utility model described in detail above.It should be appreciated that the ordinary skill people of this field
Member according to the present utility model can conceive without creative work makes many modifications and variations.Therefore, all this technology necks
Technical staff passes through logic analysis, reasoning or limited reality on the basis of existing technology according to the design of the utility model in domain
Available technical solution is tested, it all should be in the protection domain being defined in the patent claims.
Claims (4)
1. a kind of ARM platform I/O Interface status detection devices based on CPLD, which is characterized in that including CPLD, the CPLD tools
There are the first I/O interfaces being connected with the I/O interfaces of ARM controller, the 2nd I/O interfaces, the GPI interface being connected with controlled device,
The CPLD includes the connected signal judging unit of signal and serial shift register unit, the signal judging unit respectively with
The GPI interfaces of CPLD and the connection of the 2nd I/O interfaces, the serial shift register unit are connect with the first I/O interface signals, institute
ARM controller is stated by the GPO interfaces of itself, the GPI interfaces of CPLD to be connected with the signal judging unit.
2. a kind of ARM platform I/O Interface status detection devices based on CPLD as described in claim 1, which is characterized in that institute
Stating CPLD also has GPO interfaces, the GPI that the signal judging unit passes through GPO the interfaces connection and ARM controller of the CPLD
Interface signal connects.
3. a kind of ARM platform I/O Interface status detection devices based on CPLD as described in claim 1, which is characterized in that when
When judging ARM platform I/O Interface status exceptions, the signal judging unit exports preset peace by the 2nd I/O Interface Controllers
Full level signal.
4. a kind of ARM platform I/O Interface status detection devices based on CPLD as described in claim 1, which is characterized in that institute
Stating CPLD, also there is enabling pulse interface, the signal judging unit to be connected with enabling pulse interface, and the ARM controller passes through
One GPO interface, enabling pulse interface send trigger signal to signal judging unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820350725.7U CN208092715U (en) | 2018-03-14 | 2018-03-14 | A kind of ARM platform I/O Interface status detection devices based on CPLD |
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| CN201820350725.7U CN208092715U (en) | 2018-03-14 | 2018-03-14 | A kind of ARM platform I/O Interface status detection devices based on CPLD |
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| CN208092715U true CN208092715U (en) | 2018-11-13 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109656767A (en) * | 2018-12-21 | 2019-04-19 | 广东浪潮大数据研究有限公司 | A kind of acquisition methods, system and the associated component of CPLD status information |
-
2018
- 2018-03-14 CN CN201820350725.7U patent/CN208092715U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109656767A (en) * | 2018-12-21 | 2019-04-19 | 广东浪潮大数据研究有限公司 | A kind of acquisition methods, system and the associated component of CPLD status information |
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Legal Events
| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Room 314, Room 333 Jiufojian Road, Zhongxin Guangzhou Knowledge City, Guangzhou, Guangdong 510000 Patentee after: Guangdong Hanwei Information Technology Co.,Ltd. Address before: Room 314, Room 333 Jiufojian Road, Zhongxin Guangzhou Knowledge City, Guangzhou, Guangdong 510000 Patentee before: GUANGDONG HANWEI INTEGRATED TECHNOLOGY CO.,LTD. |
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| CP01 | Change in the name or title of a patent holder | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A CPLD based i/o interface state detection device for arm platform Effective date of registration: 20220623 Granted publication date: 20181113 Pledgee: CITIC Bank Co.,Ltd. Guangzhou Branch Pledgor: Guangdong Hanwei Information Technology Co.,Ltd. Registration number: Y2022440000127 |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right |