CN208046756U

CN208046756U - video display processing device

Info

Publication number: CN208046756U
Application number: CN201820385838.0U
Authority: CN
Inventors: 陈水忠; 王炜; 陈腾
Original assignee: Luoyang Institute of Electro Optical Equipment AVIC
Current assignee: Luoyang Institute of Electro Optical Equipment AVIC
Priority date: 2018-03-21
Filing date: 2018-03-21
Publication date: 2018-11-02
Anticipated expiration: 2028-03-21

Abstract

The utility model is related to video display processing devices；Including GPU, FPGA and SSD solid state disk, GPU is attached by PCIe switch and FPGA and SSD solid state disks；FPGA is equipped with the video acquisition port for acquiring external video, and FPGA is passed through collected outer video in PCIe bus transfers to GPU by video acquisition port；SSD solid state disks send it to GPU for storing 3-D information by PCIe buses；GPU includes DVI output ports, and video information output will be carried out after the outer video received, 3-D information superpositions for GPU.Multi-functional, the high performance embedded gpu platform being arranged in the utility model has the characteristics that complexity 3-D maps, video superposition, video display real-time height etc. can be drawn, improves the processing capacity of figure so that the real-time higher that video is shown.

Description

Video display processing device

Technical field

The utility model is related to video display processing devices, belong to avionic device field of display systems.

Background technology

With the development of Digital image technology and multimedia information technology, the application of mass image data is more and more common, Wherein, the display rendering technique in avionics system is also particularly important.Currently, the graphics process frame of avionics system Structure is to be based on FPGA+DSP platforms；But as graphic intensive is using such as 3-D draftings, target identification, radar information processing pair The raising of mass data computation capability, high-speed video stream process Capability Requirement, to showing drafting in avionics system The graphics capability of equipment, more stringent requirements are proposed for display real-time.Existing graphics process framework has been unable to meet sea Graphics data parallel processing demand, causes the processing capacity of figure relatively low.

Utility model content

The purpose of this utility model is to provide a kind of video display processing devices, to solve existing graphics process frame Structure cannot meet method of massive graphic data parallel processing demand, cause the processing capacity of figure it is relatively low, display when drawing ability it is low, aobvious Show the not high problem of real-time.

To achieve the above object, the utility model provides a kind of video display processing device, includes mainly following scheme：

Display processing unit scheme one：Including GPU, FPGA and SSD solid state disk, the GPU by PCIe switch with FPGA and SSD solid state disks are attached；

The FPGA is equipped with the video acquisition port for acquiring external video, and the FPGA leads to collected outer video It crosses in PCIe bus transfers to GPU；

The 3-D information of storage is sent to GPU by the SSD solid state disks by PCIe buses；

The GPU includes DVI output ports, and the GPU will pass through described after the outer video received, 3-D information superpositions DVI output ports are exported.

Display processing unit scheme two：Further include processor CPU on the basis of display processing unit scheme one, it is described CPU is connect with PCIe switch.

Display processing unit scheme three：On the basis of display processing unit scheme two, described GPU, FPGA, CPU, PCIe Interchanger and SSD solid state disks are arranged on VPX standard hardware boards.

Display processing unit scheme four：On the basis of display processing unit scheme three, the VPX standard hardwares board is also VPX connectors are provided with, include debugging interface, communication interface, the debugging interface, communication interface point on the VPX connectors Do not connect with CPU, for realizing to board on-line debugging and PC machine communication.

Display processing unit scheme five：On the basis of display processing unit scheme four, the GPU passes through DVI output ends Mouth is connect with VPX connectors, and the video information after superposition is carried out output by VPX connectors to be shown.

Display processing unit scheme six：On the basis of display processing unit scheme one, the GPU decodes core by DVI Piece is connect with FPGA；The FPGA further includes the video output terminals for exporting the decoded video information received Mouthful.

Display processing unit scheme seven：On the basis of display processing unit scheme six, the FPGA uses ARINC818 Protocol bus completes the acquisition and output of video.

The utility model has the beneficial effects that：The utility model in order to meet the needs of to high performance graphics processing capacity, It is flat that the graphics process framework of avionics system from FPGA adds DSP platform to be gradually transitions multi-functional, high performance embedded gpu Platform is improved to mass data computation capability, high-speed video stream process ability.

Description of the drawings

Fig. 1 is video acquisition display processing unit structure diagram.

Specific implementation mode

The utility model is described in further detail below in conjunction with the accompanying drawings.

Fig. 1 is the most preferred video display processing device schematic diagram of the utility model, which includes being arranged at one piece 6U sizes, GPU, CPU, FPGA, SSD solid state disk on VPX standard hardware boards, PCIe switch and VPX connectors.

Wherein, GPU is attached by PCIe switch and FPGA and SSD solid state disks；FPGA is equipped with outer for acquiring Collected outer video is passed through PCIe bus transfers to GPU by the video acquisition port of portion's video and video-out port later In；SSD solid state disks send it to GPU for storing 3-D information by PCIe buses；GPU outer is regarded what is received Frequently, 3-D information is overlapped the video information after being superimposed.

GPU in the present embodiment includes DVI output ports, and GPU is connect by DVI output ports with VPX connectors, and will Video information after superposition carries out output by VPX connectors and shows.

Meanwhile the GPU in the present embodiment is also connect by DVI decoding chips with FPGA, for the video letter after being superimposed Breath is sent to FPGA after being decoded；FPGA by the video-out port of itself by the decoded video information received into Row output display.Therefore, because GPU chips can support 6 road video display outputs, the video information after being superimposed in the device is shown Show that can while carry out output by above-mentioned 2 kinds of modes shows.

Certainly, it as other embodiment, only can directly be exported through VPX connectors by the video information being superimposed in GPU DVI videos show and can also meet the requirements.Similarly, the video after superposition is only sent to by FPGA by DVI decoding chips, Video data directly exports display through video-out port and can also meet the requirements in FPGA.

FPGA is acquisition and the output display for carrying out data through optical fiber according to ARINC818 agreements in the present embodiment.Together When, FPGA can also directly read outer video, i.e. conduct when carrying out outer video acquisition from the DVI input interfaces of VPX connectors ARINC818 buses receive the backup of outer video.

Processor CPU in the present embodiment is connect as PCIe architecture for exchanging root nodes with PCIe switch, is handed over PCIe Bus of changing planes is controlled；And CPU plays control action to the data transmission of whole device.Processor CPU is total by Local bus Line is connect with programmable logic chip CPLD, and CPLD completes Local bus address/data bus demultiplexing, resets distribution function.

Further include debugging interface, communication interface on VPX connectors in the present embodiment, debugging interface therein, communication connect Mouthful connect respectively with CPU, for realizing to board on-line debugging and PC machine communication, control of the completion to board, status information It reads.

The course of work of the device is：FPGA receives the outer of ARINC818 bus transfers by video acquisition port through optical fiber Video, and outer video is sent to by GPU by the end-to-end transmission of PCIe, it is stored in GPU video memorys.SSD solid state disks are for depositing 3-D cartographic informations are stored up, and GPU is sent it to by PCIe buses.GPU draw 2-D, 3-D graphical symbol, and with outer video, 3-D cartographic informations are overlapped, and are all the way exported the video information after superposition through VPX connectors by the DVI output ports of GPU And it shows；Another way GPU is sent to FPGA by DVI decoding chips after being decoded the video information after superposition；FPGA is logical It crosses the video-out port of itself the decoded video information received is subjected to output and show.

GPU chip type selectings in the present embodiment are Advanced Micro Devices Radeon series E8860, complete video superposition, 2-D or 3-D The key functions such as symbol plotting, video processing.

The utility model is described in the above combination attached drawing, but the utility model be not limited to it is above-mentioned Specific implementation mode, is not departing from the utility model aims and scope of the claimed protection, can also make very much Deformation, these both are within the protection scope of the present invention.

Claims

1. a kind of video display processing device, which is characterized in that including GPU, FPGA and SSD solid state disk, the GPU passes through PCIe switch is attached with FPGA and SSD solid state disks；

The FPGA is equipped with the video acquisition port for acquiring external video, and the FPGA passes through collected outer video In PCIe bus transfers to GPU；

The GPU includes DVI output ports, and the GPU will be defeated by the DVI after the outer video received, 3-D information superpositions Exit port is exported.

2. video display processing device according to claim 1, which is characterized in that further include processor CPU, the CPU It is connect with PCIe switch.

3. video display processing device according to claim 2, which is characterized in that described GPU, FPGA, CPU, PCIe are handed over It changes planes and SSD solid state disks is arranged on VPX standard hardware boards.

4. video display processing device according to claim 3, which is characterized in that the VPX standard hardwares board is also set VPX connectors are equipped with, include debugging interface, communication interface, the debugging interface, communication interface difference on the VPX connectors Connect with CPU, for realizing to board on-line debugging and PC machine communication.

5. video display processing device according to claim 4, which is characterized in that the GPU by DVI output ports with VPX connectors connect, and the video information after superposition is carried out output by VPX connectors and is shown.

6. video display processing device according to claim 1, which is characterized in that the GPU by DVI decoding chips with FPGA connections；The FPGA further includes the video-out port for exporting the decoded video information received.

7. video display processing device according to claim 6, which is characterized in that the FPGA uses ARINC818 agreements Bus completes the acquisition and output of video.