CN208015757U - A kind of equalizing circuit for the bandwidth decaying that the number of being compensated for intersymbol interference introduces - Google Patents
A kind of equalizing circuit for the bandwidth decaying that the number of being compensated for intersymbol interference introduces Download PDFInfo
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- CN208015757U CN208015757U CN201820312488.5U CN201820312488U CN208015757U CN 208015757 U CN208015757 U CN 208015757U CN 201820312488 U CN201820312488 U CN 201820312488U CN 208015757 U CN208015757 U CN 208015757U
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Abstract
The utility model is related to a kind of equalizing circuits for the bandwidth decaying that the number of being compensated for intersymbol interference introduces comprising amplifying circuit, rising edge detection circuit and/or failing edge detection circuit.The utility model to original signal by carrying out rise/fall along detection circuit, obtained pulse signal contains in original signal " individual 0 " symbol and the " phase information of individual 1 " symbol, therefore the rising edge phase or failing edge phase of original signal can be compensated respectively, to realize the compensation to the high frequency attenuation caused by ISI intersymbol interferences.
Description
Technical field
The utility model is related to electronic circuit technology fields, and in particular to a kind of band that the number of being compensated for intersymbol interference introduces
The equalizing circuit of width decaying.
Background technology
The shake (jitter) of high-speed signal transmission is to influence the important indicator of signal transmission quality, how to eliminate signal and trembles
It is the circuit common of high-speed digital signal circuit that dynamic needs, which use equalizer techniques, balanced device, is widely used in optic communication
In high speed integrated circuit design, such as TIA, LA, LDD.Its principle is to utilize compensation technique, improves signal high-frequency gain, opens up
Signal-three dB bandwidth is opened up, shake is reduced.
The data dependence that ISI intersymbol interferences are introduced in signals transmission shakes (DDJ:Data Dependent
Jitter be) one kind in signal jitter, in data-signal code stream " individual 0 " and " high frequency that individual 1 " pattern includes at
Point maximum, in data transmission procedure, the radio-frequency component of this pattern is lost most serious, the distortion of pattern also most serious.At present
There are no the dedicated equalizers technologies dedicated for compensation ISI shakes.
Fig. 1 is existing equalizer compensation circuit, as shown in Figure 1, INP0, INN0 are balanced device input pin, INP1, INN1
For signal input pin of the signal after " be delayed and negate "；OUTP, OUTN are balanced device output pin.Original input signal INP0/
INN0 is overlapped with signal INP1/INN1 of the input signal after " be delayed and negate ", can improve signal element rise/
The relative magnitude of failing edge improves the amplitude of signal radio-frequency component on frequency domain, to achieve the purpose that improve signal bandwidth.
Although prior art can effectively improve the bandwidth of signal, its can not emphasis compensation due to signal
ISI（Intersymbol interference）Caused high-frequency components loss.Meanwhile existing scheme can only be simultaneously to the increasing at the rise and fall of signal edge
Benefit compensates, however signals transmission is different to the attenuation degree of the radio-frequency component of different patterns, and existing scheme can not be right
The rising and falling edges of signal compensate respectively.
Utility model content
The purpose of this utility model is to provide a kind of equilibrium electricity for the bandwidth decaying that the number of being compensated for intersymbol interference introduces
Road can compensate the high frequency attenuation caused by intersymbol interference.
To achieve the above object, the technical solution adopted in the utility model is：
A kind of equalizing circuit for the bandwidth decaying that the number of being compensated for intersymbol interference introduces comprising amplifying circuit, rising edge
Detection circuit and/or failing edge detection circuit, wherein the amplifying circuit include the first amplifying circuit, the second amplifying circuit and
Third amplifying circuit；The input terminal of the input terminal connection equalizing circuit of first amplifying circuit, the balanced electricity of output end connection
The output end on road；The input terminal of the input terminal connection equalizing circuit of the failing edge detection circuit, output end connection second are put
The input terminal of big circuit, and the output end of the output end of the second amplifying circuit connection equalizing circuit；The rising edge detection circuit
Input terminal connection equalizing circuit input terminal, output end connects the output end of third amplifying circuit, and third amplifying circuit
Output end connection equalizing circuit output end.
The failing edge detection circuit include the first delay unit, first negate arithmetic element, second negate arithmetic element,
First prolongs with arithmetic element, the second delay unit, the first path selection switch, the input terminal connection first of failing edge detection circuit
The input terminal of Shi Danyuan, and an input terminal of the output end of the first delay unit connection first and arithmetic element；Meanwhile declining
It is also connected with the first input terminal for negating arithmetic element along the input terminal of detection circuit, first negates the output end connection of arithmetic element
With another input terminal of arithmetic element；And the first input terminal for connecting the second delay unit with the output end of arithmetic element, second
The output end of delay unit connects an input terminal of the first path selection switch, meanwhile, the output end of the second delay unit also passes through
Another input terminal that the first path selection switch is connected after arithmetic element, the output end of the first path selection switch are negated by second
Output end as failing edge detection circuit is connected to the input terminal of the second amplifying circuit.
The rising edge detection circuit include the first delay unit, third negate arithmetic element, the 4th negate arithmetic element,
Second prolongs with arithmetic element, third delay unit, alternate path selecting switch, the input terminal connection first of rising edge detection circuit
The input terminal of Shi Danyuan, and the output end of the first delay unit connection third negates the input terminal of arithmetic element, third negates fortune
An input terminal of the output end connection second and arithmetic element of unit is calculated, meanwhile, the input terminal of rising edge detection circuit is also connected with
Second with another input terminal of arithmetic element；Second connect the input terminal of third delay unit with the output end of arithmetic element, the
One input terminal of the output end connection alternate path selecting switch of three delay units, meanwhile, the output end of third delay unit is also
Another input terminal for negating arithmetic element connection alternate path selecting switch via the 4th, and the output of alternate path selecting switch
End is connected to the input terminal of third amplifying circuit as the output end of rising edge detection circuit.
The amplifying circuit includes metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3, metal-oxide-semiconductor M4, metal-oxide-semiconductor M4, metal-oxide-semiconductor M5, metal-oxide-semiconductor
M6, resistance R1, resistance R2 and variable current source Itai10, variable current source Itai11, variable current source Itai12, wherein
Metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, resistance R1, resistance R2, variable current source Itai10 constitute the first amplifying circuit, metal-oxide-semiconductor M3, metal-oxide-semiconductor
M4, resistance R1, resistance R2, variable current source Itai11 constitute the second amplifying circuit, metal-oxide-semiconductor M5, metal-oxide-semiconductor M6, resistance R1, resistance
R2, variable current source Itai12 constitute third amplifying circuit；
The grid of metal-oxide-semiconductor M1 connects the input terminal inp0 of the first amplifying circuit, and source electrode is grounded through variable current source Itai10,
It drains through resistance R1 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M1 is connected to as an output end of the first amplifying circuit
The output end outn of weighing apparatus circuit；The grid of metal-oxide-semiconductor M2 connects the input terminal inn0 of the first amplifying circuit, and source electrode is through variable current source
Itai10 is grounded, and is drained through resistance R2 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M2 is as the another defeated of the first amplifying circuit
Outlet connects the output end outp of equalizing circuit；
The grid of metal-oxide-semiconductor M3 connects the input terminal inp1 of the second amplifying circuit, and source electrode is grounded via variable current Itai11,
It drains through resistance R1 connection power supplys, meanwhile, the drain electrode of metal-oxide-semiconductor M3 is connected to balanced electricity as an output end of the second amplifying circuit
The output end outn on road；The grid of metal-oxide-semiconductor M4 connects the input terminal inn1 of the second amplifying circuit, and source electrode is through variable current source
Itai11 is grounded, and is drained through resistance R2 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M4 is as the another defeated of the second amplifying circuit
Outlet connects the output end outp of equalizing circuit；
The input terminal inp2 of the grid connection third amplifying circuit of metal-oxide-semiconductor M5, source electrode are grounded via variable current Itai12,
It drains through resistance R1 connection power supplys, meanwhile, the drain electrode of metal-oxide-semiconductor M5 is connected to balanced electricity as an output end of third amplifying circuit
The output end outn on road；The input terminal inn2 of the grid connection third amplifying circuit of metal-oxide-semiconductor M6, source electrode is through variable current source
Itai12 is grounded, and is drained through resistance R2 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M6 is as the another defeated of third amplifying circuit
Outlet connects the output end outp of equalizing circuit.
Metal-oxide-semiconductor in the amplifying circuit could alternatively be triode.
After adopting the above scheme, the utility model detects pulse by failing edge and can be found that in code stream " individual 0 " code
The location information of member, to " individual 0 " symbol detects pulse into horizontal phasing control, by rising edge and can be found that in code stream
" the location information of individual 1 " symbol, to " individual 1 " symbol into horizontal phasing control, to realize to the upper of original signal
It rises and is compensated along phase and the failing edge phase of original signal is compensated.To " individual 1 " symbol in original signal
Or " phase of individual 0 " symbol is adjusted, and expands signal bandwidth, and realization declines to the high frequency caused by ISI intersymbol interferences
The compensation subtracted.
The failing edge detection pulse of the utility model can be found that in code stream that " location information of individual 0 " symbol rises
" the location information of individual 1 " symbol is can be found that in code stream along detection pulse.Due to two kinds of detection pulse paths be it is separated,
Therefore the rising edge of signal and failing edge can be adjusted respectively.
Description of the drawings
Fig. 1 is the circuit diagram of the equalizing circuit of the prior art；
Fig. 2 is the circuit diagram of the equalizing circuit of the utility model first embodiment；
Fig. 3 is the sequence diagram that the utility model carries out input signal rising edge separate compensation；
Fig. 4 is the sequence diagram that the utility model carries out input signal failing edge separate compensation.
Specific implementation mode
The utility model discloses a kind of equalizing circuit for the bandwidth decaying that the number of being compensated for intersymbol interference introduces, and passes through
Rise/fall is carried out along detection circuit to original signal, obtained pulse signal contain in original signal " individual 0 " symbol and
" phase information of individual 1 " symbol, therefore the rising edge phase or failing edge phase of original signal can be compensated respectively, from
And realize the compensation to the high frequency attenuation caused by ISI intersymbol interferences.
Fig. 2 is the circuit diagram of the equalizing circuit for the bandwidth decaying that the number of being compensated for intersymbol interference introduces, as shown in Fig. 2,
Weighing apparatus circuit includes rising edge detection circuit 2, failing edge detection circuit 1 and amplifying circuit, and wherein amplifying circuit includes the first amplification
The input terminal of circuit 31, the second amplifying circuit 32 and third amplifying circuit 33, the first amplifying circuit 31 connects the defeated of equalizing circuit
Enter end, output end connects the output end of equalizing circuit；The input of the input terminal connection equalizing circuit of failing edge detection circuit 1
End, output end connects the input terminal of the second amplifying circuit 32, and the output end of the second amplifying circuit 32 connects equalizing circuit
Output end；The input terminal of the input terminal connection equalizing circuit of rising edge detection circuit 2, output end connect third amplifying circuit 33
Output end, and the output end of third amplifying circuit 33 connection equalizing circuit output end.
Wherein, the first amplifying circuit 31 is used as original signal access, and the signal of output end output is original signal；Second amplification
Circuit 32 is as to " the thermal compensation signal access of individual 0 " symbol, output end output signal are to " the benefit of individual 0 " symbol
Fill signal；Third amplifying circuit 33 is as to " signal of the thermal compensation signal access of individual 1 " symbol, output end output is pair
" the thermal compensation signal of individual 1 " symbol.The output signal of three amplifying circuits is superimposed, that is, realizes in original signal
Rising edge phase or failing edge phase are compensated respectively, to realize to the high frequency attenuation caused by ISI intersymbol interferences
Compensation.
Failing edge detection circuit 1 includes the first delay unit 11, first negates arithmetic element 12, second negates arithmetic element
15, first with arithmetic element 13, the second delay unit 14, the first path selection switch unit 16, failing edge detection circuit 1 it is defeated
Enter the input terminal of the first delay unit 11 of end connection, and the output end of the first delay unit 11 connects first and arithmetic element 13
One input terminal；Meanwhile the input terminal of failing edge detection circuit 1 is also connected with the first input terminal for negating arithmetic element 12, first
Negate another input terminal of the output end connection first and arithmetic element 13 of arithmetic element 12；And first is defeated with arithmetic element 13
Outlet connects the input terminal of the second delay unit 14, and the output end of the second delay unit 14 on the one hand open by the selection of the first access of connection
The input terminal for closing 16, the another defeated of the first path selection switch 16 is connected after on the other hand negating arithmetic element 15 via second
Enter end, the output end of the first path selection switch 16 is connected to the second amplifying circuit as the output end of failing edge detection circuit 1
32 input terminal.Above-mentioned first delay unit 11 carries out signal the delay of a cycle T, and the first path selection switch 16 can
To be realized using single-pole double-throw switch (SPDT).
When input signal InputData passes through failing edge detection circuit 1, input signal InputData's negates signal, with
Input signal InputData is carried out by the time delayed signal of a cycle T and operation, obtains failing edge detection pulse.Failing edge
" the individual rising edge phase of 0 " symbol is consistent, that is, includes " independent in code stream with original signal code stream for the failing edge of detection pulse
0 " symbol leading edge position information.Failing edge detects pulse or failing edge detection pulse negates signal through what is negated
Output signal as failing edge detection circuit 1 is sent to the input terminal of the second amplifying circuit 32.
When the output signal of failing edge detection circuit 1 is when negating signal of failing edge pulse, input the second amplification electricity
In road 32, the output signal after the second amplifying circuit 32 is superimposed with the output signal of the first amplifying circuit 31, that is, is realized pair
" the rising edge phase of individual 0 " symbol is adjusted into line broadening in original signal；Under the output restricting the number of failing edge detection circuit 1 is
It when drop is along pulse, inputs in the second amplifying circuit 32, the output signal after the second amplifying circuit 32 and the first amplifying circuit
31 output signal superposition, that is, realize to " the rising edge phase of individual 0 " symbol carries out compression adjustment in original signal.It is above-mentioned
Each stage signal sequence diagram of adjustment is as shown in Figure 3.
Rising edge detection circuit 2 negates arithmetic element the 21, the 4th and negates arithmetic element including the first delay unit 11, third
24, second with arithmetic element 22, third delay unit 23, alternate path selecting switch 25, the input terminal of rising edge detection circuit 2
The input terminal of the first delay unit 11 is connected, and the output end of the first delay unit 11 connection third negates the defeated of arithmetic element 21
Entering end, third negates an input terminal of the output end connection second and arithmetic element 22 of arithmetic element 21, meanwhile, rising edge detection
The input terminal of circuit 2 is also connected with another input terminal of second and arithmetic element 22；Second connect with the output end of arithmetic element 22
On the one hand the output end of the input terminal of third delay unit 23, third delay unit 23 connects the one of alternate path selecting switch 25
Input terminal, another input terminal on the other hand negating the connection alternate path of arithmetic element 24 selecting switch 25 via the 4th, and the
The output end of two path selection switch 25 is connected to the input of third amplifying circuit 33 as the output end of rising edge detection circuit 2
End.
When input signal InputData is by rising edge detection circuit 2, input signal InputData passes through a cycle T
Delay and the signal that negates is carried out with input signal InputData and operation, obtain rising edge detection pulse.The rising
" the individual failing edge phase of 1 " symbol is consistent, that is, includes " single in code stream with original signal code stream for the failing edge of edge detection pulse
The failing edge location information of 1 " only symbol.Rising edge detects pulse or rising edge detection pulse negates signal as rising edge
The output signal of detection circuit 2 is sent to the input terminal of third amplifying circuit 33.
When the output signal of rising edge detection circuit 2 is that rising edge detects pulse, in input third amplifying circuit 33,
Output signal and the output signal of the first amplifying circuit 31 after third amplifying circuit 33 are overlapped, that is, are realized to original
" the failing edge phase of individual 1 " symbol is adjusted into line broadening in signal；When the output signal of rising edge detection circuit 2 is to rise
Along when negating signal of pulse of detection, input third amplifying circuit 33, the output signal after third amplifying circuit 33
It is overlapped with the output signal of the first amplifying circuit 31, you can realize to " the failing edge phase of individual 1 " symbol in original signal
Position carries out compression adjustment.Each stage signal sequence diagram of above-mentioned adjustment is as shown in Figure 4.
Above-mentioned amplifying circuit includes metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3, metal-oxide-semiconductor M4, metal-oxide-semiconductor M4, metal-oxide-semiconductor M5, metal-oxide-semiconductor
M6, resistance R1, resistance R2 and variable current source Itai10, variable current source Itai11, variable current source Itai12, wherein
Metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, resistance R1, resistance R2, variable current source Itai10 constitute the first amplifying circuit 31, metal-oxide-semiconductor M3, MOS
Pipe M4, resistance R1, resistance R2, variable current source Itai11 constitute the second amplifying circuit 32, metal-oxide-semiconductor M5, metal-oxide-semiconductor M6, resistance R1,
Resistance R2, variable current source Itai12 constitute third amplifying circuit 33.
In first amplifying circuit 31, the grid of metal-oxide-semiconductor M1 connects the input terminal inp0 of the first amplifying circuit 31, and source electrode warp can
Time-dependent current source Itai10 is grounded, and is drained through resistance R1 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M1 is as the first amplifying circuit
31 output end is connected to the output end outn of equalizing circuit.The grid of metal-oxide-semiconductor M2 connects the input of the first amplifying circuit 31
It holds inn0, source electrode to be grounded through variable current source Itai10, drains through resistance R2 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M2
The output end outp of equalizing circuit is connected as another output end of the first amplifying circuit 31.
In second amplifying circuit 32, the grid of metal-oxide-semiconductor M3 connects the input terminal inp1 of the second amplifying circuit 32, source electrode via
Variable current Itai11 ground connection, drains through resistance R1 connection power supplys, meanwhile, the drain electrode of metal-oxide-semiconductor M3 is as the second amplifying circuit 32
An output end be connected to the output end outn of equalizing circuit.The grid of metal-oxide-semiconductor M4 connects the input terminal of the second amplifying circuit 32
Inn1, source electrode are grounded through variable current source Itai11, are drained through resistance R2 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M4 is made
The output end outp of equalizing circuit is connected for another output end of the second amplifying circuit 32.
In third amplifying circuit 33, the input terminal inp2 of the grid of metal-oxide-semiconductor M5 connection third amplifying circuit 33, source electrode via
Variable current Itai12 ground connection, drains through resistance R1 connection power supplys, meanwhile, the drain electrode of metal-oxide-semiconductor M5 is as third amplifying circuit 33
An output end be connected to the output end outn of equalizing circuit.The input terminal of the grid connection third amplifying circuit 33 of metal-oxide-semiconductor M6
Inn2, source electrode are grounded through variable current source Itai12, are drained through resistance R2 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M6 is made
The output end outp of equalizing circuit is connected for another output end of third amplifying circuit 33.
Triode replacement, when being replaced using triode, the hair of triode may be used in metal-oxide-semiconductor in above-mentioned amplifying circuit
Emitter-base bandgap grading is corresponding with the source electrode of metal-oxide-semiconductor, and the base stage of triode is corresponding with the grid of metal-oxide-semiconductor, the leakage of the collector and metal-oxide-semiconductor of triode
It is extremely corresponding.
By adjusting separately three variable current sources of amplifying circuit, the magnification ratio of corresponding amplifying circuit can be adjusted,
The output signal of common adjustment equalizing circuit.
" individual 0 " symbol and " the radio-frequency component maximum that individual 1 " symbol includes, so in number in data-signal code stream
According in transmission process, most serious is lost in the radio-frequency component of this pattern, leads to " individual 0 " symbol and " individual 1 " symbol
It is distorted most serious（This is also the definition of ISI intersymbol interferences）.
The utility model detects pulse by failing edge and can be found that in code stream that " location information of individual 0 " symbol leads to
It crosses rising edge detection pulse and can be found that in code stream " the location information of individual 1 " symbol, then to the " phase of individual 0 " symbol
Position and " phase of individual 1 " symbol is adjusted, to " individual 0 " or " individual 1 " symbol in original signal
Phase is adjusted（Broadening or compression）, the high-frequency loss of the pattern is compensated, signal bandwidth is expanded, is realized dry to ISI intersymbols
Disturb the compensation of caused high frequency attenuation.
The failing edge detection pulse of the utility model can be found that in code stream that " location information of individual 0 " symbol rises
" the location information of individual 1 " symbol is can be found that in code stream along detection pulse.Due to two kinds of detection pulse paths be it is separated,
Therefore the rising edge of signal and failing edge can be adjusted respectively.
Equalizing circuit shown in Fig. 2 is only the utility model preferred embodiment, in practical applications, equalizing circuit also can only by
Rising edge detection circuit 2 and amplifying circuit are constituted, at this point, amplifying circuit only includes above-mentioned first amplifying circuit 31 and above-mentioned third
Amplifying circuit 33.Alternatively, equalizing circuit is only made of failing edge detection circuit 1 and amplifying circuit, at this point, amplifying circuit only includes
Above-mentioned first amplifying circuit 31 and above-mentioned second amplifying circuit 32.Equalizing circuit under both of these case is only to " individual 1 " code
Member is into horizontal phasing control or only to " individual 0 " symbol is realized and the failing edge of original signal is compensated or risen into horizontal phasing control
Along compensation, can equally carry out a degree of compensation to the high frequency attenuation caused by ISI intersymbol interferences, only compensation effect compared with
The compensation effect of embodiment illustrated in fig. 2 is less better.
Claims (5)
1. a kind of equalizing circuit for the bandwidth decaying that the number of being compensated for intersymbol interference introduces, it is characterised in that：The equalizing circuit
Including amplifying circuit, rising edge detection circuit and/or failing edge detection circuit, wherein the amplifying circuit includes the first amplification
Circuit, the second amplifying circuit and third amplifying circuit；The input terminal of the input terminal connection equalizing circuit of first amplifying circuit,
Its output end connects the output end of equalizing circuit；The input terminal of the input terminal connection equalizing circuit of the failing edge detection circuit,
Its output end connects the input terminal of the second amplifying circuit, and the output end of the second amplifying circuit connects the output end of equalizing circuit；
The input terminal of the input terminal connection equalizing circuit of the rising edge detection circuit, output end connect the output of third amplifying circuit
End, and the output end of the output end of third amplifying circuit connection equalizing circuit.
2. the equalizing circuit for the bandwidth decaying that a kind of number of being compensated for intersymbol interference according to claim 1 introduces, special
Sign is：The failing edge detection circuit include the first delay unit, first negate arithmetic element, second negate arithmetic element,
First prolongs with arithmetic element, the second delay unit, the first path selection switch, the input terminal connection first of failing edge detection circuit
The input terminal of Shi Danyuan, and an input terminal of the output end of the first delay unit connection first and arithmetic element；Meanwhile declining
It is also connected with the first input terminal for negating arithmetic element along the input terminal of detection circuit, first negates the output end connection of arithmetic element
With another input terminal of arithmetic element；And the first input terminal for connecting the second delay unit with the output end of arithmetic element, second
The output end of delay unit connects an input terminal of the first path selection switch, meanwhile, the output end of the second delay unit also passes through
Another input terminal that the first path selection switch is connected after arithmetic element, the output end of the first path selection switch are negated by second
Output end as failing edge detection circuit is connected to the input terminal of the second amplifying circuit.
3. the equalizing circuit for the bandwidth decaying that a kind of number of being compensated for intersymbol interference according to claim 1 introduces, special
Sign is：The rising edge detection circuit include the first delay unit, third negate arithmetic element, the 4th negate arithmetic element,
Second prolongs with arithmetic element, third delay unit, alternate path selecting switch, the input terminal connection first of rising edge detection circuit
The input terminal of Shi Danyuan, and the output end of the first delay unit connection third negates the input terminal of arithmetic element, third negates fortune
An input terminal of the output end connection second and arithmetic element of unit is calculated, meanwhile, the input terminal of rising edge detection circuit is also connected with
Second with another input terminal of arithmetic element；Second connect the input terminal of third delay unit with the output end of arithmetic element, the
One input terminal of the output end connection alternate path selecting switch of three delay units, meanwhile, the output end of third delay unit is also
Another input terminal for negating arithmetic element connection alternate path selecting switch via the 4th, and the output of alternate path selecting switch
End is connected to the input terminal of third amplifying circuit as the output end of rising edge detection circuit.
4. the equalizing circuit for the bandwidth decaying that a kind of number of being compensated for intersymbol interference according to claim 1 introduces, special
Sign is：The amplifying circuit includes metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3, metal-oxide-semiconductor M4, metal-oxide-semiconductor M4, metal-oxide-semiconductor M5, metal-oxide-semiconductor
M6, resistance R1, resistance R2 and variable current source Itai10, variable current source Itai11, variable current source Itai12, wherein
Metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, resistance R1, resistance R2, variable current source Itai10 constitute the first amplifying circuit, metal-oxide-semiconductor M3, metal-oxide-semiconductor
M4, resistance R1, resistance R2, variable current source Itai11 constitute the second amplifying circuit, metal-oxide-semiconductor M5, metal-oxide-semiconductor M6, resistance R1, resistance
R2, variable current source Itai12 constitute third amplifying circuit；
The grid of metal-oxide-semiconductor M1 connects the input terminal inp0 of the first amplifying circuit, and source electrode is grounded through variable current source Itai10, drain electrode
Through resistance R1 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M1 is connected to balanced electricity as an output end of the first amplifying circuit
The output end outn on road；The grid of metal-oxide-semiconductor M2 connects the input terminal inn0 of the first amplifying circuit, and source electrode is through variable current source
Itai10 is grounded, and is drained through resistance R2 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M2 is as the another defeated of the first amplifying circuit
Outlet connects the output end outp of equalizing circuit；
The grid of metal-oxide-semiconductor M3 connects the input terminal inp1 of the second amplifying circuit, and source electrode is grounded via variable current Itai11, drain electrode
Through resistance R1 connection power supplys, meanwhile, the drain electrode of metal-oxide-semiconductor M3 is connected to equalizing circuit as an output end of the second amplifying circuit
Output end outn；The grid of metal-oxide-semiconductor M4 connects the input terminal inn1 of the second amplifying circuit, and source electrode connects through variable current source Itai11
Ground drains through resistance R2 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M4 is connected as another output end of the second amplifying circuit
The output end outp of equalizing circuit；
The input terminal inp2 of the grid connection third amplifying circuit of metal-oxide-semiconductor M5, source electrode are grounded via variable current Itai12, drain electrode
Through resistance R1 connection power supplys, meanwhile, the drain electrode of metal-oxide-semiconductor M5 is connected to equalizing circuit as an output end of third amplifying circuit
Output end outn；The input terminal inn2 of the grid connection third amplifying circuit of metal-oxide-semiconductor M6, source electrode connect through variable current source Itai12
Ground drains through resistance R2 connection power supply Vdd, meanwhile, the drain electrode of metal-oxide-semiconductor M6 is connected as another output end of third amplifying circuit
The output end outp of equalizing circuit.
5. the equalizing circuit for the bandwidth decaying that a kind of number of being compensated for intersymbol interference according to claim 4 introduces, special
Sign is：Metal-oxide-semiconductor in the amplifying circuit replaces with triode.
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| CN201820312488.5U CN208015757U (en) | 2018-03-07 | 2018-03-07 | A kind of equalizing circuit for the bandwidth decaying that the number of being compensated for intersymbol interference introduces |
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| CN201820312488.5U CN208015757U (en) | 2018-03-07 | 2018-03-07 | A kind of equalizing circuit for the bandwidth decaying that the number of being compensated for intersymbol interference introduces |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108183875A (en) * | 2018-03-07 | 2018-06-19 | 厦门优迅高速芯片有限公司 | The equalizing circuit of bandwidth attenuation that a kind of number of being compensated for intersymbol interference introduces |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108183875A (en) * | 2018-03-07 | 2018-06-19 | 厦门优迅高速芯片有限公司 | The equalizing circuit of bandwidth attenuation that a kind of number of being compensated for intersymbol interference introduces |
| CN108183875B (en) * | 2018-03-07 | 2019-12-27 | 厦门优迅高速芯片有限公司 | Equalizing circuit capable of compensating bandwidth attenuation caused by signal intersymbol interference |
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