CN207939496U - A kind of pin function limits circuit and chip - Google Patents
A kind of pin function limits circuit and chip Download PDFInfo
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- CN207939496U CN207939496U CN201820307873.0U CN201820307873U CN207939496U CN 207939496 U CN207939496 U CN 207939496U CN 201820307873 U CN201820307873 U CN 201820307873U CN 207939496 U CN207939496 U CN 207939496U
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- antifuse
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Abstract
The utility model provides a kind of pin function and limits circuit and chip.It includes antifuse branch and functional specification branch that the pin function, which limits circuit,；The functional specification branch is separately connected first function module, second function module, the antifuse branch and the I/O pin；The antifuse branch, for providing antifuse current potential for the functional specification branch；The functional specification branch connects first function module or second function module for limiting the I/O pin according to the antifuse current potential.Since the antifuse current potential that antifuse branch provides is permanent current potential, therefore functional specification branch limits I/O pin and connects the first function module, either the second function module of connection is permanent connection, this limited way without reconfiguring pin function after the power is turned on every time, it is easy to use, and the reliability and radioresistance anti-interference of chip can be improved to avoid configuration error caused by radiation etc..
Description
Technical field
The utility model is related to field of computer technology, and circuit and chip are limited more particularly to a kind of pin function.
Background technology
Now, the peripheral interface of CPU (Central Processing Unit, central processing unit) chip is feature-rich more
Coloured silk, but there are problems that pin inadequate resource, for the problem, the mode for mostly using pin multiplexing is drawn to improve cpu chip
The utilization rate of foot.Cpu chip after the power is turned on, by system software to specific register read-write operation configuration IO (input output,
Input and output) pin function so that one of in multiple functions in function connects to I/O pin.This mode can be anti-
Multiple operation, and can be according to the application field flexible configuration of chip.But for certain special users, application field is solid
It is fixed, certain functions are only used without the use of other functions, and multiplexing pins needs reconfigure pin function every time, operate after the power is turned on
It is comparatively laborious.Also, it may lead to configuration error due to radiation etc. in multiplexing pins, reduce the reliable of cpu chip
Property.
Utility model content
In view of the above problems, it is proposed that the utility model embodiment overcoming the above problem or at least portion in order to provide one kind
A kind of pin function to solve the above problems with dividing limits circuit and chip.
To solve the above-mentioned problems, the utility model embodiment discloses a kind of pin function restriction circuit, is applied to core
Piece, the chip include the first function module, the second function module and I/O pin, and it includes anti-molten that the pin function, which limits circuit,
Silk branch and functional specification branch；
The functional specification branch is separately connected first function module, second function module, the antifuse
Branch and the I/O pin；
The antifuse branch, for providing antifuse current potential for the functional specification branch；
The functional specification branch connects first function for limiting the I/O pin according to the antifuse current potential
Module or second function module.
Optionally, the functional specification branch includes enabled device, output device and entering apparatus；
The enabled device is separately connected first function module, second function module, the antifuse branch
With the I/O pin；The enabled device, for according to the antifuse current potential from first function module and described second
One is chosen in the corresponding enable signal of function module, controls the I/O pin input signal or output signal；
The output device is separately connected first function module, second function module, the antifuse branch
With the I/O pin；The output device, for according to the antifuse current potential from the first function module and second function
One is chosen in the corresponding output signal of module, is exported from the I/O pin；
The entering apparatus is separately connected first function module, second function module, the antifuse branch
With the I/O pin；The entering apparatus, the input signal for receiving the I/O pin, and will according to the antifuse current potential
The input signal is input to first function module or the second function module.
Optionally, the enabled device is the first multiplexer, and first multiplexer is alternative multiplexer；
The input terminal of first multiplexer is separately connected first function module, second function module and described
The output end of antifuse branch, first multiplexer connects the I/O pin.
Optionally, the output device is the second multiplexer, and second multiplexer is alternative multiplexer；
The input terminal of second multiplexer is separately connected first function module, second function module and described
The output end of antifuse branch, second multiplexer connects the I/O pin.
Optionally, the entering apparatus includes and door and NAND gate；
Described to be separately connected the antifuse branch and the I/O pin with door input terminal, the output end with door connects
Connect first function module；
The input terminal of the NAND gate is separately connected the antifuse branch and the I/O pin, the output of the NAND gate
End connects second function module.
Optionally, the antifuse branch includes resistance and antifuse device；
The both ends of the resistance are separately connected the first power end and antifuse node；
One end of the antifuse device is separately connected second source end and the antifuse node, the antifuse device
The other end connect ground terminal；The antifuse device is used for the voltage turn-on according to the second source end or shutdown；
The antifuse node connects the functional specification branch；The antifuse node, for according to the antifuse
The voltage of the on or off of device and first power end provides the antifuse electricity for the functional specification branch
Position.
Optionally, the antifuse branch further includes switch；
The both ends of the switch are separately connected the second source end and the antifuse device.
Optionally, the antifuse device is semiconductor element；The antifuse device is low at the second source end
It is turned off when level, the permanent conduction after the second source end is high level.
The utility model additionally provides a kind of chip, and the chip draws including the first function module, the second function module, IO
Foot and such as above-mentioned pin function limit circuit；
The pin function limits circuit and is separately connected first function module, second function module and the IO
Pin connects first function module or second function module for limiting the I/O pin.
The utility model embodiment includes following advantages：
According to the utility model, it includes antifuse branch and functional specification branch that pin function, which limits circuit,；Functional specification
Branch is separately connected the first function module, the second function module, antifuse branch and I/O pin；Antifuse branch is functional specification
Branch provides antifuse current potential；Functional specification branch limits I/O pin according to antifuse current potential and connects the first function module or second
Function module.Since the antifuse current potential that antifuse branch provides is permanent current potential, functional specification branch limits IO
Pin connects the first function module, or the second function module of connection is permanent connection, and this limited way is without each
Pin function is reconfigured after the power is turned on, it is easy to use, and chip can be improved to avoid configuration error caused by radiation etc.
Reliability and radioresistance anti-interference.
Description of the drawings
Fig. 1 is that a kind of pin function of the utility model limits one of the structural schematic diagram of circuit；
Fig. 2 is that a kind of pin function of the utility model limits the second structural representation of circuit；
Fig. 3 is that a kind of pin function of the utility model limits the third structural representation of circuit；
Fig. 4 is that a kind of pin function of the utility model limits the four of the structural schematic diagram of circuit；
Fig. 5 is that a kind of pin function of the utility model limits the five of the structural schematic diagram of circuit；
Fig. 6 is that a kind of pin function of the utility model limits the six of the structural schematic diagram of circuit.
Specific implementation mode
To keep the above objects, features, and advantages of the utility model more obvious and easy to understand, below in conjunction with the accompanying drawings and have
Body embodiment is described in further detail the utility model.
Referring to Fig.1, show that a kind of pin function of the utility model limits the structural schematic diagram of circuit.Applied to core
Piece, the chip include the first function module 20, the second function module 30 and I/O pin 40, and the pin function limits circuit 10
Including antifuse branch 101 and functional specification branch 102；
The functional specification branch 102 is separately connected first function module 20, second function module 30, described
Antifuse branch 101 and the I/O pin 40；
The antifuse branch 101, for providing antifuse current potential for the functional specification branch 102；
The functional specification branch 102 connects described for limiting the I/O pin 40 according to the antifuse current potential
One function module 20 or second function module 30.
In the present embodiment, chip includes the first function module 20 and the second function module 30, and two modules have different
Function, and the same I/O pin of two module reuses 40.Pin function limits in circuit 10, and antifuse branch 101 is using anti-
Fuse technique is that functional specification branch 102 provides antifuse current potential, and antifuse current potential may include high level and low level.Function
Branch 102 is limited according to antifuse current potential, I/O pin 40 is limited and connects the first function module 20 or the second function module 30.Example
Such as, when antifuse current potential is high level, functional specification branch 102 can limit I/O pin 40 and connect the first function module 20；Instead
When fuse current potential is low level, functional specification branch 102 can limit I/O pin 40 and connect the second function module 30.It is melted due to counter
The antifuse current potential that silk branch 101 provides is permanent current potential, therefore functional specification branch 102 limits the connection of I/O pin 40 the
One function module 20, or the second function module 30 of connection is permanent connection, this limited way is not necessarily to every time after the power is turned on
Reconfigure pin function, it is easy to use, and can be to avoid configuration error the problem of, improve reliability.
Optionally, the structural schematic diagram of circuit, the functional specification branch 102 are limited with reference to pin function shown in Fig. 2
Including enabled device 1021, output device 1022 and entering apparatus 1023；
The enabled device 1021 is separately connected first function module 20, second function module 30, described anti-
Fuse branch 101 and the I/O pin 40；The enabled device 1021, for according to the antifuse current potential from first work(
One is chosen in energy module 20 and second function module, 30 corresponding enable signal, controls the input of the I/O pin 40
Signal or output signal；
The output device 1022 is separately connected first function module 20, second function module 30, described anti-
Fuse branch 101 and the I/O pin 40；The output device 1022, for according to the antifuse current potential from the first function mould
One is chosen in 30 corresponding output signal of block 20 and second function module, is exported from the I/O pin 40；
The entering apparatus 1023 is separately connected first function module 20, second function module 30, described anti-
Fuse branch 101 and the I/O pin 40；The entering apparatus 1023, the input signal for receiving the I/O pin 40, and
The input signal is input to first function module, 20 or second function module 30 according to the antifuse current potential.
In the present embodiment, the enable signal and output signal of the first function module 20 and the output of the second function module 30, with
And the input signal received is that timesharing is realized.
First function module 20, the second function module 30, antifuse branch 101 and I/O pin 40 are all connected with enabled device
1021, when the first function module 20 and the second function module 30 export enable signal, enabled device 1021 is according to antifuse branch
The 101 antifuse current potentials provided, choose from 30 corresponding enable signal of the first function module 20 and the second function module
Go out one, is input to I/O pin 40.For example, when antifuse current potential is high level, enabled device 1021 chooses the first function module
20 enable signal inputs I/O pin 40；When antifuse current potential is low level, enabled device 1021 chooses the second function module 30
Enable signal input I/O pin 40.Enable signal can control 40 input signal of I/O pin or output signal.
First function module 20, the second function module 30, antifuse branch 101 and I/O pin 40 are all connected with output device
1022.The structural schematic diagram that circuit is limited with reference to pin function shown in Fig. 3 controls 40 output signal of I/O pin in enable signal
When, the antifuse current potential that output device 1022 is provided according to antifuse branch 101, from the first function module 20 and the second function mould
One is selected in 30 corresponding output signal of block, is input to I/O pin 40.For example, when antifuse current potential is high level,
Output device 1022 chooses the output signal of the first function module 20, is exported from I/O pin 40；When antifuse current potential is low level,
Output device 1022 chooses the output signal of the second function module 30, is exported from I/O pin 40.
First function module 20, the second function module 30, antifuse branch 101 and I/O pin 40 are all connected with entering apparatus
1023.The structural schematic diagram that circuit is limited with reference to pin function shown in Fig. 4 controls 40 input signal of I/O pin in enable signal
When, entering apparatus 1023 receives the input signal of I/O pin 40, and input signal is input to the first work(according to antifuse current potential
It can module 20 or the second function module 30.For example, when antifuse signal is high level, entering apparatus 1023 will connect from I/O pin 40
The input signal of receipts is input to the first function module 20；When antifuse signal is low level, entering apparatus 1023 will be from I/O pin
40 input signals received are input to the second function module 30.
Optionally, pin function referring to Figure 5 limits the structural schematic diagram of circuit, and the enabled device 1021 is the
One multiplexer, first multiplexer are alternative multiplexer；
The input terminal of first multiplexer is separately connected first function module 20,30 and of the second function module
The output end of the antifuse branch 101, first multiplexer connects the I/O pin.
Optionally, pin function referring to Figure 5 limits the structural schematic diagram of circuit, and the output device 1022 is the
Two multiplexers, second multiplexer are alternative multiplexer；
The input terminal of second multiplexer is separately connected first function module 20,30 and of the second function module
The output end of the antifuse branch 101, second multiplexer connects the I/O pin 40.
In the present embodiment, the first multiplexer and the second multiplexer can be alternative multiplexers.Alternative multiplexer according to
Antifuse current potential chooses an output from the signal of inputoutput multiplexer.
Optionally, pin function referring to Figure 5 limits the structural schematic diagram of circuit, and the entering apparatus 1023 includes
With door L1 and NAND gate L2；
It is described to be separately connected the antifuse branch 101 and the I/O pin 40, described and door L1 with door L1 input terminal
Output end connect first function module 20；
The input terminal of the NAND gate L2 is separately connected the antifuse branch 101 and the I/O pin 40, it is described with it is non-
The output end of door L2 connects second function module 30.
In the present embodiment, when enable signal controls 40 input signal of I/O pin, antifuse current potential and input are believed with door L1
It number carries out and operation, NAND gate L2 carries out NAND operation to antifuse current potential and input signal.For example, antifuse current potential is high electricity
Usually, first function mould is input to by the input signal of I/O pin 40 to high level and input signal progress and operation with door L1
Block 20；When antifuse current potential is low level, NAND gate L2 carries out NAND operation to low level and input signal, by I/O pin 40
Input signal is input to the second function module 30.
Optionally, the structural schematic diagram of circuit is limited with reference to pin function shown in fig. 6, the antifuse branch 101 wraps
Include resistance R1 and antifuse device Q1；
The both ends of the resistance R1 are separately connected the first power end V1 and antifuse node J1；
One end of the antifuse device Q1 is separately connected second source end V2 and the antifuse node J1, described anti-molten
The other end connection ground terminal GND of silk device Q1；The antifuse device Q1, for the voltage according to the second source end V2
On or off；
The antifuse node J1 connections functional specification branch 102, the antifuse node J1 are used for according to
The voltage of antifuse device Q1 on or off and the first power end V1 provides institute for the functional specification branch 102
State antifuse current potential.
In the present embodiment, antifuse node J1 linkage functions limit branch 102, are provided for functional specification branch 102 anti-molten
Silk current potential.The other end of one end connection second source the end V2, antifuse device Q1 of antifuse device Q1 connect ground terminal, anti-molten
Voltage turn-ons or shutdown of the silk device Q1 according to second source end V2.Specifically, the antifuse device Q1 is semiconductor element；
The antifuse device Q1 is turned off when the second source end V2 is low level, after the second source end V2 is high level
Permanent conduction.When antifuse device Q1 is turned off, antifuse node J1 is limited by resistance R1 connection the first power end V1 for function
The antifuse current potential for determining the offer of branch 102 is permanently high level；After antifuse device Q1 permanent conductions, antifuse node J1 connects
It is permanently low level that ground, which is the antifuse current potential that functional specification branch 102 provides,.The first power end of the utility model embodiment pair
The resistance value size of the voltage swing and resistance R1 of V1 and second source end V2 does not limit in detail, can be according to actual conditions
It is configured.
Optionally, the structural schematic diagram of circuit is limited with reference to pin function shown in fig. 6, the antifuse branch 101 is also
Including switch K1；
The both ends the switch K1 are separately connected the second source end V2 and the antifuse device Q1.
In the present embodiment, second source end V2 can be high level, by switch K1 control antifuse device Q1 whether with
High level connects, i.e., controls antifuse device Q1 on or off by switch K1.Antifuse device is semiconductor element, can be with
Play the role of to programming port it is encrypted, it is counter to decode very difficult, be suitable for the very high application field of confidentiality requirement.
The utility model embodiment also provides a kind of chip, and the chip includes the first function module 20, the second function mould
Block 30, I/O pin 40 and such as above-mentioned pin function limit circuit 10；
The pin function limits circuit 10 and is separately connected first function module 20,30 and of the second function module
The I/O pin 40 connects first function module 20 or second function module 30 for limiting the I/O pin 40.
In the present embodiment, doing disposably and permanently programming to the pin of same chip using anti-fuse technology, to form interface complete
Different chips.For example, I/O pin 40, which connects the first function module 20, forms chip A, I/O pin 40 connects the second function module
30 formation chip B, chip A and chip B can apply the multiplicity that chip design is greatly reduced in different fields, shorten
The market periods of chip, improve the competitiveness of chip.
In conclusion in the utility model, it includes antifuse branch and functional specification branch that pin function, which limits circuit,；Work(
Branch can be limited and be separately connected the first function module, the second function module, antifuse branch and I/O pin；Antifuse branch is work(
Branch can be limited, antifuse current potential is provided；Functional specification branch limits I/O pin according to antifuse current potential and connects the first function module
Or second function module.Since the antifuse current potential that antifuse branch provides is permanent current potential, functional specification branch
Limit I/O pin connect the first function module, or connection the second function module be permanent connection, this limited way without
It needs to reconfigure pin function after the power is turned on every time, it is easy to use, and situations such as radiating caused configuration error is avoided, it improves
Reliability and radioresistance anti-interference.
Circuit and chip are limited to a kind of pin function provided by the utility model above, are described in detail, this
It applies specific case in text to be expounded the principles of the present invention and embodiment, the explanation of above example is
It is used to help understand the method and its core concept of the utility model；Meanwhile for those of ordinary skill in the art, according to this
The thought of utility model, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification
It should not be construed as a limitation of the present invention.
Claims (9)
1. a kind of pin function limits circuit, be applied to chip, the chip include the first function module, the second function module and
I/O pin, which is characterized in that it includes antifuse branch and functional specification branch that the pin function, which limits circuit,；
The functional specification branch is separately connected first function module, second function module, the antifuse branch
With the I/O pin；
The antifuse branch, for providing antifuse current potential for the functional specification branch；
The functional specification branch connects first function module for limiting the I/O pin according to the antifuse current potential
Or second function module.
2. circuit according to claim 1, which is characterized in that the functional specification branch includes enabled device, follower
Part and entering apparatus；
The enabled device is separately connected first function module, second function module, the antifuse branch and institute
State I/O pin；The enabled device, for according to the antifuse current potential from first function module and second function
One is chosen in the corresponding enable signal of module, controls the I/O pin input signal or output signal；
The output device is separately connected first function module, second function module, the antifuse branch and institute
State I/O pin；The output device, for according to the antifuse current potential from the first function module and second function module
One is chosen in corresponding output signal, is exported from the I/O pin；
The entering apparatus is separately connected first function module, second function module, the antifuse branch and institute
State I/O pin；The entering apparatus, the input signal for receiving the I/O pin, and will be described according to the antifuse current potential
Input signal is input to first function module or the second function module.
3. circuit according to claim 2, which is characterized in that the enabled device is the first multiplexer, and described first is multiple
It is alternative multiplexer with device；
The input terminal of first multiplexer is separately connected first function module, second function module and described anti-molten
The output end of silk branch, first multiplexer connects the I/O pin.
4. circuit according to claim 2, which is characterized in that the output device is the second multiplexer, and described second is multiple
It is alternative multiplexer with device；
The input terminal of second multiplexer is separately connected first function module, second function module and described anti-molten
The output end of silk branch, second multiplexer connects the I/O pin.
5. circuit according to claim 2, which is characterized in that the entering apparatus includes and door and NAND gate；
It is described to be separately connected the antifuse branch and the I/O pin with door input terminal, it is described to connect institute with the output end of door
State the first function module；
The input terminal of the NAND gate is separately connected the antifuse branch and the I/O pin, and the output end of the NAND gate connects
Connect second function module.
6. circuit according to claim 1, which is characterized in that the antifuse branch includes resistance and antifuse device；
The both ends of the resistance are separately connected the first power end and antifuse node；
One end of the antifuse device is separately connected second source end and the antifuse node, the antifuse device it is another
One end connects ground terminal；The antifuse device is used for the voltage turn-on according to the second source end or shutdown；
The antifuse node connects the functional specification branch；The antifuse node, for according to the antifuse device
On or off and first power end voltage, provide the antifuse current potential for the functional specification branch.
7. according to circuit according to claim 6, which is characterized in that the antifuse branch further includes switch；
The both ends of the switch are separately connected the second source end and the antifuse device.
8. circuit according to claim 6, which is characterized in that the antifuse device is semiconductor element；It is described anti-molten
Silk device is turned off when the second source end is low level, the permanent conduction after the second source end is high level.
9. a kind of chip, which is characterized in that the chip includes the first function module, the second function module, I/O pin and such as weighs
Profit requires 1-8 any one of them pin functions to limit circuit；
The pin function restriction circuit is separately connected first function module, second function module and the IO and draws
Foot connects first function module or second function module for limiting the I/O pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820307873.0U CN207939496U (en) | 2018-03-06 | 2018-03-06 | A kind of pin function limits circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820307873.0U CN207939496U (en) | 2018-03-06 | 2018-03-06 | A kind of pin function limits circuit and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207939496U true CN207939496U (en) | 2018-10-02 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820307873.0U Active CN207939496U (en) | 2018-03-06 | 2018-03-06 | A kind of pin function limits circuit and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207939496U (en) |
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2018
- 2018-03-06 CN CN201820307873.0U patent/CN207939496U/en active Active
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Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |
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| CP01 | Change in the name or title of a patent holder |