CN207925467U - array substrate and display device - Google Patents
array substrate and display device Download PDFInfo
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- CN207925467U CN207925467U CN201820436763.4U CN201820436763U CN207925467U CN 207925467 U CN207925467 U CN 207925467U CN 201820436763 U CN201820436763 U CN 201820436763U CN 207925467 U CN207925467 U CN 207925467U
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Abstract
A kind of array substrate of the utility model offer and display device, it includes signal wire, the signal wire includes at least three strip signal wires being arranged in order in their extension direction, and in tactic three strips signal wire, intermediate subsignal line is arranged with the different layer of remaining two strip signal wire, the setting of remaining two strip signal wire same layer；Also, intermediate subsignal line is electrically connected with remaining two strip signal wire respectively by via.Array substrate provided by the utility model, can be to avoid generation electrostatic damage.
Description
Technical field
The utility model is related to display technology fields, and in particular, to a kind of array substrate and display device.
Background technology
Display device has been widely used in disappearing for mobile phone, laptop, PC and personal digital assistant etc.
Take the display screen of electronic product.Display device may be by static damage during manufacturing process or use.
Display device generally includes array substrate and color membrane substrates, and a large amount of letter is formed in the neighboring area of array substrate
Number line and its lead, since signal line leads are very long, in the manufacturing process of array substrate, due to plasma-deposited, etching
It is easy to generate accumulation of static electricity on signal wire and its lead with the technique of friction etc., or generates electrostatic in use, believe
Number line and its lead are easy to that electrostatic damage occurs because of antenna effect, bad to generate.
Utility model content
The utility model aims to solve at least one of the technical problems existing in the prior art, it is proposed that a kind of array substrate
And display device, it can be to avoid generation electrostatic damage.
To realize that the purpose of this utility model provides a kind of array substrate, the signal wire includes in their extension direction
At least three strip signal wires being arranged in order, and in the tactic three subsignal lines, the intermediate subsignal
Line is arranged with remaining the two different layers of subsignal line, remaining the two subsignal line same layer settings；Also, intermediate is described
Subsignal line is electrically connected with remaining the two subsignal lines respectively by via.
Optionally, the signal wire is a plurality of, and is mutually parallel；Also, for two adjacent signal wires, wherein
The subsignal line in at least one subsignal line and another signal line adjacent thereto in one signal line is different
Layer setting.
Optionally, two signal wires of arbitrary neighborhood are respectively the first signal wire and second signal line, wherein described
First signal wire includes three subsignal lines, is used separately as the first main body, first connecting portion and the first leading part；Described
Binary signal line includes four subsignal lines, is used separately as the second main body, second connecting portion, third interconnecting piece and the second lead
Portion；Wherein,
Second main body is arranged with the first main body same layer；
The second connecting portion is arranged with the different layer of first main body；
The third interconnecting piece is arranged with the different layer of the first connecting portion；
Second leading part is arranged with the different layer of first leading part.
Optionally, first main body is consistent with the wire laying mode of the second main body；The first connecting portion with it is described
The wire laying mode of second connecting portion is consistent.
Optionally, the array substrate further includes and the orthogonal third signal wire of the signal wire, the third letter
Number line and the first connecting portion are overlapped；Also, the third signal wire is arranged with the first main body same layer.
Optionally, the array substrate further includes underlay substrate and insulating layer, wherein
The first connecting portion, second connecting portion and the second leading part are arranged on the underlay substrate；
The insulating layer is arranged on the underlay substrate, and covers the first connecting portion, second connecting portion and second
Leading part；
The third signal wire, first main body, the second main body, first leading part and the setting of third interconnecting piece exist
On the insulating layer.
Optionally, two signal wires of arbitrary neighborhood are respectively the first signal wire and second signal line, wherein described
First signal wire includes three subsignal lines, is used separately as the first main body, first connecting portion and the first leading part；Described
Binary signal line includes three subsignal lines, is used separately as the second main body, second connecting portion and the second leading part；Wherein,
Second main body is arranged with the different layer of first main body；
The second connecting portion is arranged with the different layer of the first connecting portion；
Second leading part is arranged with the different layer of first leading part.
Optionally, the array substrate further includes and the orthogonal third signal wire of the signal wire, the third letter
Number line and the first connecting portion are overlapped；Also, the third signal wire is arranged with the different layer of first main body；Described
Three signal wires are arranged with the different layer of second main body.
Optionally, the array substrate further includes underlay substrate, electrostatic protection device, the first insulating layer and the second insulation
Layer, wherein
The first connecting portion, the second main body and the second leading part are arranged on the underlay substrate；
First insulating layer is arranged on the underlay substrate, and covers the first connecting portion, the second main body and the
Two leading parts；
First main body, first leading part and second connecting portion are arranged on first insulating layer；
The second insulating layer is arranged on first insulating layer, and covers first main body, first lead
Portion and second connecting portion；The third signal wire is arranged in the second insulating layer.
As another technical solution, the utility model also provides a kind of display device comprising the utility model provides
Above-mentioned array substrate.
The utility model has the advantages that：
Array substrate provided by the utility model comprising signal wire, the signal wire include in their extension direction successively
At least three strip signal wires of arrangement, and in tactic three strips signal wire, intermediate subsignal line with remaining two
The different layer setting of subsignal line, the setting of remaining two strip signal wire same layer；Also, intermediate subsignal line by via respectively with its
Two strip signal wires of remaininging are electrically connected.By making the different layer of intermediate subsignal line and remaining two strip signal wire be arranged, and remaining two
Strip signal wire same layer be arranged, can make it is separated in whole signal wire, so as to avoid occur electrostatic damage.
Display device provided by the utility model can be with by using above-mentioned array substrate provided by the utility model
It avoids that electrostatic damage occurs.
Description of the drawings
Fig. 1 is the vertical view of the signal wire for the array substrate that the utility model first embodiment provides；
Fig. 2 is the sectional view for the array substrate that the utility model first embodiment provides；
Fig. 3 is the vertical view of the signal wire for the array substrate that the utility model second embodiment provides；
Fig. 4 is the sectional view along line A-A in Fig. 3；
Fig. 5 is the sectional view along line B-B in Fig. 3；
Fig. 6 is the vertical view of the signal wire for the array substrate that the utility model 3rd embodiment provides；
Fig. 7 is the sectional view along line C-C in Fig. 6；
Fig. 8 is the sectional view along line D-D in Fig. 6.
Specific implementation mode
To make those skilled in the art more fully understand the technical solution of the utility model, come below in conjunction with the accompanying drawings to this
The array substrate and display device that utility model provides are described in detail.
It, should also referring to the array substrate that Fig. 1 to Fig. 2, the utility model first embodiment are provided, including signal wire 1
Signal wire 1 includes three strip signal wires (1a, 1b, 1c) being arranged in order in their extension direction, and at tactic three
In subsignal line (1a, 1b, 1c), intermediate subsignal line 1b is arranged with the different layer of remaining two strip signal wire (1a, 1c), remaining two
Strip signal wire (1a, 1c) same layer is arranged；Also, intermediate subsignal line 1b by via (2a, 2b) respectively with remaining two
Subsignal line (1a, 1c) is electrically connected.In the present embodiment, via 2a is two, and via 2b is two, certainly in practical application
In, via 2a may be one either three or more via 2b may be one or three or more.
By making intermediate subsignal line 1b be arranged with the different layer of remaining two strip signal wire (1a, 1c), and remaining two strip
Signal wire (1a, 1c) same layer be arranged, can make it is separated in whole signal wire 1, so as to avoid occur electrostatic damage.
Certainly, in practical applications, subsignal line can also be four, five or six or more.Also, random order
In three strip signal wires of arrangement, intermediate subsignal line is arranged with the different layer of remaining two strip signal wire.
In the present embodiment, as shown in Fig. 2, array substrate further includes underlay substrate 3, buffer insulation layer 4 and insulating layer 5,
Wherein, buffer insulation layer 4 is arranged on underlay substrate 3.Three strip signal wires (1a, 1b, 1c) be used separately as main body, interconnecting piece and
Leading part, wherein intermediate subsignal line 1b is arranged on buffer insulation layer 4；Insulating layer 5 is arranged on buffer insulation layer 4, and
Cover intermediate subsignal line 1b.
Array substrate further includes and 1 orthogonal third signal wire 7 of signal wire the third signal wire 7 and intermediate son
The different layer settings of signal wire 1b, and be arranged with remaining two strip signal wire (1a, 1c) same layer.Specifically, remaining two strip signal wire
(1a, 1c) and third signal wire 7 are arranged on insulating layer 5.Also, remaining two strip signal wire (1a, 1c) passes through two
Via (2a, 2b) is electrically connected with intermediate subsignal line 1b.Third signal wire 7 overlaps with intermediate subsignal line 1b.Third
Signal wire 7 can be the discharge lines etc. of grid line, public electrode wire or electrostatic protection device.
The array substrate provided also referring to Fig. 3 to Fig. 5, the utility model second embodiment comprising a plurality of signal
Line, and a plurality of signal wire is mutually parallel.Also, for two adjacent signal lines, wherein at least one in a signal line
The different layer setting of subsignal line in subsignal line and another signal line adjacent thereto.It is so-called " adjacent ", refer to assuming wherein
At least one subsignal line in one signal line with the subsignal line in another signal line in same layer, with signal wire
The perpendicular direction of extending direction on, this two strips signal wire is least partially overlapped, or can be described as at least partly side by side
Setting.
By making in at least one subsignal line and another signal line adjacent in contrast in a wherein signal line
The different layer setting of subsignal line, it is possible to reduce the relative area of adjacent two signal line is believed so as to reduce at adjacent two
The parasitic capacitance generated between number line.
Specifically, in the present embodiment, two signal lines of arbitrary neighborhood are respectively the first signal wire 8 and second signal line
9, wherein the first signal wire 8 includes three strip signal wires, is used separately as the first main body 8a, first connecting portion 8b and the first lead
Portion 8c；Second signal line includes four strip signal wires, is used separately as the second main body 9a, second connecting portion 9b, third interconnecting piece 9c
With the second leading part 9d.First signal wire 8 and second signal line 9 can be data line.
Wherein, as shown in Figure 4 and Figure 5, the second main body 9a and the first main body 8a same layers are arranged.Second connecting portion 9b and first
The different layer settings of main body 8a.The different layers of third interconnecting piece 9c and first connecting portion 8b are arranged.Second leading part 8c and the first leading part 8c
Different layer setting.
Optionally, the first main body 8a is consistent with the wire laying mode of the second main body 9a；First connecting portion 8b and second connecting portion
The wire laying mode of 9b is consistent.So-called wire laying mode is consistent, refer to the positions and dimensions of the first main body 8a and the second main body 9a substantially
It is identical, in this way, wiring consistency and via arrangement consistency are more advantageous to, so as to balance via contact resistance and via
Etching technics uniformity.
In the present embodiment, array substrate further includes and the orthogonal third signal wire 12 of signal wire, the third signal
Line 12 and first connecting portion 8b are overlapped.Also, third signal wire 12 and the first main body 8a same layers are arranged.Third signal wire 12
Can be the discharge lines etc. of grid line, public electrode wire or electrostatic protection device.
Further, in the present embodiment, array substrate further includes underlay substrate 13, buffer insulation layer 14 and insulating layer
15, wherein buffer insulation layer 14 is arranged on underlay substrate 13.First connecting portion 8b, second connecting portion 9b and the second leading part
9d is arranged on buffer insulation layer 14；Insulating layer 15 is arranged on buffer insulation layer 14, and covers first connecting portion 8b, the second company
Socket part 9b and the second leading part 9d.Third signal wire 12, the first main body 8a, the second main body 9a, the first leading part 8c and third connect
Socket part 9c is arranged on insulating layer 15.
First main body 8a and the first leading part 8c is electrically connected by two vias (10a, 10b) with first connecting portion 8b respectively
It connects.Second main body 9a is electrically connected by via 11a with second connecting portion 9b.Third interconnecting piece 9c is connected by via 11b and second
Socket part 9b electrical connections, and third interconnecting piece 9c is electrically connected by via 11c with the second leading part 9d.
It is real with above-mentioned second also referring to the array substrate that Fig. 6 to Fig. 8, the utility model 3rd embodiment are provided
It applies example to compare, includes equally a plurality of signal wire, and a plurality of signal wire is mutually parallel.Also, two signal lines of arbitrary neighborhood point
It Wei the first signal wire 17 and second signal line 18, wherein the first signal wire 17 includes three strip signal wires, is used separately as first
Main body 17a, first connecting portion 17b and the first leading part 17c；Second signal line 18 includes three strip signal wires, is used separately as the
Two main body 18a, second connecting portion 18b and the second leading part 18c.First signal wire 17 and second signal line 18 can be data
Line.
Wherein, the different layer settings of the second main body 18a and the first main body 17a；Second connecting portion 18b and first connecting portion 17b are different
Layer setting；The different layer settings of second leading part 18c and the first leading part 17c.In this way, adjacent two letters can be reduced farthest
The relative area of number line, so as to more effectively reduce the parasitic capacitance generated between adjacent two signal line.
Optionally, the second main body 18a is consistent with the wire laying mode of the first main body 17a.First connecting portion 17b is connect with second
The wire laying mode of portion 18b is consistent.In this way, wiring consistency and via arrangement consistency are more advantageous to, so as to balance via
Contact resistance and via etch process uniformity.
In the present embodiment, array substrate further includes and the orthogonal third signal wire 12 of signal wire, the third signal
Line 12 and first connecting portion 17b are overlapped；Also, third signal wire 12 and the different layers of the first main body 17a are arranged；Third signal wire
12 and second the different layers of main body 18a be arranged.Third signal wire 12 can be putting for grid line, public electrode wire or electrostatic protection device
Electric wire etc..
In the present embodiment, the first signal wire 17 and second signal line 18 are data line, and the second main body 18a and first
The different layer settings of main body 17a.Third signal wire is grid line.In this case, since the data line in viewing area cannot be with grid line
Same layer, therefore, it is necessary to three-layer metal layer is arranged, that is, data line occupies two metal layers, and grid line occupies one layer of metal layer.
Specifically, array substrate further includes underlay substrate 13, buffer insulation layer 14, the first insulating layer 15 and second insulating layer
16, wherein buffer insulation layer 14 is arranged on underlay substrate 13.First connecting portion 17b, the second main body 18a and the second leading part
18c is arranged on buffer insulation layer 14；First insulating layer 15 is arranged on buffer insulation layer 14, and covering first connecting portion 17b,
Second main body 18a and the second leading part 18c.First main body 17a, the first leading part 17c and second connecting portion 18b are arranged first
On insulating layer 15.Second insulating layer 16 be arranged on the first insulating layer 15, and cover the first main body 17a, the first leading part 17c and
Second connecting portion 18b.Third signal wire 12 is arranged in second insulating layer 16.
First main body 17a and the first leading part 17c passes through two vias (19a, 19b) and first connecting portion 17b electricity respectively
Connection.Second connecting portion 18b is electrically connected with the second main body 18a and the second leading part 18c respectively by two vias (20a, 20b)
It connects.
In conclusion the array substrate that the above-mentioned each embodiment of the utility model provides, by making intermediate subsignal line
It is arranged with the different layer of remaining two strip signal wire, and remaining two strip signal wire same layer is arranged, and can make the centre of whole signal wire
It disconnects, so as to avoid that electrostatic damage occurs.
As another technical solution, the utility model embodiment also provides a kind of display device comprising this practicality is new
The above-mentioned array substrate that type embodiment provides.
The display device that the utility model embodiment provides, the above-mentioned battle array provided by using the utility model embodiment
Row substrate, can be to avoid generation electrostatic damage.
It is understood that embodiment of above is merely to illustrate that the principles of the present invention and uses exemplary
Embodiment, however the utility model is not limited thereto.For those skilled in the art, this is not being departed from
In the case of the spirit and essence of utility model, various changes and modifications can be made therein, these variations and modifications are also considered as this reality
With novel protection domain.
Claims (10)
1. a kind of array substrate, including signal wire, which is characterized in that the signal wire includes being arranged in order in their extension direction
At least three strip signal wires, and in the tactic three subsignal lines, the intermediate subsignal line and remaining
Two different layer settings of subsignal line, remaining the two subsignal line same layer settings；Also, the intermediate subsignal line
It is electrically connected respectively with remaining the two subsignal lines by via.
2. array substrate according to claim 1, which is characterized in that the signal wire is a plurality of, and is mutually parallel；And
And for two adjacent signal wires, wherein at least one subsignal line in a signal line and adjacent thereto
Another signal line in the subsignal line different layer setting.
3. array substrate according to claim 2, which is characterized in that two articles of signal wires of arbitrary neighborhood are respectively
One signal wire and second signal line, wherein first signal wire includes three subsignal lines, is used separately as the first master
Body, first connecting portion and the first leading part；The second signal line includes four subsignal lines, is used separately as the second master
Body, second connecting portion, third interconnecting piece and the second leading part；Wherein,
Second main body is arranged with the first main body same layer；
The second connecting portion is arranged with the different layer of first main body；
The third interconnecting piece is arranged with the different layer of the first connecting portion；
Second leading part is arranged with the different layer of first leading part.
4. array substrate according to claim 3, which is characterized in that the wiring of first main body and second main body
Mode is consistent；The first connecting portion is consistent with the wire laying mode of the second connecting portion.
5. array substrate according to claim 3, which is characterized in that the array substrate further includes and the signal wire phase
Mutually vertical third signal wire, the third signal wire and the first connecting portion are overlapped；Also, the third signal wire
It is arranged with the first main body same layer.
6. array substrate according to claim 5, which is characterized in that the array substrate further includes underlay substrate and insulation
Layer, wherein
The first connecting portion, second connecting portion and the second leading part are arranged on the underlay substrate；
The insulating layer is arranged on the underlay substrate, and covers the first connecting portion, second connecting portion and the second lead
Portion；
The third signal wire, first main body, the second main body, first leading part and third interconnecting piece are arranged described
On insulating layer.
7. array substrate according to claim 2, which is characterized in that two articles of signal wires of arbitrary neighborhood are respectively
One signal wire and second signal line, wherein first signal wire includes three subsignal lines, is used separately as the first master
Body, first connecting portion and the first leading part；The second signal line includes three subsignal lines, is used separately as the second master
Body, second connecting portion and the second leading part；Wherein,
Second main body is arranged with the different layer of first main body；
The second connecting portion is arranged with the different layer of the first connecting portion；
Second leading part is arranged with the different layer of first leading part.
8. array substrate according to claim 7, which is characterized in that the array substrate further includes and the signal wire phase
Mutually vertical third signal wire, the third signal wire and the first connecting portion are overlapped；Also, the third signal wire
It is arranged with the different layer of first main body；The third signal wire is arranged with the different layer of second main body.
9. array substrate according to claim 8, which is characterized in that the array substrate further includes underlay substrate, electrostatic
Protect device, the first insulating layer and second insulating layer, wherein
The first connecting portion, the second main body and the second leading part are arranged on the underlay substrate；
First insulating layer is arranged on the underlay substrate, and the covering first connecting portion, the second main body and second are drawn
Line portion；
First main body, first leading part and second connecting portion are arranged on first insulating layer；
The second insulating layer is arranged on first insulating layer, and cover first main body, first leading part and
Second connecting portion；The third signal wire is arranged in the second insulating layer.
10. a kind of display device, which is characterized in that including array substrate described in any one of claim 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820436763.4U CN207925467U (en) | 2018-03-29 | 2018-03-29 | array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820436763.4U CN207925467U (en) | 2018-03-29 | 2018-03-29 | array substrate and display device |
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| CN207925467U true CN207925467U (en) | 2018-09-28 |
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ID=63596807
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109449168A (en) * | 2018-11-14 | 2019-03-08 | 合肥京东方光电科技有限公司 | Conductor structure and its manufacturing method, array substrate and display device |
| CN109860253A (en) * | 2019-01-31 | 2019-06-07 | 上海天马有机发光显示技术有限公司 | A kind of flexible display panels and flexible display apparatus |
| WO2020103909A1 (en) * | 2018-11-22 | 2020-05-28 | 京东方科技集团股份有限公司 | Array substrate, electrostatic discharge protection circuit and display apparatus |
-
2018
- 2018-03-29 CN CN201820436763.4U patent/CN207925467U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109449168A (en) * | 2018-11-14 | 2019-03-08 | 合肥京东方光电科技有限公司 | Conductor structure and its manufacturing method, array substrate and display device |
| CN109449168B (en) * | 2018-11-14 | 2021-05-18 | 合肥京东方光电科技有限公司 | Lead structure, manufacturing method thereof, array substrate and display device |
| US11088180B2 (en) * | 2018-11-14 | 2021-08-10 | Hefei Boe Optoelectronics Technology Co., Ltd. | Conductive wire structure and manufacturing method thereof, array substrate and display device |
| WO2020103909A1 (en) * | 2018-11-22 | 2020-05-28 | 京东方科技集团股份有限公司 | Array substrate, electrostatic discharge protection circuit and display apparatus |
| US11315920B2 (en) | 2018-11-22 | 2022-04-26 | Boe Technology Group Co., Ltd. | Array substrate, electrostatic discharge protection circuit and display apparatus |
| CN109860253A (en) * | 2019-01-31 | 2019-06-07 | 上海天马有机发光显示技术有限公司 | A kind of flexible display panels and flexible display apparatus |
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