CN207909193U - A kind of image filtering circuit of removal salt-pepper noise - Google Patents

Abstract

The utility model discloses an image filter circuit for removing salt and pepper noise, which comprises a first right-shift 1-bit logic module, a second right-shift 1-bit logic module, a third right-shift 1-bit logic module, and a fourth right-shift 1-bit logic module. block, first 8-bit inverter, second 8-bit inverter, first 8-bit numerical comparator, second 8-bit numerical comparator, third 8-bit numerical comparator, fourth 8-bit numerical comparator block , 8-bit XOR operation, the first 8-bit AND operation, the second 8-bit AND operation, the third 8-bit AND operation block, 8-bit OR operation, the first left-shift 1-bit logic, the second left-shift 1-bit logic, 2-bit left shift logic, 8-bit adder, 8-bit buffer, and 8-bit average operation. The evolutionary filter circuit of the utility model utilizes the optimization characteristic of the intelligent evolutionary algorithm, continuously updates the filter structure by comparing the effect of the sample image before and after filtering, and finally seeks a set of suitable function-level relationship operation sets, so that the evolutionary filter circuit can obtain the best filtering Effect.

Description

An image filter circuit for removing salt and pepper noise

technical field

The utility model relates to an image filter circuit for removing salt and pepper noise, which belongs to the technical field of image processing.

Background technique

Image filtering has always been a hot spot in image preprocessing. Due to the influence of the external environment and its own physical devices, noise is always inevitably generated during the process of image transmission and acquisition. Image denoising processing is the process of performing other subsequent operations on the image. necessary preprocessing steps.

Commonly used image filters are median, mean filter, LEE, FROST and KUAN filters. The median filter is a nonlinear filter, which can better preserve the details and edges of the image and weaken the blurring effect. The FROST filter algorithm assumes that the image is a stationary process, and its impulse response is a bilateral exponential function. FROST can be regarded as a low-pass filter; the KUAN wave algorithm assumes that the noise is additive noise related to the signal, and then uses the minimum variance estimation to obtain a fixed window. The linear combination of medium observed intensity and local average intensity; LEE filtering is an adaptive filtering algorithm using the sample mean and variance in the filtering window; Astola et al. proposed a vector median filtering algorithm based on further research on median filtering; Trahanias et al. Analyzing and comparing the magnitude and phase of the underpixels of the color image, a vector direction filter is proposed that is statistically sorted according to the direction distance of the pixel vector; Karakos et al. combine the above two filters to form a vector magnitude direction Filter; Lukac extends the weighted median filter to the application of color image denoising, integrates the characteristics of the vector direction filter, proposes a vector weighted direction median filter, and proposes a gradient iterative optimization solution method for the weight coefficients .

In recent years, in addition to using traditional optimization methods to improve filtering performance, FPGA provides a general framework for solving complex system optimization problems. In the field of evolutionary design of image filtering, Sekanina et al. proposed the use of Cartesian genetic programming (Cartesian Genetic Programming -CGP) to design the structure of the image denoising filter, and achieved good results; Bao et al. proposed a multi-objective filtering evolutionary circuit, which optimized the circuit resources on the basis of minimizing the error before and after filtering; Vasicek Based on the Sekanina method, an improved evolution scheme of 5╳5 filtering window is proposed, and the filtering experiments of various images under various noises are carried out.

However, the existing technology has the following disadvantages: 1. Most of the current filtering algorithms are still software filtering, which has limitations in real-time application and processing speed, and some algorithms require complex manual conversion for hardware; 2. Traditional linear mean Both the filter and the nonlinear statistical filter use simple averaging or sorting relationship operations, and the filtering still has defects in detail retention; 3. The traditional linear mean filter and nonlinear statistical filter both use simple Taking the average value or sorting the relationship operation, the filtering still has defects in detail preservation.

In view of this, it is obviously necessary to develop a new image filter circuit for removing salt and pepper noise to solve the above defects.

Contents of the invention

The purpose of the invention of the utility model is to provide an image filter circuit for removing salt and pepper noise.

In order to achieve the purpose of the above invention, the technical solution adopted by the utility model is: an image filter circuit for removing salt and pepper noise, including a first right-shift 1-bit logic module, a second right-shift 1-bit logic module, and a third right-shift 1-bit logic module. Logic module, the fourth right shift 1-bit logic module, the first 8-bit inverter module, the second 8-bit inverter module, the first 8-bit numerical comparator module, the second 8-bit numerical comparator module, the third 8-bit numerical comparator module, the fourth 8-bit numerical comparator module, 1 8-bit XOR operation module, the first 8-bit AND operation module, the second 8-bit AND operation module, the third 8-bit AND operation module, 1 An 8-bit OR operation module, a first left-shift 1-bit logic module, a second left-shift 1-bit logic module, a left-shift 2-bit logic module, an 8-bit adder module, an 8-bit buffer module and 1 8-bit mean calculation module,

The output end of the first 8-bit numerical comparator module is connected to an input end of the second 8-bit numerical comparator module, and the output end of the second 8-bit numerical comparator module is connected to the third 8-bit numerical comparator module. An input end of the numerical comparator module is connected, and an output end of the third 8-bit numerical comparator module is connected to an input end of the fourth 8-bit numerical comparator module,

The output end of the first 8-bit inverter module is connected to an input end of the 8-bit XOR operation module, and the output end of the 8-bit XOR operation module is connected to the first left-shift 1-bit logic module The input terminal of the first left-shift 1-bit logic module is connected to an input terminal of the 8-bit or operation module, and the output terminal of the 8-bit or operation module is connected to the third 8-bit value The other input of the comparator module is connected,

The output end of the first right-shift 1-bit logic module and the output end of the second right-shift 1-bit logic module are respectively connected to the input ends of the 8-bit adder module, and the output of the 8-bit adder module The end is connected with the other input end of the 8-bit XOR operation module,

The output end of the third right-shifting 1-bit logic module is connected to the input end of the 8-bit AND operation module, and the output end of the 8-bit AND operation module is connected to the fourth right-shifting 1-bit logic module, so The output end of the fourth right shift 1-bit logic module is connected to the input end of the second 8-bit AND operation, and the output end of the second 8-bit AND operation is connected to the input end of the third 8-bit AND operation ,

The output end of the second 8-bit inverter module is connected to the other input end of the second 8-bit AND operation module,

The output end of the left-shift 2-bit logic module is connected to the input end of the second left-shift 1-bit logic module, and the output end of the second left-shift 1-bit logic module is connected to the third 8-bit AND operation module The other input terminal is connected, the output terminal of the third 8-bit AND operation module is connected to the other input terminal of the fourth 8-bit value comparator module,

The output terminal of the 8-bit buffer module and the output terminal of the fourth 8-bit numerical comparator module are connected to the input terminal of the 8-bit mean value operation module.

Preferably, the output terminal of the fourth 8-bit numerical comparator module and the output terminal of the 8-bit buffer module are respectively connected to the two input terminals of the 8-bit average value operation module, and the output terminals of the 8-bit average value operation module are connected to There is a synchronous circuit consisting of 8 D flip-flops.

In the above, the 8 D flip-flops run synchronously and in parallel through the clock signal Clk, there is no connection between the 8 D flip-flops, and the final circuit output is the Q output combination of the 8 flip-flops.

Due to the application of the above-mentioned technical solutions, the utility model has the following advantages compared with the prior art:

1. While the filtering algorithm is hardware-based, the utility model realizes maximum retention of image details and edges, reduces the number of high error points, and improves the visual effect after filtering;

2. The evolutionary filter circuit of the utility model utilizes the optimization characteristic of the intelligent evolutionary algorithm, and continuously updates the filter structure by comparing the effect of the sample image before and after filtering, and finally seeks a set of suitable function-level relational operation sets, so that the evolutionary filter circuit can obtain the best filter effect;

3. The evolutionary circuit of the utility model has strong hardware implementation flexibility, can be transplanted on various hardware platforms, and provides possibility for real-time application of filtering algorithms.

Description of drawings

Fig. 1 is the structural representation of the utility model.

Among them: 1. The first 1-bit right-shift logic module; 2. The second 1-bit right-shift logic module; 3. The third 1-bit right-shift logic module; 4. The fourth 1-bit right-shift logic module; 5. The first 8-bit inverter module; 6. The second 8-bit inverter module; 7. The first 8-bit numerical comparator module; 8. The second 8-bit numerical comparator module; 9. The third 8-bit numerical comparator module 10. The fourth 8-bit numerical comparator module; 11. The 8-bit XOR operation module; 12. The first 8-bit AND operation module; 13. The second 8-bit AND operation module; 14. The third 8-bit AND operation module ; 15, 8-bit OR operation module; 16, the first left-shift 1-bit logic module; 17, the second left-shift 1-bit logic module; 18, left-shift 2-bit logic module; 19, 8-bit adder module; 20, 8-bit buffer module; 21, 8-bit mean calculation module.

Detailed ways

Below in conjunction with accompanying drawing and embodiment the utility model is further described:

Embodiment 1: Referring to FIG. 1 , an image filter circuit for removing salt and pepper noise, including a first right-shift 1-bit logic module 1, a second right-shift 1-bit logic module 2, and a third right-shift 1-bit logic module 3 , the fourth right shift 1-bit logic module 4, the first 8-bit inverter module 5, the second 8-bit inverter module 6, the first 8-bit numerical comparator module 7, the second 8-bit numerical comparator module 8 , the third 8-bit numerical comparator module 9, the fourth 8-bit numerical comparator module 10, one 8-bit XOR operation module 11, the first 8-bit AND operation module 12, the second 8-bit AND operation module 13, the first 8-bit AND operation module 13, Three 8-bit AND operation modules 14, one 8-bit OR operation module 15, the first left-shift 1-bit logic module 16, the second left-shift 1-bit logic module 17, one left-shift 2-bit logic module 18, one 8 Bit adder module 19, 1 8-bit buffer module 20 and 1 8-bit average computing module 21,

The output end of the first 8-bit numerical comparator module 7 is connected to an input end of the second 8-bit numerical comparator module 8, and the output end of the second 8-bit numerical comparator module 8 is connected to the first 8-bit numerical comparator module. One input end of three 8-bit numerical comparator modules 9 is connected, and the output end of the third 8-bit numerical comparator module 9 is connected with an input end of the fourth 8-bit numerical comparator module 10,

The output end of the first 8-bit inverter module is connected to an input end of the 8-bit XOR operation module 11, and the output end of the 8-bit XOR operation module 11 is connected to the first left-shifted 1-bit The input end of logic module 17 is connected, and the output end of described first left-shift 1 bit logic module 17 is connected with an input end of described 8-bit or operation module 11, and the output end of described 8-bit or operation module 11 is connected with all The other input end of the third 8-bit value comparator module 9 is connected,

The output end of the first right-shift 1-bit logic module 1 and the output end of the second right-shift 1-bit logic module 2 are respectively connected to the input end of the 8-bit adder module 19, and the 8-bit adder The output end of module 19 is connected with the other input end of described 8-bit XOR operation module 15,

The output end of the third right-shifting 1-bit logic module 3 is connected to the input end of the 8-bit AND operation module 12, and the output end of the 8-bit AND operation module 12 is connected to the fourth right-shift 1-bit logic module 4 connection, the output terminal of the fourth right-shift 1-bit logic module 4 is connected with the input terminal of the second 8-bit AND operation 13, and the output terminal of the second 8-bit AND operation module 13 is connected with the third 8 bits are connected with the input end of the arithmetic module 14,

The output terminal of the second 8-bit inverter module 6 is connected to the other input terminal of the second 8-bit AND operation module 13,

The output end of described left-shift 2-bit logic module 18 is connected with the input end of described second left-shift 1-bit logic module 17, and the output end of described second left-shift 1-bit logic module 17 is connected with the third 8-bit logic module 17. It is connected with the other input end of the operation module 14, and the output end of the third 8-bit and operation module 1 is connected with the other input end of the fourth 8-bit value comparator module 10,

The output terminal of the 8-bit buffer module 20 and the output terminal of the fourth 8-bit value comparator module 10 are connected to the input terminal of the 8-bit average value operation module 21 .

In this embodiment, the output terminal of the fourth 8-bit numerical comparator module and the output terminal of the 8-bit buffer module are respectively connected to the two input terminals of the 8-bit mean value calculation module, and the output of the 8-bit mean value calculation module The terminal is connected with a synchronous circuit composed of 8 D flip-flops.

In the above, the 8 D flip-flops run synchronously and in parallel through the clock signal Clk, there is no connection between the 8 D flip-flops, and the final circuit output is the Q output combination of the 8 flip-flops.

Explanation of terms involved in the utility model:

1. Image filtering: the processing method to remove the inevitable noise generated in the process of image transmission and acquisition: a necessary preprocessing step for other subsequent operations on the image.

2. Pixel: 8-bit binary number from 0 to 255, the basic unit of image filter input.

In the utility model, the input of image filtering is based on pixel points, and the pixel points are 8-bit binary numbers of 0 to 255. If the filtering pixel points are I(x, y), the window of image filtering can be 3╳3,5 ╳5, 7╳7 or 9╳9, the larger the window, the better the peak signal-to-noise ratio value after filtering, but the visual effect of the image is easy to blur, and it also increases the calculation cost, so the filtering used in this patent is 3 ╳3 window, each calculation takes 9 pixels in the image pixel point I(x, y) field {I(x-1, y), I(x, y), I(x+1, y), I(x-1, y-1), I(x, y-1), I(x+1, y-1), I(x-1, y+1), I(x,y+1) , I(x+1, y+1)} is used as input, and the output of the filter circuit is one pixel after filtering. The 9 inputs use T1~T9, representing the 9 pixels of the circuit input.

In this embodiment, the 3╳3 table has a total of 9 pixel points, corresponding to 9 pixel input terminals, and the first row from top to bottom and from left to right are the first pixel input terminal, the second pixel input terminal, and the third pixel input terminal. terminal, the second row from left to right is the fourth pixel input terminal, the fifth pixel input terminal, the sixth pixel input terminal, the third row from left to right is the ninth pixel input terminal, the eighth pixel input terminal, The seventh pixel input terminal, the first pixel input terminal is connected to the third 8-bit right-shift 1-bit module 3; the second pixel input terminal is connected to the first input terminal of the first 8-bit value comparator module 7 and the first 8-bit right-shift module 3 Shift 1 bit module 1; The third pixel input terminal is connected to the second 8-bit inverter module 6 and the second 8-bit value comparator module 8; The fourth pixel input terminal is connected to the second 8-bit right shift 1-bit module 2; The five-pixel input terminal is connected to the 8-bit XOR operation module 11; the sixth pixel input terminal is connected to the 8-bit left shift 2-bit module 18; the seventh pixel input terminal is connected to the second input terminal of the first 8-bit value comparator module 7; The eight-pixel input terminal is connected to the first 8-bit inverter module 5; the ninth pixel input terminal is connected to the 8-bit buffer module 20.

The filter circuit of the utility model is composed of modules, the basic operation of each logic module in the circuit is a logic function of 2 inputs (pixel points), and the set {and (ADD), or (OR), not (NOT)} is As far as the "base" circuit is concerned, it is a logic operation with 16-bit binary input, and the minimum window of the filter operation is 3╳3 (9 pixels). The filter circuit is a large-scale circuit with 72-bit input, which can evolve to A set of 8-bit binary logical operations (for example: {shift (Shift), addition (ADD), bit AND (bit AND), bit OR (bit OR), bit exclusive OR (bit XOR)}) as the "base" circuit , can effectively evolve the filtering operation circuit.

In the utility model, the circuit structure includes: 4 "right shift 1 bit" logic modules, 2 "8-bit inverters", 4 "8-bit numerical comparators", 1 "8-bit XOR operation" module , 3 "8-bit 'and' operation modules, 1 "8-bit 'or' operation" module, 2 "left shift 1 bit" logic modules, 1 "right shift 2 bit" logic modules, "8 1 "bit adder", 1 "8-bit buffer", 1 "8-bit average value operation module" and 8 D flip-flops. A synchronous circuit composed of 8 D flip-flops is added at the output end, that is, a mechanism for eliminating competition and risk is added to achieve the purpose of eliminating competition and risk at the output end.

Circuit FPGA implementation of salt and pepper noise filtering. Each module of the filter circuit has a 16-bit input, and there are 19 such modules in total. Therefore, the programmable logic system of FPGA is used to design the module, and the user can not only conveniently design the logic of each module of the filter circuit Function, realize the repeated programming of the system, thus greatly reducing the difficulty of development, shortening the development cycle, and improving the operating speed of the system.

Table 1 The hardware implementation of the filter circuit in EPM9320LC84-15 In LCs Utilized P-terms Realization of filter circuit for removing salt and pepper noise 31 45/320 14% 150

The table above shows that the salt and pepper noise removal circuit is implemented on the FPGA hardware platform, and there is no need to convert complex algorithms to hardware. The filter circuit logic to be obtained in this application is implemented on the EPM9320LC84-15 platform of Ateral's device. In Table 1, In represents the number of input pins, LCs represents the number of logical cells, P-terms represents the number of product terms, and Utilized represents resource utilization. It is observed from the results that the hardware resource consumption of the evolutionary filter circuit obtained under the salt and pepper noise is relatively low.

Below is the application of the present utility model:

Experimental noise: salt and pepper noise with variance D of 0.12, 0.16, and 0.2. The noise is loaded into 13 standard pictures (256╳256) for learning, and the obtained circuit is tested on the pictures of lenna and baboon.

The filter circuit of the utility model and various spatial filtering methods (average value, median value, loss median value and loss direction median value), wavelet denoising method in the frequency domain, and an evolutionary filter circuit (EvolutionaryImage) with the optimization goal of minimizing MAE Filter-EIF) [13] for comparison. All the data in this application are obtained by running the program developed by our research group. In the experimental results, MF means median filter; VMF means vector median filter; BVDF means vector median filter; AF means mean filter; Wavelet means Wavelet threshold filtering.

The implementation case is divided into 2 parts:

1) Comparison of filter circuit, MF and BVDF details and edge preservation of the utility model;

2) Comparison between the filter circuit of the present utility model and EIF.

1) Comparison of detail and edge preservation

Comparing the filter circuit of the utility model with MF and BVDF filters for edge preservation and noise points, because the effects of MF and VMF are close, MF is selected as the comparison object. It can be observed that the filter circuit of the present invention retains better edges under salt and pepper and pulse noise. Although the MF definition is high and the number of noise points is significantly reduced, the filter circuit of the present invention has a stronger ability to retain edges. At the lenna hair and baboon hair with more edges, the edges of MF are smooth, while the edges of MEIF can still be well preserved, and the edges of BVDF are better than MF, slightly worse than the filtering circuit of the present invention. BVDF has obvious noise points under salt and pepper and impulse noise, especially dense noise points appear in the baboon image.

2) Comparison between the utility model circuit and EIF

According to previous achievements in this field, EIF has good denoising ability, and the overall filtering effect of EIF is similar to that of the filter circuit of the present invention, and the difference between the filter circuit of the present invention and PSNR and MSE is also small, but the local filtering effect of the filter is relatively small. The noise points in the area are more obvious. EIF and the filter circuit of the present utility model are to the filter effect of salt and pepper noise (lenna figure), and the large error noise point of EIF will be more than the filter circuit of the present utility model, and in the lower region of the grayscale value of image, the noise point of EIF is just more obvious.

Claims (2)

1. An image filter circuit for removing salt-and-pepper noise, characterized in that: it comprises a first right-shift 1-bit logic module, a second right-shift 1-bit logic module, a third right-shift 1-bit logic module, and a fourth right-shift 1-bit logic module Logic module, first 8-bit inverter module, second 8-bit inverter module, first 8-bit numerical comparator module, second 8-bit numerical comparator module, third 8-bit numerical comparator module, fourth 8-bit numerical comparator module, one 8-bit XOR operation module, the first 8-bit AND operation module, the second 8-bit AND operation module, the third 8-bit AND operation module, one 8-bit OR operation module, the first Left-shift 1-bit logic module, second left-shift 1-bit logic module, 1 left-shift 2-bit logic module, 1 8-bit adder module, 1 8-bit buffer module, and 1 8-bit average calculation module, The output end of the first 8-bit numerical comparator module is connected to an input end of the second 8-bit numerical comparator module, and the output end of the second 8-bit numerical comparator module is connected to the third 8-bit numerical comparator module. An input end of the numerical comparator module is connected, and an output end of the third 8-bit numerical comparator module is connected to an input end of the fourth 8-bit numerical comparator module, The output end of the first 8-bit inverter module is connected to an input end of the 8-bit XOR operation module, and the output end of the 8-bit XOR operation module is connected to the first left-shift 1-bit logic module The input terminal of the first left-shift 1-bit logic module is connected to an input terminal of the 8-bit or operation module, and the output terminal of the 8-bit or operation module is connected to the third 8-bit value The other input of the comparator module is connected, The output end of the first right-shift 1-bit logic module and the output end of the second right-shift 1-bit logic module are respectively connected to the input ends of the 8-bit adder module, and the output of the 8-bit adder module The end is connected with the other input end of the 8-bit XOR operation module, The output end of the third right-shifting 1-bit logic module is connected to the input end of the 8-bit AND operation module, and the output end of the 8-bit AND operation module is connected to the fourth right-shifting 1-bit logic module, so The output end of the fourth right shift 1-bit logic module is connected to the input end of the second 8-bit AND operation, and the output end of the second 8-bit AND operation is connected to the input end of the third 8-bit AND operation , The output end of the second 8-bit inverter module is connected to the other input end of the second 8-bit AND operation module, The output end of the left-shift 2-bit logic module is connected to the input end of the second left-shift 1-bit logic module, and the output end of the second left-shift 1-bit logic module is connected to the third 8-bit AND operation module The other input terminal is connected, the output terminal of the third 8-bit AND operation module is connected to the other input terminal of the fourth 8-bit value comparator module, The output terminal of the 8-bit buffer module and the output terminal of the fourth 8-bit numerical comparator module are connected to the input terminal of the 8-bit mean value operation module. 2. the image filter circuit of removing salt and pepper noise according to claim 1, is characterized in that: the output end of the 4th 8-bit value comparator module and the output end of described 8-bit buffer module are connected to 8 mean value calculations respectively The two input ends of the module, and the output end of the 8-bit average value operation module are connected with a synchronous circuit composed of 8 D flip-flops.