CN207909193U - A kind of image filtering circuit of removal salt-pepper noise - Google Patents
A kind of image filtering circuit of removal salt-pepper noise Download PDFInfo
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- CN207909193U CN207909193U CN201721204701.2U CN201721204701U CN207909193U CN 207909193 U CN207909193 U CN 207909193U CN 201721204701 U CN201721204701 U CN 201721204701U CN 207909193 U CN207909193 U CN 207909193U
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Abstract
The utility model discloses a kind of image filtering circuits of removal salt-pepper noise, 1 logic module is moved to right including first, second moves to right 1 logic module, third moves to right 1 logic module, 4th moves to right 1 logical block, one 8 bit Inverting device, 2nd 8 bit Inverting device, one 8 bit value comparator, 2nd 8 bit value comparator, 3rd 8 bit value comparator, 4th 8 bit value comparator module, 8 XOR operation, one 8 and operation, 2nd 8 and operation, 3rd 8 and operation blocks, 8 or operation, first moves to left 1 logic, second moves to left 1 logic, move to left 2 logics, 8 adders, 8 digit buffers and 8 mean operations.The utility model evolution filter circuit utilizes the optimizing characteristic of Intelligent evolution algorithm, front and back effect, which is filtered, by comparing sample image constantly updates filter construction, finally seek one group of suitable function grade relational operation set, evolution filter circuit is enable to obtain best filter effect.
Description
Technical field
The utility model is related to a kind of image filtering circuits of removal salt-pepper noise, belong to technical field of image processing.
Background technology
Image filtering is always the hot spot in image preprocessing, due to the influence of external environment and own physical device, figure
As during transmission and acquisition, being always inevitably generated noise, scene image partition processing is carried out, is that image carries out other
The necessary pre-treatment step of subsequent arithmetic.
Common image filter has intermediate value, mean filter, LEE, FROST and KUAN filter.Median filter is
A kind of nonlinear filter can preferably retain the details and edge of image, weaken fogging action.FROST filtering algorithms
It is assumed that image is stationary process, impulse response is a bilateral exponential function, and FROST can regard low-pass filter as；KUAN
Wave algorithm assume noise be with the relevant additive noise of signal, then use minimum variance estimate obtain observed in stationary window it is strong
The linear combination of degree and local mean intensity；LEE filtering is the adaptive-filtering using sample average and variance in filter window
Algorithm；Astola etc. is on the further Research foundation of medium filtering, the Vector median filtering algorithm of proposition；Trahanias etc.
The analysis of deficient amount pixel into line amplitude, the phase of color image is compared, proposes a kind of direction distance progress according to pixel vector
The vector-equation analytical method of sort method；Both the above filter is then combined by Karakos etc., and then forms amplitude of the vector side
To filter；Weighted median filter is expanded to coloured image and removed in application of making an uproar by Lukac, gathers the spy of vector-equation analytical method
Property, it proposes vector weighting directional medial filtering device, the method that Gradient Iteration optimizing solves is proposed to weight coefficient therein.
In recent years, in addition to using traditional optimization method to be filtered the improvement of performance, FPGA provides a kind of solve again
The general framework of miscellaneous system optimization problem, in the Evolutionary Design field of image filtering, the propositions such as Sekanina are lost using cartesian
The structure design that programming (Cartesian Genetic Programming-CGP) carries out scene image partition filter is passed, is taken
Obtain preferable effect；Bao etc. proposes a kind of multiple target filtering evolution circuit, right on the basis of error before and after minimizing filtering
Circuit resource is optimized；Vasicek proposed on the basis of Sekanina methods 5 ╳, 5 filter windows it is improved into
Change scheme, and carried out the filtering experiments of a variety of images under a variety of noises.
However the prior art has the following disadvantages：1, current filtering algorithm majority is still software filtering, real-time field
The application of conjunction and processing speed have limitation, some hardware algorithmizations need to carry out complicated artificial conversion；2, traditional line
Property mean filter and Nonlinear Statistical filter all use it is simple be averaged or ordering relation operation, filter thin
Section retains still defective；3, traditional linear mean filter and Nonlinear Statistical filter, which all use, is simply averaged
Value or ordering relation operation, filtering are still defective in details reservation.
In view of this, a kind of image filtering circuit of new removal salt-pepper noise of exploitation, solves drawbacks described above, it is clear that be to have
It is necessary.
Invention content
The goal of the invention of the utility model is to provide a kind of image filtering circuit of removal salt-pepper noise.
To achieve the above object of the invention, the technical solution adopted in the utility model is：A kind of image of removal salt-pepper noise
Filter circuit, including first move to right 1 logic module, second move to right 1 logic module, third moves to right 1 logic module, the 4th
Move to right 1 logic module, the one 8 bit Inverting device module, the 2nd 8 bit Inverting device module, the one 8 bit value comparator module,
28 bit value comparator modules, the 3rd 8 bit value comparator module, the 4th 8 bit value comparator module, 18 exclusive or fortune
Calculate module, the one 8 and computing module, the 2nd 8 and computing module, the 3rd 8 and computing module, 18 or operation mould
Block, first move to left 1 logic module, second move to left 1 logic module, 1 move to left 2 logic modules, 18 adder mould
Block, 18 digit buffer module and 18 mean operation module,
The output end of the one 8 bit value comparator module and one of the 2nd 8 bit value comparator module it is defeated
Enter end connection, the output end of the 2nd 8 bit value comparator module and one of the 3rd 8 bit value comparator module it is defeated
Enter end connection, the output end of the 3rd 8 bit value comparator module and one of the 4th 8 bit value comparator module it is defeated
Enter end connection,
The output end of the one 8 bit Inverting device module is connect with an input terminal of 8 XOR operation modules, institute
The input terminal that the output end for stating 8 XOR operation modules moves to left 1 logic module with described first is connect, and described first moves to left 1
The output end of position logic module is connect with an input terminal of described 8 or computing module, the output of described 8 or computing module
End is connect with another input terminal of the 3rd 8 bit value comparator module,
Described first, which moves to right the output end of 1 logic module and described second, moves to right the output end difference of 1 logic module
It is connect with the input terminal of 8 adder Modules, the output end of 8 adder Modules and 8 XOR operation moulds
Another input terminal of block connects,
The output end that the third moves to right 1 logic module is connect with described 8 with the input terminal of computing module, and described 8
Position moves to right 1 logic module with the described 4th with the output end of computing module and connect, and the described 4th moves to right the defeated of 1 logic module
Outlet is connect with described 2nd 8 with the input terminal of operation, described 2nd 8 with the output end of operation with described 3rd 8 with
The input terminal of operation connects,
The output end of the 2nd 8 bit Inverting device module is connect with described 2nd 8 with another input terminal of computing module,
The input terminal that the output end for moving to left 2 logic modules moves to left 1 logic module with described second is connect, described
Second output end for moving to left 1 logic module is connect with described 3rd 8 with another input terminal of computing module, and the described 3rd 8
Position is connect with the output end of computing module with another input terminal of the 4th 8 bit value comparator module,
The output end of the 8 digit buffer module and the output end of the 4th 8 bit value comparator module and 8 mean values
The input terminal of computing module connects.
Preferably, the output end of the 4th 8 bit value comparator module and the output end of the 8 digit buffer module connect respectively
Two input terminals of 8 mean operation modules are connected to, the output end of 8 mean operation modules is connected with by 8 d type flip flops
The synchronous circuit of composition.
Above, it is simultaneously and concurrently run by clock signal Clk between 8 d type flip flops, is not connected between 8 d type flip flops
It connects, last circuit output is the Q output combinations of 8 triggers.
Since above-mentioned technical proposal is used, the utility model has following advantages compared with prior art：
1. the utility model while filtering algorithm Hardware, realizes that image detail and edge retain to the greatest extent,
High error dot quantity is reduced, filtered visual effect is improved；
2. the utility model evolution filter circuit utilizes the optimizing characteristic of Intelligent evolution algorithm, filtered by comparing sample image
Effect constantly updates filter construction after wavefront, finally seeks one group of suitable function grade relational operation set, evolution is made to filter
Circuit can obtain best filter effect；
3. the evolution circuit of the utility model has very strong hardware realization flexibility, can transplant in multiple hardwares platform
On, provide possibility for real-time use of filtering algorithm.
Description of the drawings
Fig. 1 is the structural schematic diagram of the utility model.
Wherein：1, first 1 logic module is moved to right；2, second 1 logic module is moved to right；3, third moves to right 1 logic mould
Block；4, the 4th 1 logic module is moved to right；5, the one 8 bit Inverting device module；6, the 2nd 8 bit Inverting device module；7, the one 8 digit
It is worth comparator module；8, the 2nd 8 bit value comparator module；9, the 3rd 8 bit value comparator module；10, the 4th 8 bit value ratio
Compared with device module；11,8 XOR operation modules；12, the one 8 and computing module；13, the 2nd 8 and computing module；14, third
8 and computing module；15,8 or computing module；16, first 1 logic module is moved to left；17, second 1 logic module is moved to left；
18,2 logic modules are moved to left；19,8 adder Modules；20,8 digit buffer module；21,8 mean operation modules.
Specific implementation mode
The utility model is further described with reference to the accompanying drawings and embodiments：
Embodiment one：It is shown in Figure 1, a kind of image filtering circuit of removal salt-pepper noise, including first move to right 1 and patrol
Volume module 1, second move to right 1 logic module 2, third moves to right 1 logic module the 3, the 4th and moves to right 1 logic module the 4, the 1st
Bit Inverting device module 5, the 2nd 8 bit Inverting device module 6, the one 8 bit value comparator module 7, the 2nd 8 bit value comparator module
8, the 3rd 8 bit value comparator module 9, the 8 XOR operation modules 11, the 1st of the 4th 8 bit value comparator module 10,1
With computing module 12, the 2nd 8 and computing module 13, the 3rd 8 and computing module 14,18 or computing module 15, first
1 logic module 16 is moved to left, second 1 logic module 17,1 is moved to left and moves to left 2 logic modules, 18,18 adder Modules
19,18 digit buffer module, 20 and 18 mean operation module 21,
The output end of the one 8 bit value comparator module 7 with one of the 2nd 8 bit value comparator module 8
Input terminal connects, the output end of the 2nd 8 bit value comparator module 8 and the one of the 3rd 8 bit value comparator module 9
A input terminal connection, output end and the 4th 8 bit value comparator module 10 of the 3rd 8 bit value comparator module 9
An input terminal connection,
The output end of the one 8 bit Inverting device module is connect with an input terminal of 8 XOR operation modules 11,
The input terminal that the output end of 8 XOR operation modules 11 moves to left 1 logic module 17 with described first is connect, and described first
The output end for moving to left 1 logic module 17 is connect with an input terminal of described 8 or computing module 11, described 8 or operation
The output end of module 11 is connect with another input terminal of the 3rd 8 bit value comparator module 9,
Described first, which moves to right the output end of 1 logic module 1 and described second, moves to right the output end point of 1 logic module 2
It is not connect with the input terminal of 8 adder Modules 19, the output end of 8 adder Modules 19 and 8 exclusive or
Another input terminal of computing module 15 connects,
The output end that the third moves to right 1 logic module 3 is connect with described 8 with the input terminal of computing module 12, institute
It states 8 and moves to right 1 logic module 4 with the described 4th with the output end of computing module 12 and connect, the described 4th moves to right 1 logic mould
The output end of block 4 is connect with described 2nd 8 with the input terminal of operation 13, the 2nd 8 output end with computing module 13
It is connect with the input terminal of computing module 14 with described 3rd 8,
The output end of the 2nd 8 bit Inverting device module 6 and another input terminal of described 2nd 8 and computing module 13 connect
It connects,
The input terminal that the output end for moving to left 2 logic modules 18 moves to left 1 logic module 17 with described second is connect,
Described second output end for moving to left 1 logic module 17 is connect with described 3rd 8 with another input terminal of computing module 14, institute
The 3rd 8 is stated to connect with the output end of computing module 1 with another input terminal of the 4th 8 bit value comparator module 10,
The output end of the 8 digit buffer module 20 and the output end of the 4th 8 bit value comparator module 10 with described 8
The input terminal of mean operation module 21 connects.
In the present embodiment, the output end point of the output end of the 4th 8 bit value comparator module and the 8 digit buffer module
It is not connected to two input terminals of 8 mean operation modules, the output end of 8 mean operation modules is connected with to be touched by 8 D
Send out the synchronous circuit of device composition.
Above, it is simultaneously and concurrently run by clock signal Clk between 8 d type flip flops, is not connected between 8 d type flip flops
It connects, last circuit output is the Q output combinations of 8 triggers.
The utility model is related to explanation of nouns：
1. image filtering：It removes image and is transmitting the processing mode with the inevitable noise generated in acquisition process：
Image carries out the necessary pre-treatment step of other subsequent arithmetics.
2. pixel：0 ~ 255 8 bits, the base unit of image filtering input.
The input of image filtering is as unit of pixel in the utility model, and pixel is 0 ~ 255 8 binary systems
Number, if filtered pixel point is I (x, y), the window of image filtering can be 3 ╳ 3,5 ╳ 5,7 ╳ 7 or 9 ╳ 9, and window is bigger,
Filtered peak signal-to-noise ratio numerical value may be more preferable, but the visual effect of image is easy blurring, while also increasing computing cost,
Therefore the filtering that this patent uses is 3 ╳, 3 windows, calculates 9 pixel { I for taking the field image pixel point I (x, y) every time
(x-1, y), I (x, y), I (x+1, y), I (x-1, y-1), I (x, y-1), I (x+1, y-1), I (x-1, y+1), I (x,
Y+1), I (x+1, y+1) } as input, the output of filter circuit is filtering the latter pixel.T1 ~ T9 is just used in 9 inputs,
Represent 9 pixels of circuit input.
3 ╳, 3 tables share 9 pixels in the present embodiment, and corresponding 9 pixel input terminals, the first row is by a left side from top to bottom
It turns right and is followed successively by the first pixel input terminal, the second pixel input terminal, third pixel input terminal, the second row by being followed successively by from left to right
Four pixel input terminals, the 5th pixel input terminal, the 6th pixel input terminal, the third line are inputted by being followed successively by the 9th pixel from left to right
End, the 8th pixel input terminal, the 7th pixel input terminal, the first pixel input terminal are connected into 1 module 3 of the 3rd 8 bitwise shift right;The
Two pixel input terminals connect 1 module 1 of first input end and the one 8 bitwise shift right of the one 8 bit value comparator module 7;Third
Pixel input terminal connects the 2nd 8 bit Inverting device module 6 and the 2nd 8 bit value comparator module 8;4th pixel input terminal connects
2nd 8 module 2 of bitwise shift right 1;5th pixel input terminal connects 8 XOR operation modules 11;6th pixel input terminal connection 8
2 modules 18 of bitwise shift left;7th pixel input terminal connects the second input terminal of the one 8 bit value comparator module 7;8th picture
Plain input terminal connects the one 8 bit Inverting device module 5;9th pixel input terminal connects 8 digit buffer modules 20.
The comprising modules of the filter circuit of the utility model, in circuit the basic operation of each logic module be 2 inputs (as
Vegetarian refreshments) logical function, to set with（ADD）Or（OR）, it is non-（NOT）Be " base " circuit for, be exactly 16 two into
It is made as the logical operation of input, the minimum window of filtering operation is 3 ╳ 3 (9 pixels), and filter circuit is exactly 72 inputs
Fairly large circuit, it can evolve with 8 binary logic operation set（Such as：{ displacement（Shift）, addition（ADD）, position
With（bit AND）, position or（bit OR）, position exclusive or（bit XOR）}）For the circuit of " base ", can effectively evolve filtering operation electricity
Road.
Include in the circuit structure in the utility model：" moving to right 1 " logic module 4, " 8 bit Inverting device " 2, " 8
Bit value comparator " 4, " 8 XOR operation " module 1, " 8 ' with ' operation " module 3, " 8 ' or ' operation " mould
Block 1, " moving to left 1 " logic module 2, " moving to right 2 " logic module 1, " 8 adders " 1, " 8 bit bufferings
Device " 1, " 8 mean operation modules " 1 and 8 d type flip flops.The synchronization being made of 8 d type flip flops is added in output end
Circuit is added and eliminates competition and venture mechanism, achieve the purpose that eliminate competition and venture in output end.
The circuit FPGA of salt-pepper noise filtering is realized.Each module of filter circuit is 16 inputs, shares 19
Therefore such module is designed module using the programmable logic system of FPGA, user not only can easily design
The logic function for going out each module of required filter circuit realizes the overprogram of system, to which development difficulty greatly reduce,
The R＆D cycle is shortened, system running speed is improved.
Hardware realization of 1 filter circuit of table in EPM9320LC84-15
| In | LCs | Utilized | P-terms | |
| The filter circuit for removing salt-pepper noise is realized | 31 | 45/320 | 14% | 150 |
It is salt-pepper noise circuit shown in upper table in FPGA hardware platform, no longer needs to carry out complicated algorithm to hardware
Conversion.Device EPM9320LC84-15 platform of the application by obtained filter circuit logic in Ateral is realized.In table 1
In indicates that the quantity of input pin, LCs are logic cell quantity, and P-terms is product term quantity, and Utilized indicates resource
Utilization rate.From result viewing to the hardware resource consumption of the evolution filter circuit obtained under salt-pepper noise is relatively low.
Here is the application of the utility model：
Experimental noise：The salt-pepper noise that variance D is 0.12,0.16,0.2.Noise is loaded into 13 normal pictures（256╳
256）Learnt, obtained circuit simultaneously tests lenna, baboon picture.
The utility model filter circuit and a variety of airspace filter methods（In mean value, intermediate value, vector intermediate value and vector direction
Value）, frequency domain Wavelet noise-eliminating method and the evolution filter circuit (Evolutionary of optimization aim is minimised as with MAE
Image Filter-EIF）[13] it is compared.All data of the application are the program operation gained of this seminar exploitation,
In experimental result, MF indicates medium filtering；VMF indicates vector medium filtering；BVDF indicates vector directional medial filtering；AF tables
Show mean filter；Wavelet indicates wavelet filter.
Case study on implementation is divided into 2 parts：
1）The comparison that the utility model filter circuit, MF and BVDF details and edge retain；
2）The comparison of the utility model filter circuit and EIF.
1) comparison that details and edge retain
Edge reservation and noise spot of the utility model filter circuit with MF, BVDF filtering compare, due to MF and VMF effects
It is close, select MF for comparison other.It is observed that the utility model filter circuit retains in the spiced salt and impulsive noise lower edge
Preferably, although MF clarity is high, noise spot quantity is decreased obviously, the utility model filter circuit ability in edge reserve capability
It is stronger.At the more lenna hairs in edge and at baboon hairs, the edge-smoothing of MF, and the edge of MEIF remains able to
Preferably retain, the edge of BVDF is more preferable compared with MF, more slightly worse than filter circuit of the present invention.BVDF under the spiced salt and impulsive noise,
Noise spot is all obvious, especially occurs intensive noise spot in baboon images.
2) comparison of the utility model circuit and EIF
According to the previous achievement in the field it is found that EIF equally has a preferable noise removal capability, on the overall filter effect of EIF
It is close with filter circuit of the present invention, regional area also smaller with filter circuit difference of the present invention on PSNR and MSE, but filtering
Noise spot it is more obvious.To the filter effect of salt-pepper noise (lenna figures), EIF's is big for EIF and the utility model filter circuit
Error noise point is more than the utility model filter circuit, and in the lower region of the gray value of image, the noise spot of EIF is got over
It is apparent.
Claims (2)
1. a kind of image filtering circuit of removal salt-pepper noise, it is characterised in that：1 logic module, second are moved to right including first
Move to right 1 logic module, third moves to right 1 logic module, the 4th moves to right 1 logic module, the one 8 bit Inverting device module,
28 bit Inverting device modules, the one 8 bit value comparator module, the 2nd 8 bit value comparator module, the 3rd 8 bit value comparator
Module, the 4th 8 bit value comparator module, 18 XOR operation module, the one 8 and computing module, the 2nd 8 and operation
Module, the 3rd 8 move to left 1 logic module with computing module, 18 or computing module, first, second move to left 1 logic mould
Block, 1 move to left 2 logic modules, 18 adder Module, 18 digit buffer module and 18 mean operation module,
One input terminal of the output end and the 2nd 8 bit value comparator module of the one 8 bit value comparator module
Connection, an input terminal of the output end and the 3rd 8 bit value comparator module of the 2nd 8 bit value comparator module
Connection, an input terminal of the output end and the 4th 8 bit value comparator module of the 3rd 8 bit value comparator module
Connection,
The output end of the one 8 bit Inverting device module is connect with an input terminal of 8 XOR operation modules, and described 8
The input terminal that the output end of position XOR operation module moves to left 1 logic module with described first is connect, and described first, which moves to left 1, patrols
The output end of volume module is connect with an input terminal of described 8 or computing module, the output end of described 8 or computing module and
Another input terminal of the 3rd 8 bit value comparator module connects,
Described first move to right the output end of 1 logic module and described second move to right the output end of 1 logic module respectively with institute
State the input terminal connection of 8 adder Modules, the output end of 8 adder Modules and 8 XOR operation modules
Another input terminal connects,
The output end that the third moves to right 1 logic module is connect with described 8 with the input terminal of computing module, described 8 with
The output end of computing module moves to right 1 logic module with the described 4th and connect, and the described 4th moves to right the output end of 1 logic module
It is connect with the input terminal of operation with described 2nd 8, described 2nd 8 output end and described 3rd 8 and operation with operation
Input terminal connection,
The output end of the 2nd 8 bit Inverting device module is connect with described 2nd 8 with another input terminal of computing module,
The input terminal that the output end for moving to left 2 logic modules moves to left 1 logic module with described second is connect, and described second
The output end for moving to left 1 logic module is connect with described 3rd 8 with another input terminal of computing module, described 3rd 8 with
The output end of computing module is connect with another input terminal of the 4th 8 bit value comparator module,
The output end of the 8 digit buffer module and the output end of the 4th 8 bit value comparator module and 8 mean operations
The input terminal of module connects.
2. the image filtering circuit of removal salt-pepper noise according to claim 1, it is characterised in that：4th 8 bit value ratio
Compared with the output end of the output end of device module and the 8 digit buffer module be connected respectively to two of 8 mean operation modules it is defeated
Enter end, the output end of 8 mean operation modules is connected with the synchronous circuit being made of 8 d type flip flops.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109741286A (en) * | 2019-02-19 | 2019-05-10 | 厦门码灵半导体技术有限公司 | Median filter method, device, storage medium and electronic equipment |
| CN110580919A (en) * | 2019-08-19 | 2019-12-17 | 东南大学 | voice feature extraction method and reconfigurable voice feature extraction device under multi-noise scene |
-
2017
- 2017-09-15 CN CN201721204701.2U patent/CN207909193U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109741286A (en) * | 2019-02-19 | 2019-05-10 | 厦门码灵半导体技术有限公司 | Median filter method, device, storage medium and electronic equipment |
| CN110580919A (en) * | 2019-08-19 | 2019-12-17 | 东南大学 | voice feature extraction method and reconfigurable voice feature extraction device under multi-noise scene |
| CN110580919B (en) * | 2019-08-19 | 2021-09-28 | 东南大学 | Voice feature extraction method and reconfigurable voice feature extraction device under multi-noise scene |
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