CN207720101U - A kind of doubleway output frequency tunable clock signal generator - Google Patents
A kind of doubleway output frequency tunable clock signal generator Download PDFInfo
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- CN207720101U CN207720101U CN201721777045.5U CN201721777045U CN207720101U CN 207720101 U CN207720101 U CN 207720101U CN 201721777045 U CN201721777045 U CN 201721777045U CN 207720101 U CN207720101 U CN 207720101U
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Abstract
A kind of doubleway output frequency tunable clock signal generator includes duty ratio voltage conversion circuit, delay oscillating circuit.Two-way can realize that the differential signal of duty ratio dynamic scaling is inputted from two input terminals of duty ratio voltage conversion circuit respectively, and be converted into the output of two-way voltage control signal.Two-way voltage control signal distinguishes the control terminal of input delay oscillating circuit, and the identical clock signal of final output two-way frequency.By carrying out duty ratio scaling to input differential signal, the output signal frequency of clock-signal generator can be changed.The two-way pressure control structure of the utility model keeps the clock frequency signal of its output more efficiently and accurate.Demand for circuit system to different frequency clock signal, the utility model can export clock signal by the duty ratio of scaling input differential signal in wider frequency range.
Description
Technical field
The utility model is related to the designs of clock-signal generator, and in particular to, a kind of doubleway output frequency is adjustable
The design of clock-signal generator.
Background technology
Clock-signal generator provides stable clock signal and reference signal for electronic system, and it is logical to be widely used in electronics
In the electronic circuits such as news system, electronic timing system, controller, computer.The clock-signal generator generally used at present is more
For quartz oscillator structure, the metastable clock frequency signal of essence can be generated under various environmental conditions.But with
The development of electronic integration technology, the volume and power consumption of the clock-signal generator of quartz oscillator structure have been unable to meet and need
It asks.Also, the work of circuit system usually requires the clock signal of multi-frequency, and general solution is to use multiple clock
Signal generator.This method not only increases design difficulty and also increases cost.The utility model is in view of the above problems, propose
A kind of small size, low-power consumption, the adjustable non-crystal oscillator structure of output frequency clock-signal generator.
Utility model content
The technical problem to be solved by the utility model is to provide a kind of doubleway output frequency tunable clock signal generators.
The technical solution of the utility model is as follows：A kind of doubleway output frequency tunable clock signal generator includes duty ratio
Voltage conversion circuit, delay oscillating circuit.Two-way can realize the differential signal of duty ratio dynamic scaling respectively from duty ratio voltage
Two input terminals of conversion circuit input, and are converted into the output of two-way voltage control signal.Input delay shakes two-way voltage control signal respectively
Swing the control terminal of circuit, and the identical clock signal of final output two-way frequency.By carrying out duty ratio to input differential signal
The output signal frequency of clock-signal generator can be changed in scaling.
In a kind of doubleway output frequency tunable clock signal generator, duty ratio voltage conversion circuit is by input differential signal
Voltage control signal is converted to, and is transferred to delay oscillating circuit.Duty ratio voltage conversion circuit includes mainly that No. 1 differential signal inputs
Port, No. 2 differential signal input mouths, No. 1 delay circuit, No. 1 buffer, No. 2 buffers, 1 AND gate, 2 AND gates, No. 7
To No. 14 metal-oxide-semiconductors, No. 1 capacitance, No. 2 capacitances.Wherein No. 1 differential signal input mouth connects No. 1 input of No. 1 delay circuit
End, No. 2 differential signal input mouths connect No. 2 input terminals of No. 1 delay circuit.No. 1 output end connection 1 of No. 1 delay circuit
The lower input terminal of AND gate, the upper input terminal of No. 2 output ends 2 AND gates of connection of No. 1 delay circuit, No. 3 of No. 1 delay circuit
Output end connects the upper end of No. 2 capacitances.The input terminal of No. 1 buffer connects No. 1 differential signal input mouth, No. 1 buffer
Output end connects the grid of No. 7 metal-oxide-semiconductors.The input terminal of No. 2 buffers connects No. 2 differential signal input mouths, No. 2 buffers
Output end connects the grid of No. 10 metal-oxide-semiconductors.The upper input terminal of 1 AND gate connects No. 1 differential signal input mouth, 1 AND gate
Output end connects the source electrode of No. 7 metal-oxide-semiconductors.The lower input terminals of 2 AND gates connects No. 2 differential signal input mouths, 2 AND gates it is defeated
Outlet connects the source electrode of No. 10 metal-oxide-semiconductors.The source electrode of No. 7 metal-oxide-semiconductors connects the source electrode of No. 8 metal-oxide-semiconductors, the drain electrode connection 8 of No. 7 metal-oxide-semiconductors
The drain electrode of number metal-oxide-semiconductor.The grid of No. 8 metal-oxide-semiconductors connects the output end of No. 2 buffers.The grid of No. 9 metal-oxide-semiconductors connects No. 1 buffer
Output end, the source electrode of No. 9 metal-oxide-semiconductors connects the source electrode of No. 10 metal-oxide-semiconductors, the drain electrode of drain electrode No. 10 metal-oxide-semiconductors of connection of No. 9 metal-oxide-semiconductors.
The grid of No. 11 metal-oxide-semiconductors connects the grid of No. 7 metal-oxide-semiconductors, and the source electrode of No. 11 metal-oxide-semiconductors connects the source electrode of No. 12 metal-oxide-semiconductors and connects 11
The drain electrode of number metal-oxide-semiconductor.The grid of No. 12 metal-oxide-semiconductors connects the grid of No. 10 metal-oxide-semiconductors, and the source electrode of No. 12 metal-oxide-semiconductors connects No. 12 metal-oxide-semiconductors
Drain electrode.The grid of No. 13 metal-oxide-semiconductors connects the grid of No. 11 metal-oxide-semiconductors, and the source electrode of No. 13 metal-oxide-semiconductors connects the source electrode of No. 14 metal-oxide-semiconductors
And connect the drain electrode of No. 13 metal-oxide-semiconductors.The grid of No. 14 metal-oxide-semiconductors connects the grid of No. 12 metal-oxide-semiconductors, the source electrode connection of No. 14 metal-oxide-semiconductors
The drain electrode of No. 14 metal-oxide-semiconductors.The upper end of No. 1 capacitance connects the drain electrode of No. 8 metal-oxide-semiconductors, the lower end ground connection of No. 1 capacitance.No. 2 capacitances it is upper
The drain electrode of No. 10 metal-oxide-semiconductors of end connection, the lower end ground connection of No. 2 capacitances.
In a kind of doubleway output frequency tunable clock signal generator, the delay circuit packet in duty ratio voltage conversion circuit
Include No. 1 to No. 5 metal-oxide-semiconductor, No. 1 to No. 2 import and export end, No. 1 to No. 3 output end.The grid of wherein No. 1 metal-oxide-semiconductor connects No. 3 outputs
The source electrode at end, No. 1 metal-oxide-semiconductor connects power supply, and the drain electrode of No. 1 metal-oxide-semiconductor connects No. 1 output end.The grid connection 2 of No. 2 metal-oxide-semiconductors is defeated
Outlet, the source electrode of No. 2 metal-oxide-semiconductors connect the source electrode of No. 1 metal-oxide-semiconductor, the drain electrode of drain electrode No. 1 metal-oxide-semiconductor of connection of No. 2 metal-oxide-semiconductors.No. 3 MOS
The grid of pipe connects No. 1 output end, and the source electrode of No. 3 metal-oxide-semiconductors connects power supply, and the drain electrode of No. 3 metal-oxide-semiconductors connects No. 2 output ends.No. 4
The source electrode of metal-oxide-semiconductor connects the source electrode of No. 3 metal-oxide-semiconductors, the drain electrode of drain electrode No. 3 metal-oxide-semiconductors of connection of No. 4 metal-oxide-semiconductors.The grid of No. 5 metal-oxide-semiconductors
No. 1 input terminal is connected, the drain electrode of No. 5 metal-oxide-semiconductors connects No. 1 output end, the source electrode ground connection of No. 5 metal-oxide-semiconductors.The grid of No. 6 metal-oxide-semiconductors connects
No. 2 input terminals are connect, the drain electrode of No. 6 metal-oxide-semiconductors connects No. 2 output ends, the source electrode ground connection of No. 6 metal-oxide-semiconductors.
In a kind of doubleway output frequency tunable clock signal generator, delay oscillating circuit receives voltage control signal, and exports
The identical clock signal of two-way frequency.Postpone oscillating circuit include No. 1 to No. 4 delay cell, No. 1 clock signal output terminal mouth, 2
Number clock signal output terminal mouth.No. 1 input terminal of wherein No. 1 delay cell connects No. 1 clock signal output terminal mouth, No. 1 delay
No. 2 input terminals of unit connect No. 2 clock signal output terminal mouths.No. 1 control terminal of No. 1 delay cell connects the upper of No. 1 capacitance
End, No. 2 control terminals of No. 1 delay cell connect the upper end of No. 2 capacitances.No. 1 output end of No. 1 delay cell connects No. 2 delays
No. 1 input terminal of unit, No. 2 output ends of No. 1 delay cell connect No. 2 input terminals of No. 2 delay cell.No. 2 delay cells
No. 1 control terminal connect No. 1 control terminal of No. 1 delay cell, No. 2 control terminals of No. 2 delay cell connect No. 1 delay cell
No. 2 control terminals.No. 1 output end of No. 2 delay cell connects No. 1 input terminal of No. 3 delay cell, and No. 2 of No. 2 delay cell are defeated
Outlet connects No. 2 input terminals of No. 3 delay cell.No. 1 control terminal of No. 3 delay cell connects No. 1 control of No. 2 delay cell
End, No. 2 control terminals of No. 3 delay cell connect No. 2 control terminals of No. 2 delay cell.No. 1 output end of No. 3 delay cell connects
No. 1 input terminal of No. 4 delay cell is connect, No. 2 output ends of No. 3 delay cell connect No. 2 input terminals of No. 4 delay cell.No. 4
No. 1 control terminal of delay cell connects No. 1 control terminal of No. 3 delay cell, and No. 2 control terminals of No. 4 delay cell connect No. 3 and prolong
No. 2 control terminals of slow unit.No. 1 output end of No. 4 delay cell connects No. 1 clock signal output terminal mouth, No. 4 delay cell
No. 2 output ends connect No. 2 clock signal output terminals.
In a kind of doubleway output frequency tunable clock signal generator, postpone No. 1 to No. 4 delay cell in oscillating circuit
Internal structure having the same, delay cell include No. 15 to No. 22 metal-oxide-semiconductors, No. 1 to No. 2 input terminal, No. 1 to No. 2 control terminal,
No. 1 to No. 2 output end.Grid No. 1 control terminal of connection of wherein No. 15 metal-oxide-semiconductors, the source electrode connection power supply of No. 15 metal-oxide-semiconductors, No. 15
The source electrode of drain electrode No. 16 metal-oxide-semiconductors of connection of metal-oxide-semiconductor.The grid of No. 16 metal-oxide-semiconductors connects No. 1 output end, and the drain electrode of No. 16 metal-oxide-semiconductors connects
Connect the drain electrode of No. 17 metal-oxide-semiconductors.The source electrode of No. 17 metal-oxide-semiconductors connects the source electrode of No. 15 metal-oxide-semiconductors, and the grid of No. 17 metal-oxide-semiconductors connects No. 18
The drain electrode of metal-oxide-semiconductor, the drain electrode of drain electrode No. 20 metal-oxide-semiconductors of connection of No. 17 metal-oxide-semiconductors.Source electrode No. 17 metal-oxide-semiconductors of connection of No. 18 metal-oxide-semiconductors
Source electrode, the grid of No. 18 metal-oxide-semiconductors connect the drain electrode of No. 17 metal-oxide-semiconductors, the drain electrode of drain electrode No. 19 metal-oxide-semiconductors of connection of No. 18 metal-oxide-semiconductors.19
The source electrode of number metal-oxide-semiconductor connects the source electrode of No. 16 metal-oxide-semiconductors, and the grid of No. 19 metal-oxide-semiconductors connects No. 2 output ends, the drain electrode of No. 19 metal-oxide-semiconductors
Connect the drain electrode of No. 21 metal-oxide-semiconductors.The drain electrode of No. 20 metal-oxide-semiconductors connects No. 1 output end, and the grid of No. 20 metal-oxide-semiconductors connects No. 1 input
End, the source electrode of No. 20 metal-oxide-semiconductors connect the drain electrode of No. 22 metal-oxide-semiconductors.The drain electrode of No. 21 metal-oxide-semiconductors connects No. 2 output ends, No. 21 metal-oxide-semiconductors
Grid connect No. 2 input terminals, the source electrode of No. 21 metal-oxide-semiconductors connects the source electrode of No. 20 metal-oxide-semiconductors.The grid of No. 22 metal-oxide-semiconductors connects No. 2
Control terminal, the source electrode ground connection of No. 22 metal-oxide-semiconductors.
The two-way pressure control structure of the utility model keeps the clock frequency signal of its output more efficiently and accurate.For circuit
Demand of the system to different frequency clock signal, the utility model, can be wider by the duty ratio of scaling input differential signal
Clock signal is exported in frequency range.The utility model uses full MOS structure, and the clock signal relative to crystal oscillator structure occurs
Device, power consumption is extremely low, and volume is more small, and good with system globe area, cost is lower.
Description of the drawings
Fig. 1 is the circuit structure diagram of the utility model.
Fig. 2 be the utility model duty ratio voltage conversion circuit in delay circuit structure chart.
Fig. 3 is the structure chart for postponing delay cell in oscillating circuit of the utility model.
Specific implementation mode
For the ease of understanding the utility model, in the following with reference to the drawings and specific embodiments, the utility model is carried out more detailed
Thin explanation.The preferred embodiment of the utility model is given in this specification and its attached drawing, still, the utility model can be with
It realizes in many different forms, however it is not limited to this specification described embodiment.On the contrary, providing these embodiments
Purpose is to make the understanding of the disclosure of the utility model more thorough and comprehensive.
It should be noted that when a certain element is fixed on another element, including that the element is directly fixed on this is another
A element, or the element is fixed on another element by least one other elements placed in the middle.When an element connects
It connects another element, including the element is directly connected to another element, or the element passed through at least one placed in the middle
Other elements be connected to another element.
As shown in Figure 1, the utility model includes duty ratio voltage conversion circuit, delay oscillating circuit.Two-way can be realized and be accounted for
Sky is inputted from two input terminals of duty ratio voltage conversion circuit respectively than the differential signal of dynamic scaling, and is converted into two-way pressure
Control signal output.Two-way voltage control signal distinguishes the control terminal of input delay oscillating circuit, and final output two-way frequency is identical
Clock signal.By carrying out duty ratio scaling to input differential signal, the output signal frequency of clock-signal generator can be changed.
As shown in Figure 1, duty ratio voltage conversion circuit includes mainly differential signal input mouth Din1, differential signal input
Port Din2, delay circuit DU1, buffer B1, buffer B2, and door A1, with door A2, metal-oxide-semiconductor M7 to M14, capacitance C1, capacitance
C2.The wherein input terminal Fi1 of differential signal input mouth Din1 connection delay circuits DU1, differential signal input mouth Din2 connect
Meet the input terminal Fi2 of delay circuit DU1.The lower input terminal of the output end P1 connections and door A1 of delay circuit DU1, delay circuit
The upper input terminal of the output end P2 connections and door A2 of DU1, the upper end of the output end Vn connection capacitances C2 of delay circuit DU1.Buffering
The grid of the output end connection metal-oxide-semiconductor M7 of input terminal connection differential signal input the mouth Din1, buffer B1 of device B1.Buffer
The grid of the output end connection metal-oxide-semiconductor M10 of input terminal connection differential signal input the mouth Din2, buffer B2 of B2.With door A1
Upper input terminal connect differential signal input mouth Din1, the source electrode of metal-oxide-semiconductor M7 is connect with the output end of door A1.With under door A2
Input terminal connects differential signal input mouth Din2, and the source electrode of metal-oxide-semiconductor M10 is connect with the output end of door A2.The source electrode of metal-oxide-semiconductor M7
Connect the source electrode of metal-oxide-semiconductor M8, the drain electrode of the drain electrode connection metal-oxide-semiconductor M8 of metal-oxide-semiconductor M7.The grid connection buffer B2's of metal-oxide-semiconductor M8
Output end.The output end of the grid connection buffer B1 of metal-oxide-semiconductor M9, the source electrode of the source electrode connection metal-oxide-semiconductor M10 of metal-oxide-semiconductor M9, MOS
The drain electrode of the drain electrode connection metal-oxide-semiconductor M10 of pipe M9.The grid of the grid connection metal-oxide-semiconductor M7 of metal-oxide-semiconductor M11, the source electrode of metal-oxide-semiconductor M11 connect
It connects the source electrode of metal-oxide-semiconductor M12 and connects the drain electrode of metal-oxide-semiconductor M11.The grid of the grid connection metal-oxide-semiconductor M10 of metal-oxide-semiconductor M12, metal-oxide-semiconductor
The drain electrode of the source electrode connection metal-oxide-semiconductor M12 of M12.The grid of the grid connection metal-oxide-semiconductor M11 of metal-oxide-semiconductor M13, the source electrode of metal-oxide-semiconductor M13 connect
It connects the source electrode of metal-oxide-semiconductor M14 and connects the drain electrode of metal-oxide-semiconductor M13.The grid of the grid connection metal-oxide-semiconductor M12 of metal-oxide-semiconductor M14, metal-oxide-semiconductor
The drain electrode of the source electrode connection metal-oxide-semiconductor M14 of M14.The drain electrode of the upper end connection metal-oxide-semiconductor M8 of capacitance C1, the lower end ground connection of capacitance C1.Electricity
Hold the drain electrode of the upper end connection metal-oxide-semiconductor M10 of C2, the lower end ground connection of capacitance C2.
As shown in Fig. 2, the delay circuit in duty ratio voltage conversion circuit includes metal-oxide-semiconductor M1 to M5, import and export end Fi1 and
Fi2, output end P1 and P2, output end Vn.The grid of wherein metal-oxide-semiconductor M1 connects output end Vn, and the source electrode of metal-oxide-semiconductor M1 connects power supply
The drain electrode connection output end P1 of VDD, metal-oxide-semiconductor M1.The grid of metal-oxide-semiconductor M2 connects output end P2, and the source electrode of metal-oxide-semiconductor M2 connects MOS
The source electrode of pipe M1, the drain electrode of the drain electrode connection metal-oxide-semiconductor M1 of metal-oxide-semiconductor M2.The grid of metal-oxide-semiconductor M3 connects output end P1, metal-oxide-semiconductor M3's
Source electrode connects power vd D, the drain electrode connection output end P2 of metal-oxide-semiconductor M3.The source electrode of the source electrode connection metal-oxide-semiconductor M3 of metal-oxide-semiconductor M4, MOS
The drain electrode of the drain electrode connection metal-oxide-semiconductor M3 of pipe M4.The grid of metal-oxide-semiconductor M5 connects input terminal Fi1, the drain electrode connection output of metal-oxide-semiconductor M5
Hold P1, the source electrode ground connection of metal-oxide-semiconductor M5.The grid of metal-oxide-semiconductor M6 connects input terminal Fi2, and the drain electrode of metal-oxide-semiconductor M6 connects output end P2,
The source electrode of metal-oxide-semiconductor M6 is grounded.
As shown in Figure 1, delay oscillating circuit includes CU1 to CU4 delay cells, clock signal output terminal mouth Fout1, clock
Signal output port Fout2.The input terminal VI1 connection clock signal output terminal mouth Fout1 of wherein delay cell CU1, delay are single
The input terminal VI2 connection clock signal output terminal mouths Fout2 of first CU1.The control terminal VC1 connection capacitances C1's of delay cell CU1
Upper end, the upper end C2 of the control terminal VC2 connection capacitances of delay cell CU1.The output end VO1 connection delay lists of delay cell CU1
The input terminal VI2 of the output end VO2 connection delay units CU2 of input terminal VI1, the CU1 delay cell of first CU2.Delay cell CU2
Control terminal VC1 connection delay units CU1 control terminal VC1, the control terminal VC2 connection delay units CU1's of delay cell CU2
Control terminal VC2.The input terminal VI1 of the output end VO1 connection delay units CU3 of delay cell CU2, the output of delay cell CU2
Hold the input terminal VI2 of VO2 connection delay units CU3.The control terminal of the control terminal VC1 connection delay units CU2 of delay cell CU3
The control terminal VC2 of the control terminal VC2 connection delay units CU2 of VC1, delay cell CU3.The output end VO1 of delay cell CU3 connects
Meet the input terminal VI1 of delay cell CU4, the input terminal VI2 of the output end VO2 connection delay units CU4 of delay cell CU3.Prolong
The control terminal VC1 of the control terminal VC1 connection delay units CU3 of slow unit CU4, the control terminal VC2 connection delays of delay cell CU4
The control terminal VC2 of unit CU3.The output end VO1 connection clock signal output terminal mouth Foutl of delay cell CU4, delay cell
The output end VO2 connection clock signal output terminal mouths Fout2 of CU4.
As shown in figure 3, delay cell CU1 to the CU4 internal structures having the same in delay oscillating circuit, delay cell
Including metal-oxide-semiconductor M15 to M22, input terminal VI1 and VI2, control terminal VC1 and VC2, output end VO1 and VO2.Wherein metal-oxide-semiconductor M15's
Grid connects control terminal VC1, and the source electrode of metal-oxide-semiconductor M15 connects power vd D, the source electrode of the drain electrode connection metal-oxide-semiconductor M16 of metal-oxide-semiconductor M15.
The grid of metal-oxide-semiconductor M16 connects output end VO1, the drain electrode of the drain electrode connection metal-oxide-semiconductor M17 of metal-oxide-semiconductor M16.The source electrode of metal-oxide-semiconductor M17 connects
Meet the source electrode of metal-oxide-semiconductor M15, the drain electrode of the grid connection metal-oxide-semiconductor M18 of metal-oxide-semiconductor M17, the drain electrode connection metal-oxide-semiconductor M20 of metal-oxide-semiconductor M17
Drain electrode.The source electrode of the source electrode connection metal-oxide-semiconductor M17 of metal-oxide-semiconductor M18, the drain electrode of the grid connection metal-oxide-semiconductor M17 of metal-oxide-semiconductor M18, MOS
The drain electrode of the drain electrode connection metal-oxide-semiconductor M19 of pipe M18.The source electrode of the source electrode connection metal-oxide-semiconductor M16 of metal-oxide-semiconductor M19, the grid of metal-oxide-semiconductor M19
Connect output end VO2, the drain electrode of the drain electrode connection metal-oxide-semiconductor M21 of metal-oxide-semiconductor M19.The drain electrode of metal-oxide-semiconductor M20 connects defeated end VO1, MOS
The grid of pipe M20 connects input terminal VI1, the drain electrode of the source electrode connection metal-oxide-semiconductor M22 of metal-oxide-semiconductor M20.The drain electrode of metal-oxide-semiconductor M21 connects
The grid of output end VO2, metal-oxide-semiconductor M21 connect input terminal VI2, the source electrode of the source electrode connection metal-oxide-semiconductor M20 of metal-oxide-semiconductor M21.Metal-oxide-semiconductor
The grid of M22 connects control terminal VC2, the source electrode ground connection of metal-oxide-semiconductor M22.
A kind of change in duty cycle of the input differential signal of doubleway output frequency tunable clock signal generator is ranging from
20% to 80%.The variation range of the clock signal frequency of output is 40KHz to 34MHz.
Such as：Under the conditions of 0.18um CMOS technologies, chip area footprints 0.07mm2, power vd D is 0.9V, capacitance C1
It is 64PF for 64PF, capacitance C2, the duty ratio of differential input signal FIN1 is 60%, and the duty ratio of differential input signal FIN2 is
40%, then the voltage control signal COR1 of duty ratio voltage conversion circuit output is 600mV, and voltage control signal COR2 is 350mV, when two-way
The clock signal frequency of clock signal output port output is 20MHz, and clock-signal generator system power dissipation is 93.6uW.It needs
Bright, above-mentioned each technical characteristic continues to be combined with each other, and forms the various embodiments not being enumerated above, and it is new to be accordingly to be regarded as this practicality
The range that type specification is recorded；Also, for those of ordinary skills, it can be improved or be become according to the above description
It changes, and all these modifications and variations should all belong to the protection domain of its appended claims of the utility model.
Claims (5)
1. a kind of doubleway output frequency tunable clock signal generator, which is characterized in that it include duty ratio voltage conversion circuit,
Postpone oscillating circuit；
Two-way can realize that the differential signal of duty ratio dynamic scaling is defeated from two input terminals of duty ratio voltage conversion circuit respectively
Enter, and is converted into the output of two-way voltage control signal；
Two-way voltage control signal distinguishes the control terminal of input delay oscillating circuit, and the identical clock letter of final output two-way frequency
Number；
By carrying out duty ratio scaling to input differential signal, the output signal frequency of clock-signal generator can be changed.
2. a kind of doubleway output frequency tunable clock signal generator according to claim 1, which is characterized in that duty ratio electricity
Voltage conversion circuit includes differential signal input mouth Din1, differential signal input mouth Din2, delay circuit DU1, buffer B1,
Buffer B2, and door A1, with door A2, metal-oxide-semiconductor M7 to M14, capacitance C1, capacitance C2；
The input terminal Fi1 of differential signal input mouth Din1 connection delay circuits DU1, the Din2 connections of differential signal input mouth are prolonged
The input terminal Fi2 of slow circuit DU1；
The lower input terminal of the output end P1 connections and door A1 of delay circuit DU1, output end P2 connections and the door A2 of delay circuit DU1
Upper input terminal, the upper end of the output end Vn connection capacitances C2 of delay circuit DU1；
The grid of the output end connection metal-oxide-semiconductor M7 of input terminal connection differential signal input the mouth Din1, buffer B1 of buffer B1
Pole；
The grid of the output end connection metal-oxide-semiconductor M10 of input terminal connection differential signal input the mouth Din2, buffer B2 of buffer B2
Pole；
It is connect differential signal input mouth Din1 with the upper input terminal of door A1, the source electrode of metal-oxide-semiconductor M7 is connect with the output end of door A1；
It is connect differential signal input mouth Din2 with the lower input terminal of door A2, the source of metal-oxide-semiconductor M10 is connect with the output end of door A2
Pole；
The source electrode of the source electrode connection metal-oxide-semiconductor M8 of metal-oxide-semiconductor M7, the drain electrode of the drain electrode connection metal-oxide-semiconductor M8 of metal-oxide-semiconductor M7；
The output end of the grid connection buffer B2 of metal-oxide-semiconductor M8；
The output end of the grid connection buffer B1 of metal-oxide-semiconductor M9, the source electrode of the source electrode connection metal-oxide-semiconductor M10 of metal-oxide-semiconductor M9, metal-oxide-semiconductor M9
Drain electrode connection metal-oxide-semiconductor M10 drain electrode；
The grid of the grid connection metal-oxide-semiconductor M7 of metal-oxide-semiconductor M11, the source electrode of the source electrode connection metal-oxide-semiconductor M12 of metal-oxide-semiconductor M11 simultaneously connect MOS
The drain electrode of pipe M11；
The grid of the grid connection metal-oxide-semiconductor M10 of metal-oxide-semiconductor M12, the drain electrode of the source electrode connection metal-oxide-semiconductor M12 of metal-oxide-semiconductor M12；
The grid of the grid connection metal-oxide-semiconductor M11 of metal-oxide-semiconductor M13, the source electrode of metal-oxide-semiconductor M13 connect source electrode and the connection of metal-oxide-semiconductor M14
The drain electrode of metal-oxide-semiconductor M13；
The grid of the grid connection metal-oxide-semiconductor M12 of metal-oxide-semiconductor M14, the drain electrode of the source electrode connection metal-oxide-semiconductor M14 of metal-oxide-semiconductor M14；
The drain electrode of the upper end connection metal-oxide-semiconductor M8 of capacitance C1, the lower end ground connection of capacitance C1；
The drain electrode of the upper end connection metal-oxide-semiconductor M10 of capacitance C2, the lower end ground connection of capacitance C2.
3. a kind of doubleway output frequency tunable clock signal generator according to claim 1, which is characterized in that duty ratio electricity
Delay circuit in voltage conversion circuit includes metal-oxide-semiconductor M1 to M5, import and export end Fi1 and Fi2, output end P1 and P2, output end Vn；
The grid of metal-oxide-semiconductor M1 connects output end Vn, and the source electrode of metal-oxide-semiconductor M1 connects power vd D, the drain electrode connection output of metal-oxide-semiconductor M1
Hold P1；
The grid of metal-oxide-semiconductor M2 connects output end P2, the source electrode of the source electrode connection metal-oxide-semiconductor M1 of metal-oxide-semiconductor M2, and the drain electrode of metal-oxide-semiconductor M2 connects
Connect the drain electrode of metal-oxide-semiconductor M1；
The grid of metal-oxide-semiconductor M3 connects output end P1, and the source electrode of metal-oxide-semiconductor M3 connects power vd D, the drain electrode connection output of metal-oxide-semiconductor M3
Hold P2；
The source electrode of the source electrode connection metal-oxide-semiconductor M3 of metal-oxide-semiconductor M4, the drain electrode of the drain electrode connection metal-oxide-semiconductor M3 of metal-oxide-semiconductor M4；
The grid of metal-oxide-semiconductor M5 connects input terminal Fi1, and the drain electrode of metal-oxide-semiconductor M5 connects output end P1, the source electrode ground connection of metal-oxide-semiconductor M5；
The grid of metal-oxide-semiconductor M6 connects input terminal Fi2, and the drain electrode of metal-oxide-semiconductor M6 connects output end P2, the source electrode ground connection of metal-oxide-semiconductor M6.
4. a kind of doubleway output frequency tunable clock signal generator according to claim 1, which is characterized in that delay oscillation
Circuit includes CU1 to CU4 delay cells, clock signal output terminal mouth Fout1, clock signal output terminal mouth Fout2；
The input terminal VI2 of input terminal VI1 connection clock signal output terminals the mouth Fout1, delay cell CU1 of delay cell CU1 connect
Meet clock signal output terminal mouth Fout2；
The upper end of the control terminal VC1 connection capacitances C1 of delay cell CU1, the control terminal VC2 connection capacitances of delay cell CU1 it is upper
Hold C2；
The output end VO2 of input terminal VI1, the CU1 delay cell of the output end VO1 connection delay units CU2 of delay cell CU1 connects
Meet the input terminal VI2 of delay cell CU2；
The control terminal VC2 of the control terminal VC1 of the control terminal VC1 connection delay units CU1 of delay cell CU2, delay cell CU2 connect
Meet the control terminal VC2 of delay cell CU1；
The output end VO2 of the input terminal VI1 of the output end VO1 connection delay units CU3 of delay cell CU2, delay cell CU2 connect
Meet the input terminal VI2 of delay cell CU3；
The control terminal VC2 of the control terminal VC1 of the control terminal VC1 connection delay units CU2 of delay cell CU3, delay cell CU3 connect
Meet the control terminal VC2 of delay cell CU2；
The output end VO2 of the input terminal VI1 of the output end VO1 connection delay units CU4 of delay cell CU3, delay cell CU3 connect
Meet the input terminal VI2 of delay cell CU4；
The control terminal VC2 of the control terminal VC1 of the control terminal VC1 connection delay units CU3 of delay cell CU4, delay cell CU4 connect
Meet the control terminal VC2 of delay cell CU3；
The output end VO2 of output end VO1 connection clock signal output terminals the mouth Fout1, delay cell CU4 of delay cell CU4 connect
Meet clock signal output terminal mouth Fout2.
5. a kind of doubleway output frequency tunable clock signal generator according to claim 1, which is characterized in that delay oscillation
Delay cell CU1 to CU4 internal structures having the same in circuit, delay cell include metal-oxide-semiconductor M15 to M22, input terminal
VI1 and VI2, control terminal VC1 and VC2, output end VO1 and VO2；
The grid of metal-oxide-semiconductor M15 connects control terminal VC1, and the source electrode of metal-oxide-semiconductor M15 connects power vd D, the drain electrode connection of metal-oxide-semiconductor M15
The source electrode of metal-oxide-semiconductor M16；
The grid of metal-oxide-semiconductor M16 connects output end VO1, the drain electrode of the drain electrode connection metal-oxide-semiconductor M17 of metal-oxide-semiconductor M16；
The source electrode of the source electrode connection metal-oxide-semiconductor M15 of metal-oxide-semiconductor M17, the drain electrode of the grid connection metal-oxide-semiconductor M18 of metal-oxide-semiconductor M17, metal-oxide-semiconductor
The drain electrode of the drain electrode connection metal-oxide-semiconductor M20 of M17；
The source electrode of the source electrode connection metal-oxide-semiconductor M17 of metal-oxide-semiconductor M18, the drain electrode of the grid connection metal-oxide-semiconductor M17 of metal-oxide-semiconductor M18, metal-oxide-semiconductor
The drain electrode of the drain electrode connection metal-oxide-semiconductor M19 of M18；
The source electrode of the source electrode connection metal-oxide-semiconductor M16 of metal-oxide-semiconductor M19, the grid of metal-oxide-semiconductor M19 connect output end VO2, the leakage of metal-oxide-semiconductor M19
Pole connects the drain electrode of metal-oxide-semiconductor M21；
The drain electrode of metal-oxide-semiconductor M20 connects defeated end VO1, and the grid of metal-oxide-semiconductor M20 connects input terminal VI1, the source electrode connection of metal-oxide-semiconductor M20
The drain electrode of metal-oxide-semiconductor M22；
The drain electrode of metal-oxide-semiconductor M21 connects output end VO2, and the grid of metal-oxide-semiconductor M21 connects input terminal VI2, and the source electrode of metal-oxide-semiconductor M21 connects
Connect the source electrode of metal-oxide-semiconductor M20；
The grid of metal-oxide-semiconductor M22 connects control terminal VC2, the source electrode ground connection of metal-oxide-semiconductor M22.
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| CN201721777045.5U CN207720101U (en) | 2017-12-11 | 2017-12-11 | A kind of doubleway output frequency tunable clock signal generator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2021142697A1 (en) * | 2020-01-16 | 2021-07-22 | 华为技术有限公司 | Clock signal generator, on-chip clock system, and chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2021142697A1 (en) * | 2020-01-16 | 2021-07-22 | 华为技术有限公司 | Clock signal generator, on-chip clock system, and chip |
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