CN2077132U - Logic analyzer - Google Patents
Logic analyzer Download PDFInfo
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- CN2077132U CN2077132U CN 90217081 CN90217081U CN2077132U CN 2077132 U CN2077132 U CN 2077132U CN 90217081 CN90217081 CN 90217081 CN 90217081 U CN90217081 U CN 90217081U CN 2077132 U CN2077132 U CN 2077132U
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- microcomputer
- oscillograph
- logic analyser
- logic
- instrument
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Abstract
The utility model relates to an instrument for testing and analyzing a digital logic state. The instrument adopts two kinds of terminal interfaces which can be respectively connected with an oscillograph or a microcomputer to singly work or the two kinds of terminal interfaces can be simultaneously connected with the oscillograph to work together. The inner part of the instrument is provided with a cursor generating circuit which can generate a perpendicular cursor line for the waveshape of data which is collected by the oscillograph. The position and the data of the cursor line can be directly read by a display circuit arranged at the front panel of the instrument, and therefore, the data which is collected can be analyzed and judged. The interface of the instrument and a microcomputer is provided with a human-computer conversation type Chinese language operating software. The utility model has the advantages of simple structure, high cost performance, convenient use, etc. The utility model is an ideal instrument for engineers who develop microcomputers, study digital systems, analyze faults, etc.
Description
The utility model is a kind of can be used for various digital intelligent instrument, the logic analyser that various program control, numerical controls, digital circuit and microcomputer design, debug, maintenance and centering, large scale integrated circuit carry out the logic function test.
Logic analyser can be divided into logic state analyzer and logic timing analyzer on function.The logic analyser of producing both at home and abroad has above-mentioned two kinds of functions mostly simultaneously at present.Logic analyser can be divided into again and carries demonstration on the structure, connects oscillograph and microcomputer logic analyser card, and the logic analyser of these three kinds of structures respectively has the following disadvantages:
1. carry the logic analyser complex structure expensive price of demonstration, limited the popularization and application of logic analyser.HP1651A product as the production of U.S. Hewlett-Packard Corporation.Price is 31000 yuans, the EE4511 product of domestic Nanjing telecommunication instrument plant exploitation, and price is minimum also wants 16000 yuan.
2. microcomputer logic analyser card uses inconvenience.Must insert in the microcomputer during work and work together, not drive the microcomputer instrument and can not work with microcomputer.
3. with the ordinary oscilloscope logic analyser of display terminal, can only the video data waveform, can not carry out analysis and judgement to the data of gathering.
The purpose of this utility model is the deficiency at above-mentioned prior art, provide a kind of simple in structure, cheap, both can with the ordinary oscilloscope work that links to each other separately, also can with the microcomputer work that links to each other separately, perhaps with oscillograph, microcomputer link to each other simultaneously work and the hyperchannel logic analyser that on oscillograph, the data that collect is carried out state and timing analysis.
The key problem in technology of realizing the utility model purpose is: 1. have additional cursor and produce circuit in circuit; 2. in logic analyser, be provided with oscillograph, two kinds of interfaces of microcomputer and touch key-press and show luminescence component; (3) with microcomputer interface and be provided with people's one machine dialog mode Chinese function software.
Describe structure of the present utility model in detail below in conjunction with accompanying drawing.
Fig. 1 is a circuit block diagram of the present utility model.
Fig. 2 is the timing display waveform of the utility model on oscillograph.
Fig. 3 is the schematic block circuit diagram of the utility model control cursor forward-reverse.
Fig. 4 is front panel figure of the present utility model.
Fig. 5 is rear panel figure of the present utility model.
Fig. 6 is input cable of the present utility model and input clip picture group.
Fig. 7 is the connection layout of the utility model and microcomputer.
Fig. 8 is a function software of the present utility model structural drawing.
With reference to Fig. 1, threshold voltage produces circuit and is connected with 0.2 key and TTL key. The effect of this two button is the size that threshold voltage is set. If system under test (SUT) is the TTL circuit, can press the TTL key, this moment, threshold voltage was+1.4 volts, if when system under test (SUT) is ECL or DTL circuit, can presses 0.2 volt of key threshold voltage is arranged arbitrarily in-6.4 volts to+6.2 volts scopes with 0.2 volt of step-length. Trigger-delay circuit is connected with 1000,100,10,1 four composite-keys, has trigger word setting and delayed trigger two kinds of functions are set. Cursor line produces that circuit is connected with 16,1, three buttons of U/D. Produce circuit by cursor and be transported to vertical line that is consisted of by small-pulse effect of oscillographic data time waveform increase at Multiple-shower generation circuit, be referred to as cursor line. The block diagram of this cursor line generation circuit as shown in Figure 3. The moving direction of the U/D end control cursor by forward-backward counter, mobile size is controlled by count pulse, and 16 keys come a pulse, and forward-backward counter just increases by 16 or reduce by 16,1 keys and come a pulse, and forward-backward counter increases by 1 or reduce 1. Produce a cursor pulse by digital comparator in cursor position. Several cursor pulses (8 road or 16 tunnel) just are linked to be a clearly cursor line at oscillographic fluorescent screen. The physical location of cursor line and the data mode on the cursor line can directly go out from the display circuit of logic analyser. This display circuit includes the decimal system display of four charactrons compositions and the binary displays that is made up of 8 (or 16) luminous tubes.
Among Fig. 4, (1) is digital the demonstration, is made up of four seven-segment display digital tubes, is used for show gate voltage limit, clock cycle, trigger delay or cursor position. (2) be the luminous tube group, formed by 8 or 16 light emitting diodes, show the data mode value of cursor line on the oscillograph, trigger word is being set The time, show the trigger word that arranges. (3) be that threshold voltage shows indicator lamp, (4) be the clock cycle to show indicator lamp, (5) be the trigger delay indicator lamp, (6) be that cursor position shows indicator lamp, (7) be " show and select " key, this key can change the digital content that shows, and makes (3), (4), (5), (6) four indicator lamps in turn by secretly brightening, (8) be the data input socket, (9) are to trigger polarity switch. Switch is allocated to "+" end, and instrument is in " work " state, luminous tube group this moment (2) demonstration be data mode value on the cursor line, i.e. the bright expression of luminous tube " 1 ", luminous tube secretly represents " 0 ". When switch was allocated to "-" end, instrument was in " trigger word setting " state, and what luminous tube group (2) showed is the trigger word that arranges, i.e. the bright expression of luminous tube " 1 ", and luminous tube secretly represents " 0 ". (10) for threshold voltage arranges key, pressing this key, can to make threshold voltage be+1.4 volts. (11) for threshold voltage arranges key, press this key threshold voltage is increased progressively take 0.2 volt as step-length, excursion is-6.4 volts～+ 6.2 volts, voltage increases to+6.2 volts after, press again 0.2 key, threshold voltage jumps to-6.4 volts, and then progressively increases. (12) be the clock selecting key, press the cycle of this key selectable clocking mode and internal clock, (13) be that the kilobit of trigger delay arranges key (1000 key), when triggering polarity switch in working order the time, press this key the kilobit of trigger delay amount is changed in (0～9) scope. When triggering polarity switch at " trigger word setting " state, this key is that trigger word arranges symbolic key, (14) be that hundred of trigger delay arrange key (100 key), " during duty, pressing hundred variations (0～9) scope in that this key can make the trigger delay amount when triggering polarity switch. When triggering polarity switch at " trigger word setting " state, this key is for triggering the enter key of character " X ". (15) be that ten of trigger delay arrange key (10 key), when triggering polarity switch at " work " state, press ten variations in (0～9) scope that this key can make the trigger delay amount. When triggering polarity switch at " trigger word setting " state, this key is for triggering the enter key of character " 0 ". (16) be that a position of trigger delay arranges key (1 key) when triggering polarity switch at " work " state, press position variation in (0～9) scope that this key can make the trigger delay amount. When triggering polarity switch at " trigger word setting " state, this key is for triggering the enter key of character " 1 ". (17) be cursor line moving direction operating key. (18) (19) are respectively the cursor line shifting bond(s). (20) for gathering start key. (21) be the synchronous output cable head of x axle, with x axle synchronizing cable the output signal of logic analyser delivered to oscillographic external trigger input, realize simultaneous display. (22) be the Y-axis letter Number output cable head is delivered to oscillographic Y-axis input with the Y-axis signal cable with the output of logic analyser, 8 passages or 16 channel datas gathered with the display logic analyzer.
(23) are power switch among Fig. 5, and (24) are fuse box, and (25) are that power input socket, (26), (27) are the voltage-stabilized power supply fin, and (28) are and the microcomputer interface cable socket. Link to each other with microcomputer with the interface board stube cable by the special purpose interface plate, as shown in Figure 7. During connection, special purpose interface plate (29) will insert in the vacant slot of Microcomputer box, as shown in Figure 4. Namely at first open the microcomputer case lid, remove the microcomputer back near a minor flaps of vacant slot with screwdriver, the 20 core ends that then interface board connect cable are drawn in cabinet from here, pick up again the special purpose interface plate with an end of top the 20th core cable block towards the microcomputer back, with the socket on the stube cable head insertion interface board, after inserting firmly, again interface board is slowly inserted vacant slot, cover then the microcomputer case lid, the other end with stube cable links to each other with interface socket (28) on the logic analyser rear board at last. Before life's work, with the A driver of 5 inches system floppy disks insertion microcomputers, 5 inches operation boards are inserted the B drive of microcomputers. The function software of logic analyser is a kind of function software of human-computer dialogue formula, as shown in Figure 8. The user can be equipped with the keyboard input according to the prompting on the CRT, can finish the various logic analytic function.
Triggering mode of the present utility model be provided with trigger former, postpone to trigger and trigger and limit three kinds.The step that is provided with that wherein trigger word and delay trigger is finished by triggering polarity switch and 1000,100,10,1 four buttons, and it is to pass through Q that triggering limits
1And Q
0Two height are flat to limit passage as constraint or select set trigger word.When if the user does not want with the triggering qualification, can be with the Q among Fig. 5
1The input clip meets an indeclinable high level, Q
0The input clip connects an indeclinable low level.
Embodiment of the present utility model has following four kinds:
Example 1. is one 8 passages, and 1K word, 20MHZ connect oscillographic logic analyser.
Example 2. is one 16 passages, and 2K word, 20MHZ connect oscillographic logic analyser.
Example 3. is one 8 passages, the 1K word, and 20MHZ can connect the logic analyser of oscillograph and microcomputer.
Example 4. is one 16 passages, the 2K word, and 20MHZ can connect the logic analyser of oscillograph and microcomputer.
The utlity model has following advantage.
1. be provided with movably cursor line at data waveform, can on the oscillograph screen, judge the data analysis that collects with this cursor line.
2. the physical location of cursor line and the data mode on the cursor line all can directly be read from the display circuit of logic analyser, and be convenient directly perceived, thereby realize independently data mode analysis.
3. output can link to each other with ordinary oscilloscope or IBM/PC and compatible thereof, also can link with oscillograph and microcomputer the while, and is easy to use, cheap (3500 yuan).
4. adopt man-machine conversation formula Chinese function software, easily-learned easily mastered, easy to operate.
Claims (3)
1, a kind of logic analyser includes logic analyser complete machine and display terminal two parts, and this display terminal can or be used microcomputer with oscillograph, it is characterized in that:
A. the logic analyser complete machine is provided with oscillograph and two kinds of interfaces of microcomputer, both can be connected separately with microcomputer with oscillograph respectively and carry out the logic state analysis, can be connected with microcomputer with oscillograph simultaneously again to work together;
B. logic analysis complete machine inside is provided with cursor and produces circuit, makes and produces a cursor line perpendicular to this waveform on the oscillograph data presented waveform;
C. the complete machine panel of logic analyser is provided with digital the demonstration and the luminotron assembly, with display highlighting position and data mode;
D. the input clip group of logic analyser is provided with " Q
1", " Q
0" two flat input clips that limit passage of height, panel is provided with 1000,100,10,1 four compound keys, limits trigger word and postpone to trigger three kinds of triggering forms to finish respectively to trigger;
E. logic analyser complete machine and microcomputer interface are provided with people's one machine dialog mode Chinese function software, carry out state analysis with realization with microcomputer, timing analysis, and state compares, data presentation, storage and printing.
2, logic analyser according to claim 1 is characterized in that the logic analyser complete machine is to be connected with microcomputer with the interface board stube cable by the special purpose interface plate.The special purpose interface plate inserts in the vacant slot of Microcomputer box, and the interface jack on the logic analyser rear panel is inserted in the other end of special purpose interface plate cable.
3, logic analyser according to claim 1 is characterized in that cursor line can pass through U/D, 16 and 1 three keys move left and right on oscillograph.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 90217081 CN2077132U (en) | 1990-07-26 | 1990-07-26 | Logic analyzer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 90217081 CN2077132U (en) | 1990-07-26 | 1990-07-26 | Logic analyzer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2077132U true CN2077132U (en) | 1991-05-15 |
Family
ID=4896135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 90217081 Withdrawn CN2077132U (en) | 1990-07-26 | 1990-07-26 | Logic analyzer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2077132U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100394207C (en) * | 2001-04-30 | 2008-06-11 | 诚信系统公司 | Open-loop for waveform acquisition |
-
1990
- 1990-07-26 CN CN 90217081 patent/CN2077132U/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100394207C (en) * | 2001-04-30 | 2008-06-11 | 诚信系统公司 | Open-loop for waveform acquisition |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |