CN207689805U - A kind of small size array substrate and display panel - Google Patents
A kind of small size array substrate and display panel Download PDFInfo
- Publication number
- CN207689805U CN207689805U CN201820062265.8U CN201820062265U CN207689805U CN 207689805 U CN207689805 U CN 207689805U CN 201820062265 U CN201820062265 U CN 201820062265U CN 207689805 U CN207689805 U CN 207689805U
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- array substrate
- small size
- display panel
- substrate
- binding pin
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Abstract
The utility model discloses a kind of small size array substrate and display panels.The small size array substrate includes underlay substrate and the TFT layer that is arranged on the underlay substrate, from visible area, binding pin is drawn in region to the TFT layer to the periphery and test point, the binding pin and test point are separately positioned on the opposite both ends of the underlay substrate.The small size array substrate can reduce the area of peripheral region in the case where visible area is constant, reduce overall dimensions.
Description
Technical field
The utility model is related to display field more particularly to a kind of small size array substrate and display panels.
Background technology
As industrial liquid crystal module is towards small size, the differentiation trend development of high dot matrix, client is to high dot matrix display surface
The size requirement of plate is higher and higher, in the case where visible area is constant, it is desirable that its size is small better, this just needs reduction to show
The peripheral region of panel.As shown in Figure 1, being provided with binding pin 12 ' and test in the peripheral region 11 ' of existing array substrate
Point 13 ', wherein binding pin 12 ' is used for connecting test device, is used for out for connecting driving IC and wiring board, test point 13 '
Display panel is detected before factory, screens out defective products, existing binding pin 12 ' and test point 13 ' are arranged in array substrate
The same side on, cause the unilateral width of array substrate excessive, and in array substrate with binding pin 12 ' and 13 ' phase of test point
Adjacent both sides also have to extension to adapt to the width of binding pin 12 ' and test point 13 ', lead to the entire periphery of array substrate
The area in region 11 ' is excessive, is unfavorable for the small-sized of display panel.
Utility model content
In order to solve above-mentioned the deficiencies in the prior art, a kind of small size array substrate of the utility model offer and display surface
Plate.The small size array substrate can reduce the area of peripheral region in the case where visible area is constant, reduce overall dimensions.
Technical problem to be solved in the utility model is achieved by the following technical programs：
A kind of small size array substrate, including underlay substrate and the TFT layer being arranged on the underlay substrate, the TFT
From visible area, binding pin and test point are drawn in region to layer to the periphery, and the binding pin and test point are separately positioned on described
On the opposite both ends of underlay substrate.
Further, the underlay substrate includes opposite a pair of of long side and opposite a pair of short edges, the binding pin
It is separately positioned on test point on opposite short side.
A kind of display panel, including above-mentioned small size array substrate and the coloured silk with array substrate opposing seal setting
Ilm substrate is provided with liquid crystal material between the array substrate and color membrane substrates.
Further, driving IC is provided on the binding pin.
Further, the driving IC is connected with wiring board.
Further, it is provided with the first polaroid in one side of the array substrate far from color membrane substrates.
Further, it is provided with the second polaroid in one side of the color membrane substrates far from array substrate.
The utility model has the advantages that：The small size array substrate distinguishes the binding pin and test point
Be arranged on the opposite both ends of the underlay substrate, be not in thus the excessive problem of unilateral width, and with the binding
Pin and the adjacent both sides of test point can inside contract, and to reduce peripheral region, in the case where visible area is constant, reduce whole
Size.
Description of the drawings
Fig. 1 is the schematic diagram of existing array substrate；
Fig. 2 is the schematic diagram of small size array substrate provided by the utility model；
Fig. 3 is the schematic diagram of display panel provided by the utility model.
Specific implementation mode
The utility model is described in detail with reference to the accompanying drawings and examples.
Embodiment one
As shown in Fig. 2, a kind of small size array substrate, including underlay substrate and the TFT that is arranged on the underlay substrate
Layer, from visible area, binding pin 12 and test point 13, the binding pin 12 and survey are drawn in region 11 to the TFT layer to the periphery
Pilot 13 is separately positioned on the opposite both ends of the underlay substrate.
It is opposite that the binding pin 12 is separately positioned on the underlay substrate by the small size array substrate with test point 13
Both ends on, be not in thus the excessive problem of unilateral width, and adjacent with the binding pin 12 and test point 13
Both sides can inside contract, and to reduce peripheral region 11, in the case where visible area is constant, reduce overall dimensions.
Preferably, the underlay substrate includes opposite a pair of of long side and opposite a pair of short edges, the binding pin 12
It is separately positioned on test point 13 on opposite short side.
Embodiment two
A kind of small size array substrate 1 as shown in figure 3, display panel, including described in embodiment one and with the battle array
The color membrane substrates 2 of 1 opposing seal of row substrate setting, liquid crystal material is provided between the array substrate 1 and color membrane substrates 2.
It is provided with driving IC 5, the driving IC 5 on the binding pin 12 and is connected with wiring board 6.
The array substrate 1 is provided with the first polaroid 3 in the one side far from color membrane substrates 2, the color membrane substrates 2 are separate
The second polaroid 4 is provided in the one side of array substrate 1.
The embodiment of the utility model above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
Cannot it therefore be interpreted as the limitation to the utility model patent range, as long as using the form institute of equivalent substitution or equivalent transformation
The technical solution of acquisition, shall fall within the scope of the present invention.
Claims (7)
1. a kind of small size array substrate, including underlay substrate and the TFT layer that is arranged on the underlay substrate, feature exist
In from visible area, binding pin and test point, the binding pin and test point difference are drawn in region to the TFT layer to the periphery
It is arranged on the opposite both ends of the underlay substrate.
2. small size array substrate according to claim 1, which is characterized in that the underlay substrate includes opposite a pair
Long side and opposite a pair of short edges, the binding pin and test point are separately positioned on opposite short side.
3. a kind of display panel, which is characterized in that including small size array substrate as claimed in claim 1 or 2 and with the battle array
The color membrane substrates of row substrate opposing seal setting, liquid crystal material is provided between the array substrate and color membrane substrates.
4. display panel according to claim 3, which is characterized in that be provided with driving IC on the binding pin.
5. display panel according to claim 4, which is characterized in that the driving IC is connected with wiring board.
6. according to any display panel in claim 3-5, which is characterized in that the array substrate is far from color membrane substrates
One side on be provided with the first polaroid.
7. according to any display panel in claim 3-5, which is characterized in that the color membrane substrates are far from array substrate
One side on be provided with the second polaroid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820062265.8U CN207689805U (en) | 2018-01-15 | 2018-01-15 | A kind of small size array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820062265.8U CN207689805U (en) | 2018-01-15 | 2018-01-15 | A kind of small size array substrate and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207689805U true CN207689805U (en) | 2018-08-03 |
Family
ID=62990754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820062265.8U Active CN207689805U (en) | 2018-01-15 | 2018-01-15 | A kind of small size array substrate and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207689805U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113419385A (en) * | 2021-05-31 | 2021-09-21 | 北海惠科光电技术有限公司 | Display panel, preparation method thereof and display device |
-
2018
- 2018-01-15 CN CN201820062265.8U patent/CN207689805U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113419385A (en) * | 2021-05-31 | 2021-09-21 | 北海惠科光电技术有限公司 | Display panel, preparation method thereof and display device |
| CN113419385B (en) * | 2021-05-31 | 2022-09-27 | 北海惠科光电技术有限公司 | Display panel, preparation method thereof and display device |
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