CN207424241U - A kind of Embedded radar signal and data processing device - Google Patents

Abstract

The utility model is related to a kind of Embedded radar signal and data processing device, including FPGA control circuit, signal processing circuit, A/D convertor circuit, first memory, second memory and interface circuit.FPGA control circuit includes FPGA and hard nucleus management circuit, FPGA is connected with hard nucleus management circuit by Avalon buses, FPGA is electrically connected respectively with signal processing circuit and A/D convertor circuit, A/D convertor circuit is electrically connected with external radar system, hard nucleus management circuit is electrically connected respectively with interface circuit, first memory and second memory, interface circuit and upper mechatronics.The Embedded radar signal and data processing device of the utility model, it is combined using embedded FPGA with signal processing circuit, with a variety of Peripheral Interfaces, greatly reduce the difficulty and cost of exploitation, optimize the hardware structure of system, data store and read the ping-pong structure using two memories, greatly reduce the delay of data transmission, produce in enormous quantities convenient for low cost.

Description

A kind of Embedded radar signal and data processing device

Technical field

The utility model is related to technical field of security and protection more particularly to a kind of Embedded radar signal and data processing devices.

Background technology

At present, soul core series radar signal processor has been applied successfully to the necks such as ground, carrier-borne, airborne, spaceborne radar Domain, and based on the hardware structure of multi-DSP coupling plus FPGA control circuit.At miniaturization frequency modulated continuous wave radar signal The characteristics of reason and reality, the coupling of traditional multi-DSP are primarily present following defect：

1st, since the data volume of frequency modulated continuous wave radar is much smaller than traditional pulse radar, monolithic soul core DSP architecture Operational capability can meet the needs of frequency modulated continuous wave radar；

2nd, power consumption is higher, can not adapt to the needs that equipment open air works long hours.

3rd, cost is higher, limits the large-scale promotion application of product；

4th, interface is not abundant enough, and the construction cycle is longer, and development difficulty is larger.

In addition, in the system hardware framework of existing multi-DSP chip coupling, storage and reading use pair for data Same memory is carried out at the same time, and such data delay is larger, causes the storage of data and reading efficiency less efficient.

The content of the invention

Technical problem to be solved in the utility model is in view of the above shortcomings of the prior art, to provide a kind of embedded thunder Up to signal and data processing device, the hardware structure of system is optimized, enriches system interface, and reduce cost, be suitble to Produce in enormous quantities.

The technical solution that the utility model solves above-mentioned technical problem is as follows：A kind of Embedded radar signal and data processing Device, including FPGA control circuit, signal processing circuit, A/D convertor circuit, first memory, second memory and interface electricity Road.

The FPGA control circuit includes FPGA and hard nucleus management circuit, the FPGA and the electrical connection of hard nucleus management circuit, The FPGA is electrically connected respectively with the signal processing circuit and A/D convertor circuit, the A/D convertor circuit and external radar system Electrical connection, the hard nucleus management circuit is electrically connected respectively with the interface circuit, first memory and second memory, described to connect Mouth circuit and upper mechatronics.

The beneficial effects of the utility model are：The Embedded radar signal and data processing device of the utility model, is abandoned The system hardware framework of multi-DSP chip coupling of the prior art, is combined using embedded FPGA with signal processing circuit, With a variety of Peripheral Interfaces, the difficulty and cost of exploitation are greatly reduced, optimizes the hardware structure of system, data store and reading The ping-pong structure using two memories is taken, greatly reduces the delay of data transmission, is produced in enormous quantities convenient for low cost.

Based on the above technical solutions, the utility model can also do following improvement：

Further：The Embedded radar signal and data processing device further includes positioning circuit, the positioning circuit with The hard nucleus management circuit electrical connection.

The advantageous effect of above-mentioned further scheme is：The position of whole device can be obtained in real time by the positioning circuit The location information is sent to host computer by interface circuit convenient for the FPGA, realizes the positioning to whole device by information Tracking.

Further：The positioning circuit uses the Big Dipper GPS dual-mode locating module of model N303.

The advantageous effect of above-mentioned further scheme is：Liang Taowei can be made full use of using Big Dipper GPS dual-mode locating module The strong point and satellite resource of star alignment system, precision and reliability are stronger, can also verify mutually, and clock accuracy is higher, ionization Layer error is relatively low.

Further：The Embedded radar signal and data processing device further includes warning circuit, the warning circuit with The hard nucleus management circuit electrical connection.

The advantageous effect of above-mentioned further scheme is：It can be detected by the warning circuit in the FPGA control circuit When occurring abnormal to the target information of external radar system and alarm, and alert, convenient in time reply being taken to arrange It applies.

Further：The warning circuit include phonetic alarm and/or visual alarm, the phonetic alarm and/or Visual alarm is electrically connected respectively with the hard nucleus management circuit.

Further：The Embedded radar signal and data processing device further includes radio communication circuit, the channel radio Letter circuit is electrically connected with the hard nucleus management circuit, the radio communication circuit and remote terminal wireless connection.

The advantageous effect of above-mentioned further scheme is：The hard nucleus management electricity can be realized by the radio communication circuit Road and remote terminal wireless connection, convenient for remotely receiving the target information that external radar system detects, improve the convenient of monitoring Property and promptness.

Further：The interface circuit include LAN interface, wifi interfaces, USB interface and one kind in RS232 interface or It is a variety of, the LAN interface, wifi interfaces, USB interface and RS232 interface and the upper mechatronics.

The advantageous effect of above-mentioned further scheme is：By set the LAN interface, wifi interfaces, USB interface and RS232 interface can meet the communication mode of different host computer types, enrich interface type, enhance the versatility of whole device, Reduce the difficulty and cost of exploitation.

Further：It is electrically connected between the FPGA control circuit and the signal processing circuit by four link ports of two-way It connects.

The advantageous effect of above-mentioned further scheme is：Signal processing circuit can be greatly improved by four link ports of two-way Data transmission efficiency between FPGA reduces data delay, improves the accuracy of data transmission.

Further：The FPGA control circuit use model 5CSEMA5F31C6N chip, the first memory and Second memory is DDR3 memories.

Further：The signal processing circuit uses the digital signal processing chip of model BWDSP100, and the AD turns Change the AD conversion chip that circuit uses model AD9650BCPZ-25.

Description of the drawings

Fig. 1 is the Embedded radar signal and data processing apparatus structure schematic diagram of one embodiment of the utility model；

Fig. 2 is the Embedded radar signal and data processing apparatus structure schematic diagram of another embodiment of the utility model；

Fig. 3 is the Embedded radar signal and data processing apparatus structure schematic diagram of another embodiment of the utility model；

Fig. 4 is the Embedded radar signal and data processing apparatus structure schematic diagram of another embodiment of the utility model.

Specific embodiment

The principle and feature of the utility model are described below in conjunction with attached drawing, example is served only for explaining this practicality It is new, it is not intended to limit the scope of the utility model.

As shown in Figure 1, a kind of Embedded radar signal and data processing device, including FPGA control circuit, signal processing Circuit, A/D convertor circuit, first memory, second memory and interface circuit.

The FPGA control circuit includes FPGA and hard nucleus management circuit, and the FPGA and hard nucleus management circuit pass through Avalon buses connect, and the FPGA is electrically connected respectively with the signal processing circuit and A/D convertor circuit, the AD conversion electricity Road is electrically connected with external radar system, and the hard nucleus management circuit is deposited respectively with the interface circuit, first memory and second Reservoir is electrically connected, the interface circuit and upper mechatronics.

The Embedded radar signal and data processing device of the utility model, has abandoned multi-DSP core of the prior art The system hardware framework of piece coupling, is combined using embedded FPGA with signal processing circuit, is had a variety of Peripheral Interfaces, is greatly dropped The difficulty and cost of low exploitation, optimize the hardware structure of system, data storage and read the table tennis using two memories Structure greatly reduces the delay of data transmission, produces in enormous quantities convenient for low cost.

In the present embodiment, the FPGA control circuit uses the chip of model 5CSEMA5F31C6N. 5CSEMA5F31C6N is internally embedded double arm processors, and 64KB RAM, operating temperature is 0-85 DEG C, and operating voltage can be 1.8V, 2.5V, 3.0V, 3.3V, maximum operation frequency 800MHz.

As shown in Figure 2, it is preferable that in the above-described embodiments, the Embedded radar signal and data processing device also wraps Positioning circuit is included, the positioning circuit is electrically connected with the hard nucleus management circuit.It can be obtained in real time by the positioning circuit The location information is sent to host computer, realization pair by the location information of whole device convenient for the FPGA by interface circuit The locating and tracking of whole device.

In the present embodiment, the positioning circuit uses the Big Dipper GPS dual-mode locating module of model N303.Using the Big Dipper GPS dual-mode locating module can make full use of the strong point and satellite resource of two sets of global position systems, and precision and reliability are stronger, It can also verify mutually, clock accuracy is higher, and ionospheric error is relatively low.

As shown in Figure 3, it is preferable that in the above-described embodiments, the Embedded radar signal and data processing device also wraps Warning circuit is included, the warning circuit is electrically connected with the hard nucleus management circuit.It can be described by the warning circuit FPGA control circuit detects when the target information of external radar system occurs abnormal and alarm, and alert, just Counter-measure is taken in time.

In the present embodiment, the warning circuit includes phonetic alarm and/or visual alarm, the phonetic alarm And/or visual alarm is electrically connected respectively with the hard nucleus management circuit.

As shown in Figure 4, it is preferable that in the above-described embodiments, the Embedded radar signal and data processing device also wraps Include radio communication circuit, the radio communication circuit is electrically connected with the hard nucleus management circuit, the radio communication circuit with it is remote Journey terminal wireless connects.It can realize that the hard nucleus management circuit wirelessly connects with remote terminal by the radio communication circuit It connects, convenient for remotely receiving the target information that external radar system detects, improves the convenience and promptness of monitoring.

Here, the radio communication circuit uses model Quectel MC20 wireless communication modules.Quectel MC20 There is wireless communication module ultra-small volume, low-power consumption, double card list the advantages such as to treat.MC20 embed abundant procotol (such as TCP, UDP, PPP, FTP, HTTP and SSL*).

In the present embodiment, the interface circuit includes one in LAN interface, wifi interfaces, USB interface and RS232 interface Kind is a variety of, the LAN interface, wifi interfaces, USB interface and RS232 interface and the upper mechatronics.By setting LAN interface, wifi interfaces, USB interface and RS232 interface are stated, the communication mode of different host computer types can be met, it is abundant to connect Mouth type enhances the versatility of whole device, reduces the difficulty and cost of exploitation.

Preferably, in the above-described embodiments, two-way is passed through between the FPGA control circuit and the signal processing circuit Four link port electrical connections.The data that can be greatly improved by four link ports of two-way between signal processing circuit and FPGA pass Defeated efficiency reduces data delay, improves the accuracy of data transmission.

In the present embodiment, the first memory and second memory are DDR3 memories.DDR3 memories have work( Consume the advantages that small, caloric value is small, and working frequency is high, and versatility is good.

In the present embodiment, the signal processing circuit uses the digital signal processing chip of model BWDSP100, described A/D convertor circuit uses the AD conversion chip of model AD9650BCPZ-25.AD9650BCPZ-25AD conversion chips are 16 double Modulus conversion chip, sample rate are up to 25Msps, and operating temperature is -40-85 DEG C.

In real work, shown FPGA reads the data message in the first memory, then described by being sent to Signal processing circuit, the signal processing circuit handle data message, for example Fourier transformation (FFT), moving-target are shown Show the signals such as (MTI), signal accumulation, constant false alarm rate processing (CFAR), Plot coherence, track initiation, target association, tracking filter Processing, and handling result is back to the FPGA control circuit, while the FPGA reads the reality that the positioning circuit obtains When location information, and will the handling result and location information be packaged after the host computer is sent to by the interface circuit, At this point, the second memory carries out the data accumulation of A/D convertor circuit transmission.At the data in the first memory After the completion of reason, the signal processing circuit is waited for, until after the second memory completes data accumulation, it is described FPGA read shown in data in second memory, data message is handled, and as procedure described above by handling result and Location information is sent to the host computer after being packaged, and at the same time, the data that the A/D convertor circuit is sent then are stored in described In first memory, so cycle.

The above is only the preferred embodiment of the present invention, is not intended to limit the utility model, all in this practicality Within new spirit and principle, any modifications, equivalent replacements and improvements are made should be included in the guarantor of the utility model Within the scope of shield.

Claims (10)

1. a kind of Embedded radar signal and data processing device, it is characterised in that:Including FPGA control circuit, signal processing electricity Road, A/D convertor circuit, first memory, second memory and interface circuit；

The FPGA control circuit includes FPGA and hard nucleus management circuit, and the FPGA and hard nucleus management circuit are total by Avalon Line connects, and the FPGA is electrically connected respectively with the signal processing circuit and A/D convertor circuit, the A/D convertor circuit and outside Radar system is electrically connected, and the hard nucleus management circuit is electrically connected respectively with the interface circuit, first memory and second memory It connects, the interface circuit and upper mechatronics.

2. Embedded radar signal and data processing device according to claim 1, it is characterised in that:Further include positioning electricity Road, the positioning circuit are electrically connected with the hard nucleus management circuit.

3. Embedded radar signal and data processing device according to claim 2, it is characterised in that:The positioning circuit Using the Big Dipper GPS dual-mode locating module of model N303.

4. Embedded radar signal and data processing device according to claim 1, it is characterised in that:Further include alarm electricity Road, the warning circuit are electrically connected with the hard nucleus management circuit.

5. Embedded radar signal and data processing device according to claim 4, it is characterised in that:The warning circuit Including phonetic alarm and/or visual alarm, the phonetic alarm and/or visual alarm respectively with the hard nucleus management Circuit is electrically connected.

6. Embedded radar signal and data processing device according to claim 1, it is characterised in that:Further include channel radio Believe circuit, the radio communication circuit is electrically connected with the hard nucleus management circuit, the radio communication circuit and remote terminal without Line connects.

7. Embedded radar signal and data processing device according to claim 1, it is characterised in that：The interface circuit Including the one or more in LAN interface, wifi interfaces, USB interface and RS232 interface, the LAN interface, wifi interfaces, USB interface and RS232 interface and the upper mechatronics.

8. Embedded radar signal and data processing device according to claim 1, it is characterised in that:The FPGA controls It is electrically connected between circuit and the signal processing circuit by four link ports of two-way.

9. according to claim 1-8 any one of them Embedded radar signal and data processing devices, it is characterised in that:It is described FPGA control circuit uses the chip of model 5CSEMA5F31C6N, and the first memory and second memory are DDR3 Memory.

10. according to claim 1-8 any one of them Embedded radar signal and data processing devices, it is characterised in that:Institute The digital signal processing chip that signal processing circuit uses model BWDSP100 is stated, the A/D convertor circuit uses model The AD conversion chip of AD9650BCPZ-25.