CN207399226U - Network interface expanding unit - Google Patents
Network interface expanding unit Download PDFInfo
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- CN207399226U CN207399226U CN201720941859.1U CN201720941859U CN207399226U CN 207399226 U CN207399226 U CN 207399226U CN 201720941859 U CN201720941859 U CN 201720941859U CN 207399226 U CN207399226 U CN 207399226U
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Abstract
The utility model discloses a kind of network interface expanding units.The device includes：AM3354 chips, including at least three pins；88E6176 chips, including first kind pin and the second class pin, wherein, first kind pin is connected respectively with three pins of AM3354 chips, the second class pin and at least two network interface connections；External crystal oscillator is connected with 88E6176 chips；At least two network interfaces, for network interface for being inserted into cable, each network interface connects 88E6176 chips by the second class pin, wherein, 88E6176 chips are used to carry out data transmission between AM3354 chips and at least two network interfaces.By the utility model, achieve the effect that reduce network interface extension cost.
Description
Technical field
The utility model is related to computer realm, in particular to a kind of network interface expanding unit.
Background technology
With the development of industrial network construction, the mistake formed there is an urgent need to realize multifunction instrument, measuring and controlling equipment, SCADA
Intercommunication, interconnection, the monitoring of complete paired data between process control system, ensure that the condition of production is made real time reaction by enterprise, eliminate
Information island and fault-layer-phenomenon.
In order to obtain the production information at scene, many enterprises transmit information by the way of disk or manpower transmission is copied, including
Manual metering, the mode periodically reported.Manually acquisition is not only extremely inconvenient can not also collect live data in real time, it is difficult to
Requirement in terms of meeting current Industry Control industry to producing control and information management, thus it is mutual between each system of realization
Logical, interconnection has been trend of the times.Embedded communication management gateway based on ARM frameworks is industry spot low cost solution
Ideal chose.
AM3354ARM Cortex-A8 microprocessors are designed suitable for industrial automation, provide programmable real-time unit
(PRU) on piece interface, it can be achieved that real-time industrial communication (principal and subordinate) support EtherCAT, Ethernet/IP, The common protocols such as POWERLINK and SERCOS III.The PRU+ of this uniqueness in AM3354 microprocessors
ARM frameworks can reduce system complexity, save the bill of materials (BOM) cost more than 30% without external ASIC or FPGA.This
Outside, AM3354 microprocessors also include other important industrial peripheral hardware (CAN, ADC, USB+PHY and dual-port gigabit ether
Net IEEE1588), not only support fast network connection handles up with rapid data, but also can connect sensor, driver and
Motor controls.This secondary design is exactly that the design of Multi-netmouth is realized on AM3354 platforms.
Mainstream arm processor and board major primary provide one or two 100,000,000 at present or gigabit networking interface is at some
Application scenarios have been unable to meet demand, it is necessary to expand more than two multiple network interfaces.Network interface extension at present has following
Scheme：
1st, extended using PCI-E interface.
2nd, extended using USB interface.
3rd, extended using bus interface.
Existing network interface expansion scheme is applied improper on AM3354 platforms, and AM3354 first does not have PCI-E signals to connect
Mouthful, and USB interface also only has 2 USB2.0, USB2.0 interface bandwidths can be with meet demand, and such as if 100,000,000 interfaces are extended
Gigabit network interface need to be extended, then needs using USB3.0, to be otherwise possible to the bottleneck for causing network bandwidth at usb bus.It is remaining
With bus extension scheme additional increase FPGA or CPLD is needed to realize, cost is higher.
For the problem of network interface extension is of high cost in correlation technique, currently no effective solution has been proposed.
Utility model content
The main purpose of the utility model is that a kind of network interface expanding unit is provided, to solve network in correlation technique
The problem of Interface Expanding is of high cost.
To achieve these goals, one side according to the present utility model provides a kind of network interface expanding unit,
The device includes：AM3354 chips, including at least three pins；88E6176 chips, including first kind pin and the second class pipe
Foot, wherein, the first kind pin is connected respectively with three pins of the AM3354 chips, the second class pin at least
Two network interface connections；External crystal oscillator is connected with the 88E6176 chips；At least two network interfaces, the network interface are used to be inserted into net
Line, each network interface connect the 88E6176 chips by the second class pin, wherein, the 88E6176 chips are used for
Carry out data transmission between the AM3354 chips and at least two network interface.
Further, described device further includes：At least two transformers, the second class pin with the 88E6176 chips
Connection, each transformer and a network interface connection, the quantity of the transformer are identical with the network interface quantity.
Further, the transformer is gigabit GST5009 type transformers.
Further, described device further includes：Indicator light is used to indicate the connection status of the network interface and data transmission shape
State.
Further, the quantity of the indicator light is two times of the network interface quantity.
Further, the first kind pin of the 88E6176 chips includes：PORT5 pins, with the AM3354
One pin connects；Controlling bus pin, including MDC pins and MDIO pins, the second pipe of the MDC pins and the AM3354
Foot connects, and for receiving the input of the clock of data, the MDIO pins are connected with the three-prong of the AM3354, for
The AM3354 carries out data transmission.
Further, the PORT5 pins include：End line group is received, including the first clock sampling signal line, the first data
Transmission signal line and first control signal line；End line group is sent, including second clock sampled signal line, the second data transfer signal
Line and second control signal line.
Further, the first data transmission signal wire and the second data transfer signal line are all 4.
Further, the pattern of the PORT5 pins is RGMII patterns.
Further, PORT5 pins work clock under the RGMII patterns is 125MHz.
The utility model is by AM3354 chips, including at least three pins；88E6176 chips, including first kind pin
With the second class pin, wherein, first kind pin is connected respectively with three pins of AM3354 chips, the second class pin and at least two
A network interface connection；External crystal oscillator is connected with 88E6176 chips；At least two network interfaces, network interface are used to be inserted into cable, each network interface
88E6176 chips are connected by the second class pin, wherein, 88E6176 chips are used in AM3354 chips and at least two nets
Carry out data transmission between mouthful, solve the problems, such as in correlation technique that network interface extension is of high cost, and then reduction net
Network Interface Expanding cost effectiveness.
Description of the drawings
The attached drawing for forming the part of the application is used to provide a further understanding of the present invention, the utility model
Schematic description and description does not form the improper restriction to the utility model for explaining the utility model.In attached drawing
In：
Fig. 1 is the schematic diagram according to the network interface expanding unit of the utility model first embodiment；
Fig. 2 is the schematic diagram according to the network interface expanding unit of the utility model second embodiment；
Fig. 3 is connected according to the RGMII interfaces of the PORT5 and AM3354 of a kind of 88E6176 of the utility model embodiment
Schematic diagram；
Fig. 4 is the Setting pattern schematic diagram according to the network interface signal indicator light of the 88E6176 of the utility model embodiment.
Specific embodiment
It should be noted that in the case where there is no conflict, the feature in embodiment and embodiment in the application can phase
Mutually combination.The utility model will be described in detail below with reference to the accompanying drawings and embodiments.
In order to which those skilled in the art is made to more fully understand application scheme, below in conjunction in the embodiment of the present application
The technical solution in the embodiment of the present application is clearly and completely described in attached drawing, it is clear that described embodiment is only
The embodiment of the application part, instead of all the embodiments.Based on the embodiment in the application, ordinary skill people
Member's all other embodiments obtained without making creative work should all belong to the model of the application protection
It encloses.
It should be noted that term " first " in the description and claims of this application and above-mentioned attached drawing, "
Two " etc. be the object for distinguishing similar, without being used to describe specific order or precedence.It should be appreciated that it so uses
Data can exchange in the appropriate case, so as to embodiments herein described herein.In addition, term " comprising " and " tool
Have " and their any deformation, it is intended that cover non-exclusive include.
The utility model embodiment provides a kind of network interface expanding unit.
Fig. 1 is according to the schematic diagram of the network interface expanding unit of the utility model first embodiment, as shown in Figure 1, should
Device includes consisting of part：
AM3354 chips 10, including at least three pins；
88E6176 chips 20, including first kind pin and the second class pin, wherein, first kind pin and AM3354 chips
Three pins connect respectively, the second class pin and at least two network interface connections；
External crystal oscillator 30, is connected with 88E6176 chips；At least two network interfaces, for network interface for being inserted into cable, each network interface is equal
88E6176 chips are connected by the second class pin, wherein, 88E6176 chips are used in AM3354 chips and at least two network interfaces
Between carry out data transmission.
The utility model is by AM3354 chips, including at least three pins；88E6176 chips, including first kind pin
With the second class pin, wherein, first kind pin is connected respectively with three pins of AM3354 chips, the second class pin and at least two
A network interface connection；External crystal oscillator is connected with 88E6176 chips；At least two network interfaces, network interface are used to be inserted into cable, each network interface
88E6176 chips are connected by the second class pin, wherein, 88E6176 chips are used in AM3354 chips and at least two nets
Carry out data transmission between mouthful, solve the problems, such as in correlation technique that network interface extension is of high cost, and then reduction net
Network Interface Expanding cost effectiveness.
In the utility model embodiment, three pins of AM3354 chips 10 can connect 88E6176 chips respectively
PORT5, MDC and MDIO.The work clock of external crystal oscillator 30 is 25MHz, two in PORT0~PORT4 of 88E6176 chips
Pass through the transformer and network interface connection of identical quantity respectively more than a.Network interface can be 2J45 types.Transformer and network interface
Quantity can all be 4.Optionally, the pattern of PORT5 pins is RGMII patterns.PORT5 pins work under RGMII patterns
Clock is 125MHz.
Optionally, which further includes：At least two transformers are connected, each with the second class pin of 88E6176 chips
Transformer and a network interface connection, the quantity of transformer are identical with network interface quantity.Transformer is gigabit GST5009 type transformers.
88E6176 chips need first to be connected transformer with network interface connection, and therefore, four in PORT0~PORT4 can pass through change respectively
Depressor and four network interface connections.
Optionally, which further includes：Indicator light is used to indicate the connection status and data transmission state of network interface.Instruction
The quantity of lamp is two times of network interface quantity.Network interface connection state and data transmission state can be shown by indicator light.
Optionally, the first kind pin of 88E6176 chips includes：PORT5 pins are connected with the first pin of AM3354；
Controlling bus pin, including MDC pins and MDIO pins, the second pin connection of MDC pins and AM3354, for receiving data
Clock input, the three-prong of MDIO pins and AM3354 connect, for carrying out data transmission with AM3354.
Optionally, PORT5 pins include：End line group is received, including the first clock sampling signal line, first data transmission letter
Number line and first control signal line；End line group is sent, including second clock sampled signal line, the second data transfer signal line and the
Two control signal wires.The RGMII interfaces connection of the PORT5 pins and AM3354 of 88E6176 chips can include receiving end line group
With transmission end line group, respectively send and receive end line group all includes three groups of signal wires respectively.First data transmission signal wire and second
Data transfer signal line is all 4.
The utility model embodiment additionally provides a kind of preferred embodiment, with reference to preferred embodiment to this practicality
New technical solution illustrates.
The defects of for the prior art and the application demand of client, the utility model embodiment, which provides one kind, simply to be had
The AM3354 platforms of effect realize more than two Multi-netmouth designs, and more than two Multi-netmouth designs are realized in AM3354 platforms,
And each with separate MAC address, IP address.
The utility model selects technical grade 88e6176, Link the Street gigabits of Marvell Link Street series
Fast ethernet switch be integrated with the high-performance gigabit non-blocking switching fabric of 4 priority queries of band, high-speed searching engine,
The data packet memory of multiple MGMII gigabit ethernet interfaces and 1Mb.Other advanced features include IEEE 802.1p/IPv4/
Ipv6 traffic classification feature and the VLAN based on port.Reason can be provided to stress low cost, ease for use and the product of flexibility
The exchange configuration thought and function, the chip have 7 port GE interchangers, support 5 integrated PHY, 1GMII, RGMII, 1Serdes
And EEE.
Fig. 2 is according to the schematic diagram of the network interface expanding unit of the utility model second embodiment, which can be with
As the preferred embodiment of above-mentioned first embodiment, as shown in Fig. 2, 88E6176 has 7 port GE interchangers, 5 collection are supported
Into PHY, 1GMII, RGMII, 1Serdes and EEE.This programme selects PORT5 and the CPU AM3354 of 88E6176 to be connected, and expands
4 network interfaces are put on display, the Port5 mouths of 88E6176 can support GMII/RGMII/RMII/MII various modes, and AM3354's is each
MAC supports MII/RMII/RGMII and MDIO interfaces, in order to rationally resources of chip this programme be utilized to select RGMII patterns.
Fig. 3 is connected according to the RGMII interfaces of the PORT5 and AM3354 of a kind of 88E6176 of the utility model embodiment
Schematic diagram, as shown in figure 3, INCLK pins from the TXC pins of AM3354 to 88E6176 send data, TXD [3:0] pin to
IND[3:0] pin sends data, and TX_CTL pins send data to INDV pins；The OUTCLK pins of 88E6176 to
The RXC pins of AM3354 send data, OUTD [3:0] pin is to RXD [3:0] pin sends data, and OUTEN pins are to RX_CTL
Pin sends data, and RGMII data structures meet IEEE ethernet standards, and RGMII is using 4 bit data interfaces, work clock
125MHz, and in rising edge and trailing edge simultaneous transmission data, therefore transmission rate is up to 1000Mbps.Compatible MII simultaneously
The 10/100Mbps working methods of defined support transmission rate：10M/100M/1000Mb/s corresponds to clk signal difference
For： 2.5MHz/25MHz/125MHz.
Fig. 4 is according to the Setting pattern schematic diagram of the network interface signal indicator light of the 88E6176 of the utility model embodiment, such as
Shown in Fig. 4, a kind of matrix lamp interface is used to ensure that each port there are 2 indicator lights.The meaning that each LED0, LED1 are represented
Pass through pin LED_SEL [1：0] configured, the pattern that the present embodiment uses as shown in FIG., connects in interface or there are data
During transmission, interface LED light is bright, and when not having data transmission, indicator light extinguishes.When data transmission is high speed, interface LED
Indicator light is bright, and when not being high speed data transfer, indicator light extinguishes.
10/100/1000BASE-T twisted-pair feeders transmitting-receiving transmission mode is supported in the Port 0-3 ports of 88E6176, and 4 pairs of lines are complete
All use (full duplex), each pair line, which has been superimposed, to be sent and received signal, make each pair line number according to symbol rate be 125Msps, bit rate
250Mbps.So as to reduce attenuation of the cable to signal.Mixed circuit is the core for realizing this transmitted in both directions, it will
Transmitting signal and the coupling of reception signal are transmitted in same a pair of of cable, and it is made not interfere with each other.Chip port is to network interface connection
Transformer Selection gigabit GST5009 cake cores between device.
By the technical solution of the utility model embodiment, pass through more nets of interchanger 88E6176 realization AM3354 platforms
Mouth extension, takes up little area, is low in energy consumption, and data connection is quick, reliable, and circuit design is simple.The equipment that operating system is also provided simultaneously
Driving, tool software etc. meet the various application demands of client.This solution provides high reliability, efficient Multi-netmouth solutions
Certainly scheme is widely used in the industries such as safety monitoring, industry routing.The technical solution of the present embodiment passes through experimental verification, work(
It can reach expected requirement.Network communication can reach the uplink and downlink network speed of 1000Mbps.With good
Performance disclosure satisfy that industrial requirement.
It should also be noted that, term " comprising ", "comprising" or its any other variant are intended to nonexcludability
Comprising so that process, method, commodity or equipment including a series of elements are not only including those elements, but also wrap
Include other elements that are not explicitly listed or further include for this process, method, commodity or equipment it is intrinsic will
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including element
Also there are other identical elements in process, method, commodity or equipment.
It these are only embodiments herein, be not limited to the application.To those skilled in the art,
The application can have various modifications and variations.All any modifications made within spirit herein and principle, equivalent substitution,
Improve etc., it should be included within the scope of claims hereof.
Claims (10)
1. a kind of network interface expanding unit, which is characterized in that including：
AM3354 chips, including at least three pins；
88E6176 chips, including first kind pin and the second class pin, wherein, the first kind pin and the AM3354 cores
Three pins of piece connect respectively, the second class pin and at least two network interface connections；
External crystal oscillator is connected with the 88E6176 chips；
At least two network interfaces, the network interface is for being inserted into cable, and each network interface is by described in the second class pin connection
88E6176 chips, wherein, the 88E6176 chips be used between the AM3354 chips and at least two network interface into
Row data transmission.
2. the apparatus according to claim 1, which is characterized in that described device further includes：
At least two transformers are connected with the second class pin of the 88E6176 chips, and each transformer and a network interface connect
It connects, the quantity of the transformer is identical with the network interface quantity.
3. the apparatus of claim 2, which is characterized in that the transformer is gigabit GST5009 type transformers.
4. the apparatus according to claim 1, which is characterized in that described device further includes：
Indicator light is used to indicate the connection status and data transmission state of the network interface.
5. device according to claim 4, which is characterized in that the quantity of the indicator light is the two of the network interface quantity
Times.
6. the apparatus according to claim 1, which is characterized in that the first kind pin of the 88E6176 chips includes：
PORT5 pins are connected with the first pin of the AM3354；
Controlling bus pin, including MDC pins and MDIO pins, the MDC pins are connected with the second pin of the AM3354,
For receiving the input of the clock of data, the MDIO pins are connected with the three-prong of the AM3354, for it is described
AM3354 carries out data transmission.
7. device according to claim 6, which is characterized in that the PORT5 pins include：
Receive end line group, including the first clock sampling signal line, first data transmission signal wire and first control signal line；
Send end line group, including second clock sampled signal line, the second data transfer signal line and second control signal line.
8. device according to claim 7, which is characterized in that the first data transmission signal wire and second data
Transmission signal line is all 4.
9. device according to claim 6, which is characterized in that the pattern of the PORT5 pins is RGMII patterns.
10. device according to claim 9, which is characterized in that the PORT5 pins work under the RGMII patterns
Clock is 125MHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720941859.1U CN207399226U (en) | 2017-07-31 | 2017-07-31 | Network interface expanding unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720941859.1U CN207399226U (en) | 2017-07-31 | 2017-07-31 | Network interface expanding unit |
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| Publication Number | Publication Date |
|---|---|
| CN207399226U true CN207399226U (en) | 2018-05-22 |
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| CN201720941859.1U Active CN207399226U (en) | 2017-07-31 | 2017-07-31 | Network interface expanding unit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620725A (en) * | 2018-06-20 | 2019-12-27 | 北京东土科技股份有限公司 | Method for expanding out-of-band interface of switching equipment and switching equipment |
| CN110618634A (en) * | 2019-09-27 | 2019-12-27 | 深圳市云慧联科技有限公司 | 485 communication interface expansion device and communication method |
-
2017
- 2017-07-31 CN CN201720941859.1U patent/CN207399226U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620725A (en) * | 2018-06-20 | 2019-12-27 | 北京东土科技股份有限公司 | Method for expanding out-of-band interface of switching equipment and switching equipment |
| CN110618634A (en) * | 2019-09-27 | 2019-12-27 | 深圳市云慧联科技有限公司 | 485 communication interface expansion device and communication method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Network interface expanding unit Effective date of registration: 20190627 Granted publication date: 20180522 Pledgee: Zhongguancun Beijing technology financing Company limited by guarantee Pledgor: Beijing Huadian UTS technology Limited by Share Ltd Registration number: 2019990000624 |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right |