CN207301847U - A kind of discrete power supply - Google Patents
A kind of discrete power supply Download PDFInfo
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- CN207301847U CN207301847U CN201721372749.4U CN201721372749U CN207301847U CN 207301847 U CN207301847 U CN 207301847U CN 201721372749 U CN201721372749 U CN 201721372749U CN 207301847 U CN207301847 U CN 207301847U
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Abstract
The utility model discloses a kind of discrete power supply, including：Multiple input, output ends set according to priority and multiple gating switches；Wherein, multiple input terminals are connected with the output terminal respectively；The high input terminal of priority is connected on the rudimentary circuit between the low input terminal of priority and the output terminal by the gating switch；When providing voltage to the output terminal by multiple input terminals, the gating switch disconnects the rudimentary circuit between the low input terminal of priority and the output terminal；According to technical solution provided by the utility model, it in the case of without using control chip, can realize the prioritizing selection of power supply, save cost.
Description
Technical Field
The utility model belongs to the technical field of the power, specifically speaking relates to a discrete power.
Background
Discrete switching power supplies are used in many applications because voltage conversion is performed by switching.
However, most of the discrete power supplies used at present are all completed by a control chip when selecting the priority circuit, which is high in cost and integration level, and the selected priority circuit is not an optimal circuit sometimes.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a discrete power can realize the circuit selection without control chip.
For solving the technical problem among the prior art, the utility model provides a discrete power, include: a plurality of input terminals, output terminals and a plurality of gate switches arranged according to priority; wherein,
the input ends are respectively connected with the output ends;
the input terminal with high priority is connected to a low-level line between the input terminal with low priority and the output terminal through the gating switch;
when a voltage is supplied to the output terminal through a plurality of the input terminals, the gate switch turns off the low-level line between the input terminal having a low priority and the output terminal.
Optionally, the device further comprises a ground terminal;
the gating switch comprises a voltage division circuit, a first MOS (metal oxide semiconductor) tube and a second MOS tube;
the low-level line is connected with the grounding end through the voltage division circuit;
the first MOS tube is connected with the voltage division circuit, wherein the grid electrode of the first MOS tube is connected with the input end with high priority;
the source electrode of the second MOS tube is connected with the voltage division circuit and the input end with low priority, the drain electrode of the second MOS tube is connected with the output end, and the grid electrode of the second MOS tube is connected with the drain electrode of the first MOS tube and the voltage division circuit;
when voltage is provided to the output end through the input ends, the grid electrode of the first MOS tube and the grid electrode of the second MOS tube are both high level, so that the first MOS tube and the second MOS tube are in a disconnected state.
Optionally, the voltage dividing circuit includes a first resistor, a second resistor, a third resistor, and a fourth resistor;
the first resistor and the second resistor are connected in series, one end of the first resistor is connected with the low-level line, and one end of the second resistor is connected with the grounding terminal;
the third resistor and the fourth resistor are connected in series, one end of the third resistor is connected with the low-level line, and one end of the fourth resistor is connected with the ground terminal;
the source electrode of the first MOS tube is connected with the other end of the first resistor, the drain electrode of the first MOS tube is connected with the other end of the third resistor, and the grid electrode of the first MOS tube is connected with the other end of the fourth resistor;
and the source electrode of the second MOS tube is connected with one end of the third resistor, and the grid electrode of the second MOS tube is connected with the drain electrode of the first MOS tube and the other end of the third resistor.
Optionally, the resistance of the third resistor is greater than the resistance of the fourth resistor.
Optionally, capacitors are disposed between the input terminal and the ground terminal and between the output terminal and the ground terminal.
Optionally, a diode is provided on a line between the input terminal with the higher priority and the gate switch, so that current flows from the input terminal with the higher priority to the gate switch in a single direction.
In addition, optionally, a diode is arranged on a line between the input end and the output end, so that current flows from the input end to the output end in a single direction.
The utility model provides a technical scheme, through setting up gating switch, when a plurality of inputs provide voltage to the output, gating switch disconnectable priority is low the input and the low-level circuit between the output to select the high input of priority to provide voltage for the output. The whole selection process can be realized without controlling through a control chip, the cost is saved, and meanwhile, the accuracy of selecting the optimal circuit is high.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the following briefly introduces the drawings required for the embodiments or the prior art descriptions, and obviously, the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
The accompanying drawings, which are described herein, serve to provide a further understanding of the invention and constitute a part of this specification, and the exemplary embodiments and descriptions thereof are provided for explaining the invention without unduly limiting it.
In the drawings:
fig. 1 is a circuit diagram of a discrete power supply of the present invention;
fig. 2 is a circuit diagram of the gate switch of the present invention.
Description of the reference numerals
10: an input end; 20: an output end;
30: a gating switch; 31: a first resistor; 32: a second resistor; 33: a third resistor; 34: a fourth resistor; 35: a first MOS transistor; 36: a second MOS transistor;
40: and a ground terminal.
Detailed Description
To make the objects, technical solutions and advantages of the present invention clearer, the drawings of the present invention are combined to clearly and completely describe the technical solutions of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In some of the flows described in the specification, claims, and above-described figures of the present invention, a number of operations are included that occur in a particular order, and may be performed out of order or in parallel as they occur herein. The sequence numbers of the operations, e.g., 101, 102, etc., are used merely to distinguish between the various operations, and do not represent any order of execution per se. Additionally, the flows may include more or fewer operations, and the operations may be performed sequentially or in parallel. It should be noted that, the descriptions of "first", "second", etc. in this document are used for distinguishing different messages, devices, modules, etc., and do not represent a sequential order, nor limit the types of "first" and "second" to be different.
The inventor is realizing the utility model discloses an in-process discovery, at present, the discrete power that uses all is accomplished through control chip when selecting the circuit, and is with high costs, and the integrated level is high, and the priority circuit of selecting sometimes is not the optimal circuit moreover.
Therefore, for solving the defect among the prior art, the utility model provides a discrete power does not need control chip to realize the circuit selection promptly.
The following will explain in detail the embodiments of the present invention with reference to the accompanying drawings and examples, so as to fully understand and implement how to apply the technical means to solve the technical problems and achieve the technical effects of the present invention, and the structure of the present invention will be further explained with reference to the drawings.
Fig. 1 is a circuit diagram of a discrete power supply of the present invention, as shown in fig. 1.
The utility model provides a discrete power supply, include: a plurality of input terminals 10, output terminals 20, and a plurality of gate switches 30, which are set according to priority.
Wherein the plurality of input terminals 10 are respectively connected to the output terminals 20.
The input terminal 10 with high priority is connected to a low-level line between the input terminal 10 with low priority and the output terminal 20 through the gate switch 30.
When a voltage is supplied to the output terminal 20 through the plurality of input terminals 10, the gate switch 30 disconnects a low-level line between the input terminal 10 and the output terminal 20 having a low priority.
For example, referring to fig. 1, VCC1, VCC2, and VCC3 are all input terminals 10, and when VCC1 and VCC2 coexist, that is, VCC1 and VCC2 simultaneously supply voltage to output terminal 20(VOUT), VCC1 supplies power to gate switch 30 through D2, VCC2 supplies power to gate switch 30, and gate switch 30 disconnects the line between VCC2 and output terminal 20, so that the voltage at output terminal 20 is supplied by VCC1, and VCC1 has higher priority than VCC 2.
When VCC2 coexists with VCC3, VCC2 supplies power to the gate switch 30 through DN1, VCC3 supplies power to the gate switch 30, the gate switch 30 disconnects the line between VCC3 and the output terminal 20, so that the voltage at the output terminal 20 is supplied by VCC2, and VCC2 has higher priority than VCC 3;
when VCC1, VCC2, and VCC3 coexist, VCC1 supplies power to the gate switches 30 corresponding to VCC2 and VCC3 through D2 and DN1, VCC2 and VCC3 supply power to the corresponding gate switches 30 at the same time, and the gate switches 30 disconnect the lines between VCC3 and VCC2 and the output terminal 20, so that the voltage at the output terminal 20 is supplied by VCC 1.
Thus, the priority order is VCC1> VCC2> VCC 3.
The utility model provides a technical scheme, through setting up gating switch 30, when a plurality of inputs 10 provide voltage to output 20, gating switch 30 disconnectable priority is low-level circuit between input 10 and the output 20 to select the high input 10 of priority to provide voltage for output 20. The whole selection process can be realized without controlling through a control chip, the cost is saved, and meanwhile, the accuracy of selecting the optimal circuit is high.
The following provides a further detailed description of the discrete power supply provided by the embodiment of the present invention.
Referring to fig. 2, the discrete power supply further includes a ground terminal 40. The gate switch 30 includes a voltage divider circuit, a first MOS transistor 35 and a second MOS transistor 36. Wherein, the MOS pipe is Metal Oxide Semiconductor, a voltage control device, and it has three motor: source, drain and gate, the drain-source current being controllable by the gate voltage.
The low-level line is connected to the ground terminal 40 through a voltage dividing circuit. The first MOS transistor 35 is connected to the voltage divider circuit, wherein a gate of the first MOS transistor 35 is connected to the input terminal 10 with a high priority. The source of the second MOS transistor 36 is connected to the voltage divider circuit and the input terminal 10 with the lower priority, the drain is connected to the output terminal 20, and the gate is connected to the drain of the first MOS transistor 35 and the voltage divider circuit.
When a voltage is provided to the output terminal 20 through the plurality of input terminals 10, the gates of the first MOS transistor 35 and the second MOS transistor 36 are both at a high level, so that the first MOS transistor 35 and the second MOS transistor 36 are in an off state.
For example, referring to fig. 1 and 2, when VCC1 coexists with VCC2, VCC1 outputs a voltage to the gate (node a) of the first MOS transistor 35 (Q1 in the figure) through D2, the gate of the first MOS transistor 35 is at a high level, so the first MOS transistor 35 is in an off state, VCC2 supplies power to the second MOS transistor 36 (Q2 in the figure), the gate (node B) of the second MOS transistor 36 is at the same level as the source, or the gate of the second MOS transistor 36 is at a high level, so the second MOS transistor 36 is in an off state, so the second MOS transistor 36 disconnects the line between VCC2 and the output terminal 20, and the voltage at the output terminal 20 is provided by VCC 1.
When VCC2 coexists with VCC3, the voltage at output terminal 20 is provided by VCC2 for the same reasons as described above.
When VCC1, VCC2, and VCC3 coexist, the levels of node a, node B, node C, and node D are all high, so that the gate switch 30 can disconnect the lines between VCC2 and VCC3 and the output terminal 20, and the voltage at the output terminal 20 is provided by VCC 1.
When only VCC2 exists, the gate (node a) of the first MOS transistor 35 (Q1 in the figure) is at low level, close to 0V, the first MOS transistor 35 is turned on, the gate (node B) of the second MOS transistor 36 (Q2 in the figure) is at low level, close to 0V, the second MOS transistor 36 is turned on, and VOUT is provided by VCC 2.
When only VCC3 exists, the gate (node C) of the first MOS transistor 35 (Q3 in the figure) is at low level, close to 0V, the first MOS transistor 35 is turned on, the gate (node D) of the second MOS transistor 36 (Q4 in the figure) is at low level, close to 0V, the second MOS transistor 36 is turned on, and VOUT is provided by VCC 3.
When VCC1 is present, VOUT is provided by VCC1, regardless of whether VCC2, VCC3 are present.
With reference to fig. 2, in the embodiment of the present invention, the voltage dividing circuit includes a first resistor 31, a second resistor 32, a third resistor 33, and a fourth resistor 34.
The first resistor 31 and the second resistor 32 are connected in series, one end of the first resistor 31 is connected to the low-level line, and one end of the second resistor 32 is connected to the ground terminal 40.
The third resistor 33 and the fourth resistor 34 are connected in series, one end of the third resistor 33 is connected to the low-level line, and one end of the fourth resistor 34 is connected to the ground terminal 40.
The source of the first MOS transistor 35 is connected to the other end of the first resistor 31, the drain thereof is connected to the other end of the third resistor 33, and the gate thereof is connected to the other end of the fourth resistor 34.
The source of the second MOS transistor 36 is connected to one end of the third resistor 33, and the gate is connected to the drain of the first MOS transistor 35 and the other end of the third resistor 33.
The voltage divider circuit divides the voltage of the first MOS transistor 35 and the second MOS transistor 36, and prevents the output terminal 20 having a low priority from supplying the voltage to the output terminal 20 when the output terminal 20 having a high priority is present (the voltage is supplied to the output terminal 20).
For example, without the voltage divider circuit, VCC1 and VCC2 exist at the same time, and if the voltage of VCC2 is greater than the voltage of VCC1, it may happen that the source voltage of the first MOS transistor 35 and the second MOS transistor 36 is higher than the gate voltage, and the first MOS transistor 35 and the second MOS transistor 36 are turned on at the same time, so that the priority of VCC1 is higher than that of VCC2, but VCC1 and VCC2 simultaneously provide the voltage to the output terminal 20. Therefore, such a situation can be avoided by providing the voltage dividing circuit.
In order to more accurately select the priority circuit, the resistance of the third resistor 33 in the voltage dividing circuit is larger than that of the fourth resistor 34. This makes it possible to make the first MOS transistor 35 and the second MOS transistor 36 conduct simultaneously when the input terminal 10 with low priority is present and the input terminal 10 with high priority is absent, so that the input terminal 10 with low priority provides the voltage for the output terminal 20. When the input terminals 10 with high priority and low priority exist at the same time, the first MOS transistor 35 and the second MOS transistor 36 are turned off at the same time, so that the input terminal 10 with high priority supplies voltage to the output terminal 20.
For example, when VCC2 is present and VCC1 is absent, Q1 gate level is near 0V, Q1 is on, Q2 gate level is near 0V, Q2 is on, VCC2 provides voltage for VOUT. When VCC1 and VCC2 coexist, the gate of Q1 is high, Q1 is off, the gate of Q2 is high, and Q2 is off, so that VCC1 has higher priority than VCC2, and VCC1 provides voltage for VOUT.
With reference to fig. 1, in order to prevent the voltage of the input terminal 10 from changing suddenly, capacitors are disposed between the input terminal 10 and the ground terminal 40 and between the output terminal 20 and the ground terminal 40. In fig. 1, C1, C2, C3, C4, C5, C6, C7, and C8 are all capacitors.
In order to prevent the current from reversely flowing to the input terminal 10 with low priority through the gate switch 30 when the input terminal 10 with high priority supplies voltage to the output terminal 20, therefore, in the embodiment of the present invention, a diode is provided on the line between the input terminal 10 with high priority and the gate switch 30, so that the current flows from the input terminal 10 with high priority to the gate switch 30 in one direction.
Meanwhile, when providing voltage for the output terminal 20 for preventing the input terminal 10 with high priority, the current reversely flows to the input terminal 10 with low priority, therefore, in the embodiment of the present invention, the diode is provided on the line between the input terminal 10 and the output terminal 20, so that the current flows from the input terminal 10 to the output terminal 20 in one-way.
To sum up, the utility model provides a technical scheme, through setting up gating switch, when a plurality of inputs provide voltage to the output, gating switch disconnectable priority is low the low-level circuit between input and the output to select the high input of priority to provide voltage for the output. The whole selection process can be realized without controlling through a control chip, the cost is saved, and meanwhile, the accuracy of selecting the optimal circuit is high.
It should be noted that, although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention should not be construed as limited to the scope of the present invention. Various modifications and changes may be made by those skilled in the art without inventive work within the scope of the present invention as described in the claims.
The examples of the present invention are intended to illustrate the technical features of the present invention in a concise manner, so that a person skilled in the art can understand the technical features of the present invention directly without undue restriction.
The above-described apparatus embodiments are merely illustrative, wherein the units described as separate components may or may not be physically separate. One of ordinary skill in the art can understand and implement it without inventive effort.
The foregoing description shows and describes several preferred embodiments of the present invention, but as aforementioned, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the application as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. But that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention, which is to be limited only by the claims appended hereto.
Claims (7)
1. A discrete power supply, comprising: a plurality of input terminals, output terminals and a plurality of gate switches arranged according to priority; wherein,
the input ends are respectively connected with the output ends;
the input terminal with high priority is connected to a low-level line between the input terminal with low priority and the output terminal through the gating switch;
when a voltage is supplied to the output terminal through a plurality of the input terminals, the gate switch turns off the low-level line between the input terminal having a low priority and the output terminal.
2. The discrete power supply of claim 1, further comprising a ground terminal;
the gating switch comprises a voltage division circuit, a first MOS (metal oxide semiconductor) tube and a second MOS tube;
the low-level line is connected with the grounding end through the voltage division circuit;
the first MOS tube is connected with the voltage division circuit, wherein the grid electrode of the first MOS tube is connected with the input end with high priority;
the source electrode of the second MOS tube is connected with the voltage division circuit and the input end with low priority, the drain electrode of the second MOS tube is connected with the output end, and the grid electrode of the second MOS tube is connected with the drain electrode of the first MOS tube and the voltage division circuit;
when voltage is provided to the output end through the input ends, the grid electrode of the first MOS tube and the grid electrode of the second MOS tube are both high level, so that the first MOS tube and the second MOS tube are in a disconnected state.
3. The discrete power supply of claim 2, wherein the voltage divider circuit comprises a first resistor, a second resistor, a third resistor, and a fourth resistor;
the first resistor and the second resistor are connected in series, one end of the first resistor is connected with the low-level line, and one end of the second resistor is connected with the grounding terminal;
the third resistor and the fourth resistor are connected in series, one end of the third resistor is connected with the low-level line, and one end of the fourth resistor is connected with the ground terminal;
the source electrode of the first MOS tube is connected with the other end of the first resistor, the drain electrode of the first MOS tube is connected with the other end of the third resistor, and the grid electrode of the first MOS tube is connected with the other end of the fourth resistor;
and the source electrode of the second MOS tube is connected with one end of the third resistor, and the grid electrode of the second MOS tube is connected with the drain electrode of the first MOS tube and the other end of the third resistor.
4. The discrete power supply of claim 3, wherein the third resistor has a resistance value greater than a resistance value of the fourth resistor.
5. The discrete power supply of claim 2, wherein a capacitor is disposed between the input terminal and the ground terminal and between the output terminal and the ground terminal.
6. A discrete power supply as claimed in any one of claims 1 to 5, wherein a diode is provided in the line between the input of high priority and the gate switch, so that current flows unidirectionally from the input of high priority to the gate switch.
7. A discrete power supply as claimed in any one of claims 1 to 5, wherein a diode is provided in line between the input and output terminals so that current flows unidirectionally from the input terminal to the output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721372749.4U CN207301847U (en) | 2017-10-16 | 2017-10-16 | A kind of discrete power supply |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201721372749.4U CN207301847U (en) | 2017-10-16 | 2017-10-16 | A kind of discrete power supply |
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| CN207301847U true CN207301847U (en) | 2018-05-01 |
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| CN201721372749.4U Active CN207301847U (en) | 2017-10-16 | 2017-10-16 | A kind of discrete power supply |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113612214A (en) * | 2021-06-25 | 2021-11-05 | 苏州浪潮智能科技有限公司 | Device and method for safety compatibility of various power supply modules |
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2017
- 2017-10-16 CN CN201721372749.4U patent/CN207301847U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113612214A (en) * | 2021-06-25 | 2021-11-05 | 苏州浪潮智能科技有限公司 | Device and method for safety compatibility of various power supply modules |
| CN113612214B (en) * | 2021-06-25 | 2023-07-18 | 苏州浪潮智能科技有限公司 | Device and method for safely and compatibly realizing multiple power supply modules |
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