CN207281885U - The mainboard and finance device of a kind of finance device - Google Patents

The mainboard and finance device of a kind of finance device Download PDF

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Publication number
CN207281885U
CN207281885U CN201721299332.XU CN201721299332U CN207281885U CN 207281885 U CN207281885 U CN 207281885U CN 201721299332 U CN201721299332 U CN 201721299332U CN 207281885 U CN207281885 U CN 207281885U
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networks
vcc
chips
core board
voltage
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Expired - Fee Related
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CN201721299332.XU
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Chinese (zh)
Inventor
杨鹏
桑波
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Shenzhen Yihua Computer Co Ltd
Shenzhen Yihua Time Technology Co Ltd
Shenzhen Yihua Financial Intelligent Research Institute
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Shenzhen Yihua Computer Co Ltd
Shenzhen Yihua Time Technology Co Ltd
Shenzhen Yihua Financial Intelligent Research Institute
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Application filed by Shenzhen Yihua Computer Co Ltd, Shenzhen Yihua Time Technology Co Ltd, Shenzhen Yihua Financial Intelligent Research Institute filed Critical Shenzhen Yihua Computer Co Ltd
Priority to CN201721299332.XU priority Critical patent/CN207281885U/en
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Publication of CN207281885U publication Critical patent/CN207281885U/en
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Abstract

The utility model discloses the mainboard and finance device of a kind of finance device,Mainboard is divided into master control core board and bottom plate,Core board includes the memory of storing control program,The multiple communication interfaces and multiple default I/O interfaces that master control core board is equipped with by it,Detachable connector is connected with bottom plate,Realize and easily dismantled between master control core board and bottom plate,Replace,When the mainboard of finance device needs to be updated the replacement,Only need the circuit of redesign bottom plate,And the matched control program of bottom plate in the memory of renewal or increase master control core board with redesign,And without being redesigned to whole mainboard,Greatly reduce the workload of hardware design and the construction cycle of finance device,The integrated level of the master control core board is high at the same time,When carrying out the redesign of bottom plate,The required component number of back-plane design is less,So that mainboard is smaller on the whole,Be conducive to the micromation of mainboard.

Description

The mainboard and finance device of a kind of finance device
Technical field
The utility model embodiment is related to technical field of financial equipment, more particularly to the mainboard and gold of a kind of finance device Melt equipment.
Background technology
ATM ATM (Automatic Teller Machine) machines and automatic teller machine CDM (Cash Dispenser Machine) when the motherboard design of finance device, its core board generally does main control chip with microcontroller, single Its hardware resource of piece machine is few, and processor speed is low, when causing the finance device often to run into update, is required for its mainboard weight New design, and the hardware circuit of mainboard is complicated, if renewal of the equipment every time is required for redesigning, construction cycle length is designed to This height.
Utility model content
The utility model provides a kind of control method of finance device, mainboard and finance device, to solve finance device The problem of mainboard construction cycle is grown, and design cost is high.
In a first aspect, the utility model embodiment provides a kind of mainboard of finance device, including：Master control core board and bottom Plate；
The Double Data Rate synchronous dynamic random that the master control core board includes main control chip, is electrically connected with the main control chip Memory, the memory being electrically connected with the main control chip, the power supply modular converter for master control core board power supply, Duo Getong Communication interface and multiple default I/O interfaces；
The multiple communication interface and multiple default I/O interfaces are electrically connected by detachable connector with the bottom plate；
The memory is used to store the control program that master control core board sends control instruction, and the bottom plate is used to receive institute After the control instruction for stating the transmission of master control core board, the control operation to finance device is performed.
Second aspect, the utility model embodiment additionally provide a kind of finance device, and the finance device includes above-mentioned Mainboard.
The third aspect, the utility model embodiment additionally provide a kind of control method of finance device, including：
Receive the operation information of user；
Control instruction is generated based on the operation information, and sends the control instruction to the bottom plate of finance device, it is described Bottom plate is used to generate corresponding execute instruction according to the control instruction, and is performed according to the execute instruction and the finance is set Standby control operation.
The mainboard for the finance device that the utility model embodiment provides, it is divided into master control core board and bottom plate, core board bag The memory of storing control program is included, the multiple communication interfaces and multiple default I/O that master control core board is equipped with by it connect Mouth, detachable connector and bottom plate connect, and realize and easily dismantle, replace between master control core board and bottom plate, when finance is set When standby mainboard needs to be updated the replacement, it is only necessary to redesign the circuit of bottom plate, and renewal or increase master control core board Memory in the matched control program of bottom plate with redesign, and without being redesigned to whole mainboard, drop significantly The low workload of hardware design and the construction cycle of finance device, while the integrated level of the master control core board is high, is carrying out During the redesign of bottom plate, the required component number of back-plane design is less so that mainboard is smaller on the whole, is conducive to The micromation of mainboard.
Further, the master control core board of the utility model embodiment includes multiple default I/O interfaces, have it is higher can Autgmentability and flexibility, are adapted to the changeable design requirement of designer.
Brief description of the drawings
Fig. 1 is a kind of structure diagram of the mainboard for finance device that the utility model embodiment one provides；
Fig. 2 is a kind of structure diagram of power supply module of the utility model embodiment；
Fig. 3 is a kind of electrifying timing sequence figure of the utility model embodiment；
Fig. 4 is a kind of step flow chart of the control method of finance device of the utility model embodiment two.
Embodiment
The utility model is described in further detail with reference to the accompanying drawings and examples.It is understood that herein Described specific embodiment is used only for explaining the utility model, rather than the restriction to the utility model.Further need exist for It is bright, for the ease of description, part relevant with the utility model rather than entire infrastructure are illustrate only in attached drawing.
Embodiment one
Fig. 1 is a kind of structure diagram of the mainboard for finance device that the utility model embodiment one provides, which has Body includes master control core board 2 and bottom plate 3.
Specifically, master control core board 2 can include main control chip 4, with main control chip 4 be electrically connected Double Data Rate it is synchronous move State random access memory DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory the memory 6 that) 5, is electrically connected with main control chip 4, the power supply modular converter 7 powered for master control core board 2, multiple communications Interface 8 and multiple default I/O interfaces 9；
Wherein, multiple communication interfaces 8 and multiple default I/O interfaces 9 are electrically connected by detachable connector 10 and bottom plate 3 Connect；
Memory 6 is used to store the control program that master control core board 2 sends control instruction, and bottom plate 3 is used to receive the master After controlling the control instruction that core board is sent, the control operation to finance device is performed.
The mainboard for the finance device that the utility model embodiment provides, it is divided into master control core board and bottom plate, core board bag The memory of storing control program is included, the multiple communication interfaces and multiple default I/O that master control core board is equipped with by it connect Mouth, detachable connector and bottom plate connect, and realize and easily dismantle, replace between master control core board and bottom plate, when finance is set When standby mainboard needs to be updated the replacement, it is only necessary to redesign the circuit of bottom plate, and renewal or increase master control core board Memory in the matched control program of bottom plate with redesign, and without being redesigned to whole mainboard, drop significantly The low workload of hardware design and the construction cycle of finance device, while the integrated level of the master control core board is high, is carrying out During the redesign of bottom plate, the required component number of back-plane design is less so that mainboard is smaller on the whole, is conducive to The micromation of mainboard.
Further, the master control core board of the utility model embodiment includes multiple default I/O interfaces, have it is higher can Autgmentability and flexibility, are adapted to the changeable design requirement of designer.
Further, if either maintenance section master control core board device is bad or bottom plate is bad in the debugging of mainboard, it is not necessary to Whole mainboard is all scrapped, it is only necessary to replaces corresponding master control core board or bottom plate.
Specifically, as a kind of example, main control chip 4 can select match Sentos Xilinx XC7Z020-2CLG484I, DDR SDRAM can select the DDR3 of two 16 512MB, and memory 5 can be selected according to the selection of those skilled in the art Patch FLASH memory chip M25P128-VMF6P, patch EEROM storage chip AT24C64D-SSHM-T and MRAM ferroelectricities are deposited All kinds of storage chips such as reservoir.
Wherein, multiple communication interfaces can select RS232 communication interfaces, Ethernet network interfaces, iic bus interface, JTAG At least one in debugging interface, to ensure the communication process between master control core board and bottom plate, multiple default I/O interfaces are then It is, when the hardware circuit of bottom plate changes, and the control program correspondence in memory changes, to transmit corresponding control Make the interface of instruction.
With reference to Fig. 1, detachable connector 10 can select BTB (Board to Board, plate is to plate) connector, in master control The Part I of connector 10 is the male connector 10A of BTB connectors on core board, and the another part of connector 10 is on bottom plate The female seat 10B of BTB connectors, male connector and female seat are worked in coordination connection.
With reference to Fig. 1, in a kind of preferred embodiment of the utility model, bottom plate 3 can include being used to detect the finance The sensor 11 and electric machine controller 12 of the working status of equipment.
Wherein, electric machine controller 12 is used to perform the control operation to finance device, is performing the control to finance device During operation, sensor 11 generates feedback information corresponding with control instruction, and Real-time Feedback is carried out to the working status of finance device, The bottom plate is additionally operable to send the feedback information to the master control core board, so that bottom plate can be being performed to finance While the control operation of equipment, feedback information corresponding with control instruction can also be generated, and by the feedback information send to Master control core board, extends the function of bottom plate.
With reference to Fig. 1, in a kind of preferred embodiment of the utility model, master control core board 2 can also include：Power Supply Monitoring Circuit 13 is protected, Power Supply Monitoring protection circuit 13 is electrically connected with main control chip 4, is also electrically connected with power supply modular converter 7, the power supply Monitoring protection circuit 13 persistently monitors the working status of power supply module 7 when finance device works, can be to avoid power supply modulus of conversion The generation of equipment burnout phenomenon caused by short circuit that block is likely to occur, overcurrent etc., greatly improves the safety of finance device operation Property.
With reference to Fig. 1, in a kind of preferred embodiment of the utility model, master control core board 2 can also include encryption chip 14, encryption chip 14 is electrically connected with main control chip 4, for the first preset data to be encrypted, improves the safety of communication process Property.
Specifically, encryption chip can select the core of the commercial cipher algorithm of national commercial cipher management office issue Piece, is electrically connected by SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) bus with main control chip 4, the One preset data can be then the critical datas such as the pre-set key algorithm of those skilled in the art, code and user cipher.
With reference to Fig. 1, in a kind of preferred embodiment of the utility model, master control core board 2 can also connect including USB-FHY Mouthful chip 15, USB-FHY interface chips 15 are electrically connected with main control chip 4 so that master control core board can compatibility USB interface, carry The autgmentability of high finance device.
In a kind of preferred embodiment of the utility model, needed to adapt to miscellaneous power supply in master control core board Ask, a kind of structure diagram of power supply module of the utility model embodiment with reference to shown in Fig. 2, power supply modular converter 7 can wrap Include DC-DC TPS54531 chips, LDO TPS7A4501 chips, LDO TPS73512 chips, the first DC-DC TPS62130 cores Piece, the 2nd DC-DC TPS62130 chips, the 3rd DC-DC TPS62130 chips, the 4th DC-DC TPS62130 chips, LDO REF3012 chips, LDO TPS51200 chips.
Wherein, 12V voltage of the DC-DC TPS54531 chips by the source voltage conversion of 24V into VCC_12V0 networks, it is described 5V voltage of the LDO TPS7A4501 chips by the 12V voltage conversions of VCC_12V0 networks into VCC_SOC_5V0 networks, the LDO 1.2V voltage of the TPS73512 chips by the 5V voltage conversions of VCC_SOC_5V0 networks into VCC_SOC_1V2 networks, described first 1.0V voltage of the DC-DC TPS62130 chips by the 12V voltage conversions of VCC_12V0 networks into VCC_SOC_1V0 networks, it is described 1.8V voltage of the 2nd DC-DC TPS62130 chips by the 12V voltage conversions of VCC_12V0 networks into VCC_SOC_1V8 networks, 1.5V of the 3rd DC-DC TPS62130 chips by the 12V voltage conversions of VCC_12V0 networks into VCC_SOC_1V5 networks Voltage, the 4th DC-DC TPS62130 chips are by the 12V voltage conversions of VCC_12V0 networks into VCC_SOC_3V3 networks 3.3V voltages, the LDO REF3012 chips are by the 3.3V voltage conversions of VCC_SOC_3V3 networks into REF_XADC_1V25 nets The 1.25V voltages of network, the LDO TPS51200 chips are by the 3.3V voltage conversions of VCC_SOC_3V3 networks into VREF_PS_ The reference voltage of DDR3 networks and the 0.75V voltages of VTTVREF_PS_DDR3_0V75 networks.
Wherein, master control core board include " VCC_12V0 networks, VCC_SOC_5V0 networks, VCC_SOC_1V0 networks, VCC_SOC_1V8 networks, VCC_SOC_1V5 networks, VCC_SOC_1V2 networks, VCC_SOC_3V3 networks, REF_XADC_1V25 These networks of network, VREF_PS_DDR3 networks, VTTVREF_PS_DDR3_0V75 networks " obtain after voltage conversion chip Required operating voltage, completes the power demands of master control core board.
It should be noted that the power supply of master control core board there are timing requirements, on the basis of above-mentioned supply network, make For a kind of example, a kind of electrifying timing sequence figure of the utility model embodiment with reference to shown in Fig. 3, power supply modular converter 7 was powered Journey can be as follows：
1st, master control core board 24V voltages after the power is turned on, can turn 24V the enabled pin of the DC-DC TPS54531 chips of 12V Voltage high, makes chip start to work, and obtains 12V voltages.
2nd, after 12V voltages are powered, the LDO TPS7A4501 chips for directly turning 5V by 12V obtain VCC_SOC_5V0 networks Voltage (voltage of 5V).
3rd, the 5V voltages of VCC_SOC_5V0 networks after the power is turned on, can allow 12V to turn the first DC-DC TPS62130 chip works of 1V Make, obtain the voltage of VCC_SOC_1V0 networks.
4th, the 1V voltages of VCC_SOC_1V0 networks after the power is turned on, can allow 12V to turn the 2nd DC-DC TPS62130 chips of 1.8V Work, obtains the voltage of VCC_SOC_1V8 networks.
5th, the 1.8V voltages of VCC_SOC_1V8 networks after the power is turned on, can allow 12V to turn the 3rd DC-DC TPS62130 cores of 1.5V Piece works, and obtains the voltage of VCC_SOC_1V5 networks.
6th, the 1.5V voltages of VCC_SOC_1V5 networks after the power is turned on, can allow 5V to turn the LDO TPS73512 chips and 12V of 1.2V The 4th DC-DC TPS62130 chips for turning 3.3V work at the same time, while obtain the voltage and VCC_ of VCC_SOC_1V2 networks The voltage of SOC_3V3 networks.
7th, after the power is turned on, 3.3V turns the LDO REF3012 chip operations of 1.25V to the 3.3V voltages of VCC_SOC_3V3 networks, obtains To the voltage of REF_XADC_1V25 networks；3.3V turns the LDO TPS51200 chip operations of reference voltage at the same time, obtains VREF_ The reference voltage of PS_DDR3 networks and the voltage of VTTVREF_PS_DDR3_0V75 networks.
It is further preferred that power supply modular converter 7 can also include DDR terminal voltage-stablizers, the input of DDR terminal voltage-stablizers For the 0.75V voltages of the VTTVREF_PS_DDR3_0V75 networks, the output of the DDR terminals voltage-stablizer is the double-speed Rate synchronous DRAM DDR SDRAM, thus ensure for DDR SDRAM ensure high stable operating voltage, improve with The performance of machine memory.
In addition, on the basis of above-described embodiment one, the utility model embodiment also discloses a kind of finance device, the gold Melting equipment includes the mainboard of above-described embodiment.
Embodiment two
The mainboard of the finance device provided based on above-described embodiment one, the utility model embodiment two with reference to shown in Fig. 4 A kind of finance device control method step flow chart, the utility model embodiment additionally provides a kind of control of finance device Method processed, specifically may include steps of：
Step 101, the operation information for receiving user；
Specifically, the operation information of user also refers to user in ATM ATM machine and automatic teller machine CDM The financial business operation such as transfer accounts, withdraw the money and deposit on the finance devices such as machine.
In the utility model embodiment, the mainboard of finance device can receive this kind of operation information of user, so as to Operation to user is reacted.
Step 102, based on the operation information generate control instruction, and sends the control instruction to the bottom of finance device Plate, the bottom plate is used to generate corresponding execute instruction according to the control instruction, and is performed according to the execute instruction to institute State the control operation of finance device.
In the utility model embodiment, after mainboard receives the operation information of user, the memory of the core board of mainboard In control program can be directed to the operation information, generate corresponding control instruction, then send the control instruction to finance The bottom plate of equipment, bottom plate generates corresponding execute instruction after receiving control instruction, and is performed according to the execute instruction and finance is set Standby control operation, so that finance device makes the action for meeting the operation information of user, meets user demand.
In a kind of preferred embodiment of the utility model, sometimes not only only require bottom plate according to master control core board Control instruction performs corresponding operation, and bottom plate can also generate corresponding feedback information according to the control instruction, and by described in Feedback information is sent to the master control core board of finance device, so that master control core board judges whether bottom plate correctly performs control and refer to Order, if reached control purpose, then the control method of the utility model embodiment can also include the following steps：
1st, the feedback information is received, and target data is extracted from the feedback information；
Generated specifically, feedback information can be various kinds of sensors in bottom plate, such as image acquiring sensor, temperature Sensor, voltage sensor.According to the different classifications of sensor, the feedback information of imaging sensor generation can include numeral letter Number and analog signal.
In the utility model embodiment, master control core board can extract required mesh from the feedback information received Mark data.For example, the rotary speed data of motor can be extracted, the target data such as view data of bank note.
2nd, monitor whether the target data meets the requirement of the second preset data；
Specifically, each control that the second preset data is those skilled in the art to be set inside master control core board in advance The data of the desired feedback of instruction, such as the view data of intact bank note can be used as the second preset data.
, can be by target data and second after extracting target data from feedback information in the utility model embodiment Preset data is compared, and judges whether target data meets the requirement of the second preset data.
3rd, if it is not, then correcting the control instruction, until the target data meets the second preset data requirement, and Record the operation of the correction.
In the utility model embodiment, if target data does not meet the requirement of the second preset data, master control is corrected The control instruction that core board is sent, until target data meets the requirement of the second preset data, completes the control of finance device at this time Process processed, at the same time, master control core board can also record the correct operation to control instruction, subsequently to check, to analyze school Positive operation Producing reason.
Correspondingly, if target data meets the requirement of the second preset data, show that bottom plate correctly performs control Instruction.
By the description above with respect to embodiment, it is apparent to those skilled in the art that, this practicality It is new to be realized by software and required common hardware, naturally it is also possible to by hardware realization, but in many cases the former It is more preferably embodiment.Based on such understanding, the technical solution of the utility model substantially in other words does the prior art Going out the part of contribution can be embodied in the form of software product, which can be stored in computer-readable In storage medium, floppy disk, read-only storage (Read-Only Memory, ROM), random access memory such as computer (Random Access Memory, RAM), flash memory (FLASH), hard disk or CD etc., including some instructions are used so that one Computer equipment (can be personal computer, server, or network equipment etc.) performs each embodiment institute of the utility model The method stated.
Note that it above are only the preferred embodiment and institute's application technology principle of the utility model.Those skilled in the art's meeting Understand, the utility model is not limited to specific embodiment described here, can carry out for a person skilled in the art various bright Aobvious change, readjust and substitute without departing from the scope of protection of the utility model.Therefore, although passing through above example The utility model is described in further detail, but the utility model is not limited only to above example, is not departing from In the case that the utility model is conceived, other more equivalent embodiments can also be included, and the scope of the utility model is by appended Right determine.

Claims (9)

  1. A kind of 1. mainboard of finance device, it is characterised in that including：Master control core board and bottom plate；
    The Double Data Rate synchronous dynamic random storage that the master control core board includes main control chip, is electrically connected with the main control chip Device, the memory being electrically connected with the main control chip, the power supply modular converter for master control core board power supply, multiple communications connect Mouth and multiple default I/O interfaces；
    The multiple communication interface and multiple default I/O interfaces are electrically connected by detachable connector with the bottom plate；
    The memory is used to store the control program that master control core board sends control instruction, and the bottom plate is used to receive the master After controlling the control instruction that core board is sent, the control operation to finance device is performed.
  2. 2. mainboard according to claim 1, it is characterised in that the bottom plate includes being used for the work for detecting the finance device Make the sensor and electric machine controller of state；
    The electric machine controller is used to perform the control operation to the finance device, is performing the control to the finance device During operation, the sensor generates feedback information corresponding with the control instruction；
    The bottom plate is additionally operable to send the feedback information to the master control core board.
  3. 3. mainboard according to claim 1 or 2, it is characterised in that the master control core board further includes：Power Supply Monitoring is protected Circuit, the Power Supply Monitoring protection circuit are electrically connected with the main control chip, are also electrically connected with the power supply modular converter.
  4. 4. mainboard according to claim 1 or 2, it is characterised in that the master control core board further includes encryption chip；
    The encryption chip is electrically connected with the main control chip, for the first preset data to be encrypted.
  5. 5. mainboard according to claim 1 or 2, it is characterised in that the master control core board further includes USB-FHY interface cores Piece, the USB-FHY interface chips are electrically connected with the main control chip.
  6. 6. mainboard according to claim 1 or 2, it is characterised in that the multiple communication interface includes RS232 communications and connects It is at least one in mouth, Ethernet network interfaces, iic bus interface, JTAG debugging interfaces.
  7. 7. mainboard according to claim 1 or 2, it is characterised in that the master control core board further include VCC_12V0 networks, VCC_SOC_5V0 networks, VCC_SOC_1V0 networks, VCC_SOC_1V8 networks, VCC_SOC_1V5 networks, VCC_SOC_1V2 nets Network, VCC_SOC_3V3 networks, REF_XADC_1V25 networks, VREF_PS_DDR3 networks, VTTVREF_PS_DDR3_0V75 nets Network, it is described power supply modular converter include DC-DC TPS54531 chips, LDO TPS7A4501 chips, LDO TPS73512 chips, First DC-DC TPS62130 chips, the 2nd DC-DC TPS62130 chips, the 3rd DC-DC TPS62130 chips, the 4th DC- DC TPS62130 chips, LDO REF3012 chips, LDO TPS51200 chips；
    12V voltage of the DC-DC TPS54531 chips by the source voltage conversion of 24V into VCC_12V0 networks, the LDO 5V voltage of the TPS7A4501 chips by the 12V voltage conversions of VCC_12V0 networks into VCC_SOC_5V0 networks, the LDO 1.2V voltage of the TPS73512 chips by the 5V voltage conversions of VCC_SOC_5V0 networks into VCC_SOC_1V2 networks, described first 1.0V voltage of the DC-DCTPS62130 chips by the 12V voltage conversions of VCC_12V0 networks into VCC_SOC_1V0 networks, it is described 1.8V voltage of the 2nd DC-DC TPS62130 chips by the 12V voltage conversions of VCC_12V0 networks into VCC_SOC_1V8 networks, 1.5V of the 3rd DC-DC TPS62130 chips by the 12V voltage conversions of VCC_12V0 networks into VCC_SOC_1V5 networks Voltage, the 4th DC-DC TPS62130 chips are by the 12V voltage conversions of VCC_12V0 networks into VCC_SOC_3V3 networks 3.3V voltages, the LDO REF3012 chips are by the 3.3V voltage conversions of VCC_SOC_3V3 networks into REF_XADC_1V25 nets The 1.25V voltages of network, the LDO TPS51200 chips are by the 3.3V voltage conversions of VCC_SOC_3V3 networks into VREF_PS_ The reference voltage of DDR3 networks and the 0.75V voltages of VTTVREF_PS_DDR3_0V75 networks.
  8. 8. mainboard according to claim 7, it is characterised in that the power supply modular converter further includes DDR terminal voltage-stablizers, The 0.75V voltages inputted as the VTTVREF_PS_DDR3_0V75 networks of the DDR terminals voltage-stablizer, the DDR The output of terminal voltage-stablizer is the Double Data Rate synchronous DRAM.
  9. 9. a kind of finance device, it is characterised in that the finance device includes claim 1-8 any one of them mainboards.
CN201721299332.XU 2017-10-10 2017-10-10 The mainboard and finance device of a kind of finance device Expired - Fee Related CN207281885U (en)

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Application Number Priority Date Filing Date Title
CN201721299332.XU CN207281885U (en) 2017-10-10 2017-10-10 The mainboard and finance device of a kind of finance device

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