CN207164208U - A kind of test system of chip - Google Patents
A kind of test system of chip Download PDFInfo
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- CN207164208U CN207164208U CN201721163007.0U CN201721163007U CN207164208U CN 207164208 U CN207164208 U CN 207164208U CN 201721163007 U CN201721163007 U CN 201721163007U CN 207164208 U CN207164208 U CN 207164208U
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Abstract
The utility model discloses a kind of test system of chip, including control assembly, tester and memory；The ID data of the chip to be measured are sent to control assembly by test；Control assembly is connected with tester；Control assembly sends ID to tester and reads control signal, and receives the ID data of the chip to be measured of tester transmission, and the ID data of chip to be measured are converted into binary data；Control assembly storage address according to corresponding to obtaining the binary data, obtain the test mode information of storage address storage.The utility model may determine that whether the ID of chip to be measured duplicates, and realize the function of anti-repeated code test, and can effectively prevent the retest of chip.
Description
Technical field
Chip testing field is the utility model is related to, more particularly to a kind of test system of chip.
Background technology
With the fast development of science and technology, chip is obtained due to superior functions such as its small volume, the reliable convenience of data record
It is extensive to use, identification chip is set such as on China second-generation identity card, bank's the core of the card etc. is set on bank card.
In the prior art, when tester is tested chip, also only surveyed come unique identification chip generally by ID
Whether normal try chip various functions, the ID of the chip of test is not recorded, therefore, when the chip for same ID occur
When, existing tester can not test out, and the situation of ID repeated codes easily occur, this undoubtedly can to chip it is follow-up using and
Security performance causes strong influence；The situation for chip retest occur is also easy to simultaneously, influences testing efficiency.
Utility model content
Based on this, the purpose of this utility model is, there is provided a kind of test system of chip, it has the ID for judging chip
Whether duplicate, and judge chip whether retest the advantages of.
A kind of test system of chip, including control assembly, tester and memory；
The ID that the tester is used to receive the control assembly transmission reads control signal, and obtains the ID of chip to be measured
Data, and the ID data of the chip to be measured are sent to the control assembly；
The control assembly is connected with the tester；The control assembly is used to send ID reading controls to the tester
Signal processed, and the ID data of the chip to be measured of the tester transmission are received, and the ID data of chip to be measured are converted to two and entered
Data processed；The control assembly is additionally operable to the storage address according to corresponding to obtaining the binary data, with obtaining the memory
The test mode information of location storage；
The memory is connected with the tester, and stores the test mode information of chip to be measured.
Compared to prior art, the present invention is converted to by obtaining chip ID data to be measured, and by chip ID data to be measured
The binary data corresponding with storage address, and then only need to believe by the test mode for judging storage address memory storage
Cease the test mode situation represented, it is possible to judge whether the ID of chip to be measured duplicates, realize the work(of anti-repeated code test
Can, and can effectively prevent the retest of chip.
Further, the tester includes ID reading devices, order reception apparatus, data link and memory number
According to read-write equipment；The output end of the order reception apparatus is connected with the input of the ID reading devices；The data transmission
The input of device is connected with the output end of the ID reading devices；The input of the ID reading devices also with the memory
Output end connection；The input of the memory data read-write equipment is connected with the output end of the memory, the storage
The output end of device data read-write equipment is connected with the input of the data link；
The ID that the order reception apparatus receives the control assembly transmission reads control signal, and the ID is read and controlled
Signal processed is sent to the ID reading devices；The ID reading devices receive the ID and read control signal, and read core to be measured
The ID data of piece, and the ID data of chip to be measured are sent to the data link；The data link receives institute
The ID data of chip to be measured are stated, and the ID data of the chip to be measured are sent to the control assembly；The memory data is read
Write device receives the memory that the control assembly is sent and reads signal, and the test mode information that storage address is stored is led to
Cross the data link and be sent to the control assembly.
Further, the control assembly also includes test control device and comparison means；The test control device
Input is connected with the output end of the comparison means, and the output end of the test control device and the instruction sending device
Input connection；The tester also includes test device；The input of the test device and the order reception apparatus
Output end connection；Input of the output end of the memory data read-write equipment also with the memory is connected；
The digital independent device obtains non-test data mark, and is sent to the comparison means, the comparison means
By the non-test data mark compared with the test data mark stored, and non-test signal is sent to the test control
Device processed, the test control device send test signal by the instruction sending device to the tester；The test
The test signal is sent to the test device and memory data read-write equipment by the order reception apparatus of instrument；The test
Device receives the test signal and chip to be measured is tested, and the memory data read-write equipment receives the test letter
Number and the test mode information flag that stores the storage address be the mark of test data；
The digital independent device obtains non-test data mark, and is sent to the comparison means, the comparison means
By the non-test data mark compared with the test data mark stored, and test signal is sent to the test and controlled
Device processed, the test control device receive this and do not send test signal to the tester after test signal.
Further, in addition to alarm；The output end of the input of the alarm and the test control device connects
Connect；After the test control device receives the test signal, transmission alarm signal to the alarm；The alarm connects
Receive the alarm signal and alarm, to remind tester's chip, avoid the occurrence of the chip or retest chip of repeated code.
Further, the test control device receive described in the ID data of chip to be measured are also recorded after test signal,
The chip of repeated code or the chip of retest are recorded with realizing.
Compared to prior art, the present invention is converted to by obtaining chip ID data to be measured, and by chip ID data to be measured
The binary data corresponding with storage address, and then only need to believe by the test mode for judging storage address memory storage
Cease the test mode situation represented, it is possible to judge whether the ID of chip to be measured duplicates, realize the work(of anti-repeated code test
Can, and can effectively prevent the retest of chip.Meanwhile using the binary data as storage address, deposited with obtaining this
The test mode information of memory address storage, without recording the id information of complete test chip, greatlys save space, improves
Testing efficiency.Further, it is used as read-write data bit by retaining a data bit of memory, by other numbers of memory
According to position as high address, using the address of former memory as low order address, more storage address are expanded with combination, from
And realize and the test mode of numerous chip ids is recorded, reduce testing cost.
In order to more fully understand and implement, the utility model is described in detail below in conjunction with the accompanying drawings.
Brief description of the drawings
Fig. 1 is the theory diagram of the test system of the utility model embodiment chips；
Fig. 2 is the structured flowchart of the test system of the utility model embodiment chips.
Embodiment
Please refer to Fig. 1 and Fig. 2, Fig. 1 is the theory diagram of the test system of the utility model embodiment chips；Figure
2 be the structured flowchart of the test system of the utility model embodiment chips.The test system of the chip, including tester 1, control
Component 2 and memory 3 processed.
The tester 1 is used to receive the ID reading control signals that the control assembly 2 transmits, and obtains chip to be measured
ID data, and the ID data of the chip 4 to be measured are sent to the control assembly 2.
The control assembly 2 is connected with the tester 1；The control assembly 2 is used to send ID readings to the tester 1
Control signal is taken, and receives the ID data for the chip to be measured 4 that the tester 1 transmits, and by the ID data conversions of chip 4 to be measured
For binary data；The control assembly 2 is additionally operable to the address of memory 3 according to corresponding to obtaining the binary data, and obtaining should
The test mode information of the address of memory 3 storage.
The memory is connected with the tester 1, and stores the test mode information of chip 4 to be measured.
The tester 1 includes ID reading devices 11, order reception apparatus 12, data link 13 and memory data
Read-write equipment 14.The input of the ID reading devices 11 is connected with the output end of chip 4 to be measured.The order reception apparatus 12
Output end be connected with the input of the ID reading devices 11；The input of the data link 13 is read with the ID
The output end connection of device 11；The input of the memory data read-write equipment 14 is connected with the output end of the memory 3,
The output end of the memory data read-write equipment 14 is connected with the input of the data link 13.
The ID that the control assembly 2 that the order reception apparatus 12 receives transmits reads control signal, and the ID is read
Control signal is taken to be sent to the ID reading devices；The ID reading devices 11 receive the ID and read control signal, and read
The ID data of chip 4 to be measured, and the ID data of chip 4 to be measured are sent to the data link 13；The data transmission
Device 13 receives the ID data of the chip to be measured 4, and the ID data of the chip 4 to be measured are sent into the control assembly 2.Institute
State memory data read-write equipment 14 and receive the memory reading signal that the control assembly 2 is sent, and storage address is deposited
The test mode information of storage is sent to the control assembly by the data link 13.
The ID reading devices 11 can be RF Reader, identify the chip id outside the chip 4 to be measured；The ID
Reading device 11 can also be data reading circuit, and the chip 4 to be measured is read from the stationary storage position of the chip 4 to be measured
ID data.The order reception apparatus 12 can be cable receiver or wireless receiver, be sent with obtaining control assembly 2
Instruction.The data link 13 can be the various devices that various transfer functions can be achieved.The memory data is read
Write device 14 can be the read write line conventionally used for reading memory.
The control assembly 2 includes instruction sending device 21, resolver 22 and data reading device 23.The parsing dress
22 output end is put to be connected with the input of the digital independent device 23；The output end of the digital independent device 23 with it is described
The input connection of instruction sending device 21.
The instruction sending device 21 sends ID to the tester 1 and reads control signal；The resolver 22 receives
The ID data for the chip to be measured 4 that the tester 1 transmits, and the ID data of the chip 4 to be measured are converted into binary data, and
It is sent to the digital independent device 23；The digital independent device 23 is sent according to the binary data and by the instruction
Device 21 sends memory to the memory data read-write equipment and reads signal, the test shape of the storage address storage of acquisition
State information.
The instruction sending device 21 can be wired transmitter or radio transmitter, be instructed with being sent to tester 1.
The resolver can be compiler, the ID data that identification tester 1 is sent.
In one embodiment, the control assembly 2 also includes comparison means 24 and test control device 25；The comparison
The input of device 24 is connected with the output end of the digital independent device 23, output end and the survey of the comparison means 24
Try the input connection of control device 25；The output end of the test control device 25 and the input of the instruction sending device 21
End connection.The tester 1 also includes test device 15；The input of the test device 15 and the order reception apparatus 12
Output end connection；Input of the output end of the memory data read-write equipment 14 also with the memory is connected.The survey
Test system also includes alarm 5.The input of the alarm 5 is connected with the output end of the test control device.
The digital independent device 23 obtains non-test data mark, and is sent to the comparison means 24；The comparison
Device 24 by non-test data mark compared with the test data mark of storage, and will be described in non-test signal be sent to
Test control device 25；The test control device 25 receives the non-test signal, and passes through the instruction sending device 21
Test signal is sent to the tester 1.The test signal is sent to described by the order reception apparatus 12 of the tester 1
Test device 15 and memory data read-write equipment 14；The test device 15 receives the test signal and to chip 4 to be measured
Tested, the memory data read-write equipment 14 receives the test signal and the test for storing the storage address
Status information marks labeled as test data.
The digital independent device 23 obtains non-test data mark, and is sent to the comparison means 24；The comparison
Device 24 by non-test data mark compared with the test data mark of storage, and described in test signal is sent to
Test control device 25, the test control device 25 receive this and do not send test signal to the tester after test signal
1。
The comparison means 24 can be comparison circuit or comparator, be sentenced with the test mode information according to memory storage
The chip 4 to be measured that breaks, which is not tested, still have been tested.
The test control device 25 receives the ID data that chip 4 to be measured is also recorded after the test signal, and described
After test control device 25 receives the test signal, alarm signal is also sent to the alarm 5；The alarm 5 connects
Receive the alarm signal and alarm.In one embodiment, the test control device 25 can be controller or single-chip microcomputer etc..
In one embodiment, during initialization, the test mode information that 3 each storage address of memory stores is all provided with
For 0, and set using 0 and to be marked as non-test data, the mark of test data is used as using 1.
In one embodiment, the alarm 4 is an alarm lamp.
In one embodiment, the model V5 of the tester 11, the memory 3 is model AM29F0080B
flash。
It is excessively excessive effectively to solve the problems, such as that data occurs in overabundance of data, in one embodiment, the one of reservation memory 3
Individual data bit, using other data bit of memory 3 as high address, the address of former memory 3 is made as read-write data bit
For low order address, the new address of memory 3 is expanded to combination, and then record the test mode of more chip ids.
Specifically, by taking model AM29F0080B flash as an example, it includes 20 address bits and 8 data bit, wherein
20 address bits are expressed as Addr bit0, Addr bit1, Addr bit2 ... Addr bit18, Addr bit19,8
Data bit is expressed as Data bit0, Data bit1 ... Data bit6, Data bit7：When only with 20 address bits
When corresponding with chip ID data, control assembly 2 searches data corresponding to the address of memory 3 by tester 1, and tester 1 is straight
Connect and the test mode information transmission of 20 address bit memory storages corresponding to chip ID data is returned into control assembly 2, now, memory
3 can store 220The information of=1048576 chip ids.When using one of data bit such as Data bit0 as data bit, its
His data bit such as Data bit1, Data bit2 ... Data bit6, Data bit7 is as high address Addr bit20, Addr
Bit21 ... Addr bit20, former 20 address bits are as low order address, and the chip ID data with 27 is corresponding, control assembly 2
Data corresponding to the address of memory 3 are searched by tester 1, first search address high Data bit1, Data bit2 ... Data
Bit6, Data bit7 information, then the information of i.e. former 20 address bits of address low level is searched, and then obtain chip ID data pair
The address answered, so as to obtain the status information of address storage, now, memory 3 can store 227=134217728 chips
ID information.If data now are not enough, flash number can be increased as needed.
Compared to prior art, the present invention is converted to by obtaining chip ID data to be measured, and by chip ID data to be measured
The binary data corresponding with storage address, and then only need to believe by the test mode for judging storage address memory storage
Cease the test mode situation represented, it is possible to judge whether the ID of chip to be measured duplicates, realize the work(of anti-repeated code test
Can, and can effectively prevent the retest of chip.Meanwhile using the binary data as storage address, deposited with obtaining this
The test mode information of memory address storage, without recording the id information of complete test chip, greatlys save space, improves
Testing efficiency.Further, it is used as read-write data bit by retaining a data bit of memory, by other numbers of memory
According to position as high address, using the address of former memory as low order address, more storage address are expanded with combination, from
And realize and the test mode of numerous chip ids is recorded, reduce testing cost.
Embodiment described above only expresses several embodiments of the present utility model, and its description is more specific and detailed,
But therefore it can not be interpreted as the limitation to utility model patent scope.It should be pointed out that the common skill for this area
For art personnel, without departing from the concept of the premise utility, various modifications and improvements can be made, these are belonged to
The scope of protection of the utility model.
Claims (6)
1. a kind of test system of chip, it is characterised in that including control assembly, tester and memory；
The ID that the tester is used to receive the control assembly transmission reads control signal, and obtains the ID numbers of chip to be measured
According to, and the ID data of the chip to be measured are sent to the control assembly；
The control assembly is connected with the tester；The control assembly is used to send ID to the tester and read to control to believe
Number, and the ID data of the chip to be measured of the tester transmission are received, and the ID data of chip to be measured are converted into binary number
According to；The control assembly is additionally operable to the storage address according to corresponding to obtaining the binary data, obtains the storage address and deposits
The test mode information of storage；
The memory is connected with the tester, and stores the test mode information of chip to be measured.
2. the test system of chip according to claim 1, it is characterised in that the tester include ID reading devices,
Order reception apparatus, data link and memory data read-write equipment；The output end of the order reception apparatus with it is described
The input connection of ID reading devices；The input of the data link is connected with the output end of the ID reading devices；
Output end of the input of the ID reading devices also with the memory is connected；The input of the memory data read-write equipment
End is connected with the output end of the memory, output end and the data link of the memory data read-write equipment
Input connects；
The ID that the order reception apparatus receives the control assembly transmission reads control signal, and the ID is read into control letter
Number it is sent to the ID reading devices；The ID reading devices receive the ID and read control signal, and read chip to be measured
ID data, and the ID data of chip to be measured are sent to the data link；The data link is treated described in receiving
The ID data of chip are surveyed, and the ID data of the chip to be measured are sent to the control assembly；The memory data read-write dress
Put and receive the memory reading signal that the control assembly is sent, and the test mode information that storage address is stored passes through institute
State data link and be sent to the control assembly.
3. the test system of chip according to claim 2, it is characterised in that the control assembly includes instruction and sends dress
Put, resolver and data reading device；The output end of the resolver is connected with the input of the digital independent device；
The output end of the digital independent device is connected with the input of the instruction sending device；
The instruction sending device sends ID to the tester and reads control signal；The resolver receives the tester
The ID data of the chip to be measured of transmission, and the ID data of the chip to be measured are converted into binary data, and it is sent to the number
According to reading device；The digital independent device is according to the binary data and by the instruction sending device to the memory
Data read-write equipment sends memory and reads signal, and obtains the test mode information of storage address storage.
4. the test system of chip according to claim 3, it is characterised in that the control assembly also includes testing and control
Device and comparison means；The input of the test control device is connected with the output end of the comparison means, and the test
The output end of control device is connected with the input of the instruction sending device；The tester also includes test device；It is described
The input of test device is connected with the output end of the order reception apparatus；The output end of the memory data read-write equipment
Input also with the memory is connected；
The digital independent device obtains non-test data mark, and is sent to the comparison means, and the comparison means should
Non- test data mark is sent to the testing and control dress compared with the test data mark stored, and by non-test signal
Put, the test control device sends test signal by the instruction sending device to the tester；The tester
The test signal is sent to the test device and memory data read-write equipment by order reception apparatus；The test device
Receive the test signal and chip to be measured is tested, the memory data read-write equipment receives the test signal simultaneously
The test mode information flag that the storage address is stored marks for test data；
The digital independent device obtains non-test data mark, and is sent to the comparison means, and the comparison means should
Test signal is sent to the testing and control and filled by non-test data mark compared with the test data mark stored
Put, the test control device receives this and do not send test signal to the tester after test signal.
5. the test system of chip according to claim 4, it is characterised in that also including alarm；The alarm
Input is connected with the output end of the test control device；After the test control device receives the test signal, send out
Alarm signal is sent to the alarm；The alarm receives the alarm signal and alarmed.
6. the test system of chip according to claim 5, it is characterised in that described in the test control device reception
The ID data of chip to be measured are also recorded after test signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721163007.0U CN207164208U (en) | 2017-09-11 | 2017-09-11 | A kind of test system of chip |
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| CN201721163007.0U CN207164208U (en) | 2017-09-11 | 2017-09-11 | A kind of test system of chip |
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| CN207164208U true CN207164208U (en) | 2018-03-30 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107656188A (en) * | 2017-09-11 | 2018-02-02 | 东莞市爱协生智能科技有限公司 | The test system and its method of a kind of chip |
| CN111190092A (en) * | 2019-12-27 | 2020-05-22 | 上海华岭集成电路技术股份有限公司 | FPGA test quality control optimization system |
| CN113009316A (en) * | 2021-02-20 | 2021-06-22 | 上海燧原科技有限公司 | Interface conversion circuit, multi-chip interconnection system and test method thereof |
-
2017
- 2017-09-11 CN CN201721163007.0U patent/CN207164208U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107656188A (en) * | 2017-09-11 | 2018-02-02 | 东莞市爱协生智能科技有限公司 | The test system and its method of a kind of chip |
| CN107656188B (en) * | 2017-09-11 | 2023-12-29 | 深圳市爱协生科技股份有限公司 | Chip testing system and method |
| CN111190092A (en) * | 2019-12-27 | 2020-05-22 | 上海华岭集成电路技术股份有限公司 | FPGA test quality control optimization system |
| CN113009316A (en) * | 2021-02-20 | 2021-06-22 | 上海燧原科技有限公司 | Interface conversion circuit, multi-chip interconnection system and test method thereof |
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Effective date of registration: 20230120 Address after: 518100 Zone D and E, floor 7, building 3, Tingwei Industrial Park, No. 6, Liufang Road, Xin'an street, Bao'an District, Shenzhen, Guangdong Patentee after: Shenzhen Aixiesheng Technology Co.,Ltd. Address before: 523000 Zhongji Valley Building, No. 1 Nanshan Road, Songshan Lake Hi-tech Industrial Development Zone, Dongguan City, Guangdong Province Patentee before: DONGGUAN AIXIESHENG INTELLIGENT TECHNOLOGY CO.,LTD. |
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