CN207082320U - A kind of image element circuit and display device - Google Patents
A kind of image element circuit and display device Download PDFInfo
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- CN207082320U CN207082320U CN201721082760.7U CN201721082760U CN207082320U CN 207082320 U CN207082320 U CN 207082320U CN 201721082760 U CN201721082760 U CN 201721082760U CN 207082320 U CN207082320 U CN 207082320U
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Abstract
The utility model embodiment provides a kind of image element circuit and display device, is related to display technology field, the problem of can solve the problem that short-term image retention.The image element circuit includes resetting module, drive module, writing module, compensating module, light emitting control module and luminescent device.Module is reset to write to the first pole of driving transistor by the grid of driving transistor in the initial voltage write driver module at initial voltage end, and by the voltage at tertiary voltage end；Driving transistor is in the conduction state in reset phase；Writing module writes the data voltage at data voltage end into drive module；Compensating module compensates to the threshold voltage of driving transistor in drive module；Light emitting control module caused driving current in the presence of first voltage end and second voltage end and the data voltage write to the drive module by drive module, is transmitted to luminescent device；Luminescent device is lighted according to driving current.Above-mentioned image element circuit is used to drive sub-pix to be shown.
Description
Technical field
It the utility model is related to display technology field, more particularly to a kind of image element circuit and display device.
Background technology
Organic electroluminescent LED (Organic Light Emitting Diode, OLED) display is to study at present
One of the focus in field, compared to liquid crystal display (Liquid Crystal Display, LCD), OLED has low energy consumption, life
The advantages that producing low cost, self-luminous, fast wide viewing angle and corresponding speed.
However, OLED display is when different grey menus switch at present, such as the black and white lattice picture shown by Fig. 1 a
Be switched to grey decision-making be 128 pure grey menu when, it may appear that short-term afterimage phenomena, the image now shown as shown in Figure 1 b,
The image retention of previous frame black and white lattice picture in the display picture be present.Above-mentioned short-term afterimage phenomena disappears after continuing 1 minute, now shows
Show pure grey menu that the grey decision-making that device shows is 128 as illustrated in figure 1 c.Above-mentioned short-term afterimage phenomena causes shadow to display effect
Ring.
Utility model content
Embodiment of the present utility model provides a kind of image element circuit and display device, the problem of can solve the problem that short-term image retention.
To reach above-mentioned purpose, embodiment of the present utility model adopts the following technical scheme that：
The one side of the utility model embodiment, there is provided a kind of image element circuit, including reset module, drive module, write-in
Module, compensating module, light emitting control module and luminescent device；The drive module includes driving transistor, and the driving is brilliant
First pole of body pipe is connected with said write module；The replacement module connection initial voltage end, tertiary voltage end, the drive
Dynamic model block；The module that resets is used to the initial voltage at the initial voltage end writing driving transistor in the drive module
Grid, and the voltage at the tertiary voltage end is write to the first pole of the driving transistor；The driving transistor exists
Reset phase is in the conduction state；Said write module connects data voltage end and the drive module；Said write module
For the data voltage at the data voltage end to be write into the drive module；The compensating module connects the driving mould
Block；The compensating module is used to compensate the threshold voltage of driving transistor in the drive module；The light emitting control
Module connects the anode of LED control signal end, first voltage end, the drive module and the luminescent device；It is described luminous
The negative electrode connection second voltage end of device；The light emitting control module is used under the control at the LED control signal end, will
The drive module is at the first voltage end and the second voltage end and writes to the data voltage of the drive module
Driving current caused by effect is lower, is transmitted to the luminescent device；The luminescent device is used to be carried out according to the driving current
It is luminous.
Preferably, the anode for resetting module and being also connected with the luminescent device；The replacement module is used for will be described first
The initial voltage of beginning voltage end is write to the anode of the luminescent device.
Preferably, said write module includes the first transistor, grid connection the first gating letter of the first transistor
Number end, the first pole connect the data voltage end, and the second pole is connected with the first pole of the driving transistor；The compensation mould
Block includes second transistor, and the grid of the second transistor connects the second gating signal end, and connection driving in the first pole is brilliant
The grid of body pipe, the second pole are connected with the second pole of the driving transistor；The light emitting control module includes the 3rd crystal
Pipe and the 4th transistor；The grid of the third transistor connects the 3rd gating signal end, and the first pole connects the first voltage
End, the second pole is connected with the first pole of the driving transistor；The grid of 4th transistor connects the 4th gating signal
End, the first pole connect the second pole of the driving transistor, and the second pole is connected with the anode of the luminescent device；The driving
Module also includes storage capacitance；One end of the storage capacitance connects the first voltage end, the other end and the driving crystal
The grid of pipe is connected.
Preferably, the replacement module includes grid replacement submodule and the first pole resets submodule；The grid is reset
Submodule connects the grid of the initial voltage end and the driving transistor；The grid replacement submodule is used for will be described first
The initial voltage of beginning voltage end writes the grid of the driving transistor；First pole resets submodule connection the 3rd electricity
First pole of pressure side and the driving transistor；First pole resets submodule and is used to write the voltage at the tertiary voltage end
Enter to the first pole of the driving transistor；Or the replacement module includes the grid and resets submodule and described second
Pole resets submodule；Second pole resets submodule and connects the tertiary voltage end and the second pole of the driving transistor；Institute
State the second pole and reset submodule for the voltage at the tertiary voltage end to be write to the second pole of the driving transistor.
Preferably, the grid, which resets submodule, includes the 5th transistor, the grid connection the 5th of the 5th transistor
Gating signal end, the first pole connect the grid of the driving transistor, and the second pole is connected with the initial voltage end.
Preferably, in the case where resetting module and being also connected with the anode of the luminescent device, the grid resets submodule
Including the 6th transistor；The grid of 6th transistor connects the 6th gating signal end, and the first pole connects the luminescent device
Anode, the second pole is connected with the initial voltage end；The compensating module is multiplexed with one that the grid resets submodule
Part, the grid, which resets submodule, also includes the second transistor；A part for the light emitting control module is multiplexed with institute
The part that grid resets submodule is stated, the grid, which resets submodule, also includes the 4th transistor.
Preferably, the tertiary voltage end connects the data voltage end, includes first pole in the replacement module
In the case of resetting submodule, said write module reuse is that first pole resets submodule；First pole resets submodule
Block includes the first transistor.
Preferably, the tertiary voltage end connects the first voltage end, includes first pole in the replacement module
In the case of resetting submodule, a part for the light emitting control module is multiplexed with first pole and resets submodule；Described
One pole, which resets submodule, includes the third transistor.
Preferably, the tertiary voltage end connection reference voltage end, resets in the replacement module including second pole
In the case of submodule, second pole, which resets submodule, includes the 7th transistor；The grid connection the of 7th transistor
Seven control signal ends, the first pole connect the reference voltage end, and the second pole is connected with the second pole of the driving transistor.
Preferably, the tertiary voltage end connection reference voltage end, resets in the replacement module including first pole
In the case of submodule, first pole, which resets submodule, includes the 7th transistor；The grid connection the of 7th transistor
Seven control signal ends, the first pole connect the reference voltage end, and the second pole is connected with the first pole of the driving transistor.
Preferably, in the case where resetting module and being also connected with the anode of the luminescent device, the replacement module also includes
6th transistor；The grid of 6th transistor connects the 6th gating signal end, and the first pole connects the sun of the luminescent device
Pole, the second pole are connected with the initial voltage end.
The another aspect of the utility model embodiment, there is provided a kind of display device, including any one picture as described above
Plain circuit.
The utility model embodiment provides a kind of image element circuit and display device, from the foregoing, in the image element circuit
DTFT (ON-Bias) in the conduction state can be caused at the end of reset phase by resetting module.In the case, display surface is worked as
In the image element circuit of each sub-pix of plate, DTFT is different sub- when reset phase is in above-mentioned conducting state (ON-Bias)
The DTFT of pixel gate source voltage Vgs is respectively positioned on characteristic the top, and corresponding electric current Ids is identical, and electric current Ids is very
Greatly.Therefore when showing next image frame, the brightness of each sub-pix is required to reduce, i.e., DTFT electric current in each sub-pix
Ids needs to reduce, therefore DTFT semiconductor layer and gate insulator layer interface are required to carry out electric charge release in each sub-pix
(Hole Detrapping), and each DTFT charge-trapping release way is identical, so as to solve asking for above-mentioned short-term image retention
Topic.
Brief description of the drawings
, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art
Or the required accompanying drawing used is briefly described in description of the prior art, it should be apparent that, drawings in the following description are only
It is some embodiments of the utility model, for those of ordinary skill in the art, is not paying the premise of creative work
Under, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 a are a kind of display image that prior art provides；
Fig. 1 b are the schematic diagram that the image that prior art is shown has short-term image retention；
Fig. 1 c are another display image that prior art provides；
Fig. 1 d are a kind of schematic diagram for the short-term image retention of generation that prior art provides；
Fig. 2 is a kind of structural representation for image element circuit that the utility model embodiment provides；
Fig. 3 a are a kind of concrete structure schematic diagram of part of module in Fig. 2；
Fig. 3 b are another concrete structure schematic diagram of part of module in Fig. 2；
Fig. 4 is the first set-up mode schematic diagram that module is reset in Fig. 3 a or Fig. 3 b；
Fig. 5 a are a kind of clock signal figure of each drive signal for the image element circuit shown in control figure 4；
Fig. 5 b are the reset phase shown in Fig. 5 a, a kind of break-make situation of each transistor in Fig. 4 image element circuit；
Fig. 6 a are another clock signal figure of each drive signal for the image element circuit shown in control figure 3；
Fig. 6 b are the write-in compensated stage shown in Fig. 6 a, a kind of break-make situation of each transistor in Fig. 3 image element circuit；
Fig. 7 a are another clock signal figure of each drive signal for the image element circuit shown in control figure 4；
Fig. 7 b are the glow phase in Fig. 7 a, a kind of break-make situation of each transistor in Fig. 3 image element circuit；
Fig. 8 is second of set-up mode schematic diagram that module is reset in Fig. 3 a or Fig. 3 b；
Fig. 9 a are a kind of clock signal figure of each drive signal for the image element circuit shown in control figure 8；
Fig. 9 b are the reset phase shown in Fig. 9 a, a kind of break-make situation of each transistor in Fig. 8 image element circuit；
Figure 10 a are another clock signal figure of each drive signal for the image element circuit shown in control figure 8；
Figure 10 b are the write-in compensated stage shown in Figure 10 a, a kind of break-make feelings of each transistor in Fig. 8 image element circuit
Condition；
Figure 11 a are another clock signal figure of each drive signal for the image element circuit shown in control figure 8；
Figure 11 b are the glow phase in Figure 11 a, a kind of break-make situation of each transistor in Fig. 8 image element circuit；
Figure 12 is the third set-up mode schematic diagram that module is reset in Fig. 3 a or Fig. 3 b；
Figure 13 a, Figure 13 b and Figure 13 c are respectively that the image element circuit shown in Figure 12 compensates rank in reset phase, write-in respectively
The operating diagram of section and glow phase；
Figure 14 is the 4th kind of set-up mode schematic diagram that module is reset in Fig. 3 a or Fig. 3 b；
Figure 15 a, Figure 15 b and Figure 15 c are respectively that the image element circuit shown in Figure 14 compensates rank in reset phase, write-in respectively
The operating diagram of section and glow phase；
Figure 16 is the 5th kind of set-up mode schematic diagram that module is reset in Fig. 3 a or Fig. 3 b；
Figure 17 a, Figure 17 b and Figure 17 c are respectively that the image element circuit shown in Figure 16 compensates rank in reset phase, write-in respectively
The operating diagram of section and glow phase.
Reference：
10- resets module；20- drive modules；30- writing modules；40- compensating modules；50- light emitting control modules；S1-
Scan signal end；The second scanning signals of S2- end；EM- LED control signals end；Vint- initial voltages end；Data- data electricity
Pressure side；ELVDD- first voltages end；ELVSS- second voltages end；The first gating signals of G1- end；The second gating signals of G2- end；
The gating signal ends of G3- the 3rd；The gating signal ends of G4- the 4th；The gating signal ends of G5- the 5th；The gating signal ends of G6- the 6th；G7-
Seven gating signal ends；P1- reset phases；P2- writes compensated stage；P3- glow phases.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out
Clearly and completely describing, it is clear that described embodiment is only the utility model part of the embodiment, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment obtained, belong to the scope of the utility model protection.
The utility model embodiment provides a kind of image element circuit, as shown in Fig. 2 including replacement module 10, drive module 20,
Writing module 30, compensating module 40, light emitting control module 50 and luminescent device L.
Wherein, above-mentioned drive module 20 includes driving transistor (hereinafter referred to as DTFT) as shown in Figure 3, and the first of the DTFT
Pole is connected with writing module 30.
Further, above-mentioned drive module 20 is also connected with first voltage end ELVDD, and now drive module 20 also includes storage
Electric capacity Cst.Wherein, storage capacitance Cst one end connection first voltage end ELVDD, the other end are connected with DTFT grid.
So, storage capacitance Cst can ensure DTFT grid voltages Vg stability.
The connected mode of above-mentioned modules is illustrated below.
Specifically, as shown in Fig. 2 resetting module 10 connects initial voltage end Vint, tertiary voltage end V3 and driving mould
Block 20.The replacement module 10 is used for the grid of DTFT in initial voltage end Vint initial voltage write driver module 20, and
Tertiary voltage end V3 voltage is write to DTFT the first pole.The DTFT is (ON-Bias) in the conduction state in reset phase.
It should be noted that the application is not limited the type of the DTFT, can be N-type transistor, or p-type
Transistor.Below using the DTFT as p-type, exemplified by enhancement transistor.Now, the extremely source electrode of the first of above-mentioned DTFT, the second pole
For drain electrode.
Based on this, when initial voltage end Vint initial voltage is write to DTFT grid, due to initial voltage end
Vint is usually low level, and now DTFT is turned on.Tertiary voltage end V3 voltage is write to DTFT the first pole, i.e. source electrode.This
When, the gate source voltage Vgs=Vint-V3 of the DTFT.In this case, it is possible to control above-mentioned tertiary voltage end V3 output voltages
Size, to cause Vgs=Vint-V3 ＜ Vth, so that the DTFT (ON-Bias) in the conduction state.Wherein, for p-type
For transistor enhancement transistor, turn-on condition is that Vgs ＜ Vth, Vth are negative value.
Through analysis shows, thin film transistor (TFT) (Drive Thin are driven in above-mentioned short-term afterimage phenomena and OLED display
Film Transistor, DTFT) hysteresis effect it is relevant.The process of the hysteresis effect as shown in Figure 1 d, wherein, dot-dash in Fig. 1
When line is that the source-drain voltage of the DTFT in the sub-pix of white picture is shown in OLED display is Vds1, the electric current Ids of the DTFT
With Vgs characteristic curve；When dotted line is that to show the source-drain voltage of the DTFT in the sub-pix of black picture be Vds3, DTFT electric current
Ids and Vgs characteristic curve；Solid line is the DTFT source-drain voltage for showing in sub-pix that grey decision-making is 128 when being VdS2,
DTFT electric current and Vgs characteristic curve.
It can be seen from Fig. 1 b when white picture switches to grey menu, showing the brightness of the sub-pix of white picture needs
Reduce, DTFT electric current Ids needs to reduce in the sub-pix, therefore in the sub-pix DTFT semiconductor layer and gate insulation layer
Interface needs to carry out electric charge release (Hole Detrapping), and by A1 points to A2 points, now Vgs values are become by V_w turns to V_g；When
When black picture switches to grey menu, show that the brightness of the sub-pix of black picture needs to raise, DTFT electric current in the sub-pix
Ids needs to increase, therefore DTFT semiconductor layer and gate insulator layer interface need to carry out charge-trapping (Hole in the sub-pix
Trapping), by A3 points to A4 points, now Vgs values are become by V_b turns to V_g.It can thus be seen that due to electric charge capture and release
The path of voltage change is different during putting, thus along different paths reach voltage V-g A2 points and A4 points respectively corresponding to electricity
It is different to flow Ids, so so that changed to the sub-pix of grey menu by white picture and changed by black picture to grey menu
Sub-pix between luminance difference be present, so as to short-term afterimage phenomena as illustrated in figure 1 c occur.After placing one end time, on
State A2 points and A4 points reach B points, image retention disappears.
Based on this, when in the image element circuit of each sub-pix of display panel, DTFT is in above-mentioned lead in reset phase
During logical state (ON-Bias), as shown in Figure 1 d, the DTFT of different sub-pixs gate source voltage Vgs be respectively positioned on it is characteristic most
Upper end, corresponding electric current Ids is identical, and electric current Ids is very big.Therefore when showing next image frame, each sub-pix it is bright
Degree be required to reduce, i.e., DTFT electric current Ids needs to reduce in each sub-pix, thus in each sub-pix DTFT semiconductor
Layer and gate insulator layer interface are required to carry out electric charge release (Hole Detrapping), by A1 points to A2 points, each DTFT electricity
Lotus capture release way is identical, so as to solve the problems, such as above-mentioned short-term image retention.Further, since the image element circuit that the application provides can
To solve the problems, such as short-term image retention, and consider to need certain display refresh rates during display panel display picture, therefore need not
Display image is carried out static.
On this basis, as shown in Fig. 2 above-mentioned replacement module 10 is also connected with luminescent device L anode.The replacement module 10
For initial voltage end Vint initial voltage to be write to luminescent device L anode.So, an image can be avoided
The image that the voltage next image frame that frame residues in luminescent device L anodes is shown impacts.If for example, not over weight
Put module 10 to reset luminescent device L anode, then in next image frame display image, on luminescent device L anodes
The voltage of residual can cause the driving current I for flowing through luminescent device LOLEDIncrease, so as to cause the brightness ratio of the sub-pix pre-
Phase brightness is big, can so reduce the contrast of display image.
Wherein, luminescent device L negative electrode connection second voltage end ELVSS.Wherein, luminescent device L can be luminous two
Pole pipe (Light Emitting Diode, LED) or Organic Light Emitting Diode (OLED).The utility model is not limited this.
In addition, writing module 30 connects data voltage end Data and drive module 20.The writing module 30 is used for number
Write according to voltage end Data data voltage Vdata into drive module 20.So that used caused by drive module 20
In the luminous driving current I of driving luminescent device LOLEDSize match with above-mentioned data voltage Vdata.
Compensating module 40 connects drive module 20.The compensating module 40 is used for the threshold voltage to DTFT in drive module
Vth is compensated.
Light emitting control module 50 connects LED control signal end EM, first voltage end ELVDD, drive module 20 and lighted
Device L anode.The light emitting control module is used under LED control signal end EM control, by drive module 20 in the first electricity
Pressure side ELVDD and second voltage end ELVSS and write-in are to caused by the presence of the data voltage Vdata of the drive module 20
Driving current IOLED, transmit to luminescent device L.Luminescent device L is used for according to driving current IOLEDLighted.
In summary, no matter the data voltage of previous image frame, DTFT in each sub-pix all by same state,
I.e. above-mentioned conducting state (ON-Bias) carries out data voltage write-in and threshold voltage compensation, thus can avoid being imitated by magnetic hysteresis
Should caused short-term image retention problem.
It should be noted that in the utility model embodiment, first voltage end ELVDD is used to export constant high level.
Second voltage end ELVSS is used to export constant low level, such as can be by second voltage end ELVSS connection earth terminals.And
And the relative size relation between the high and low voltage for only representing input here.
Based on this, as shown in Fig. 3 a or Fig. 3 b, writing module 30 includes the first transistor M1.Wherein, the first transistor
M1 grid connects the first gating signal end G1, the first pole connection data voltage end Data, the second pole and DTFT the first pole phase
Connection.
Compensating module 40 includes second transistor M2.Second transistor M2 grid connects the second gating signal end G2,
First pole connects DTFT grid, and the second pole is connected with DTFT the second pole.
Light emitting control module 50 includes third transistor M3 and the 4th transistor M4.Third transistor M3 grid connection
3rd gating signal end G3, the first pole connection first voltage end ELVDD, the second pole is connected with DTFT the first pole.
4th transistor M4 grid connects the 4th gating signal end G4, and the first pole connects DTFT the second pole, the second pole
It is connected with luminescent device L anode.
On this basis, it is extremely heavy that the grid that above-mentioned replacement module 10 is included as shown in Figure 3 a resets submodule 101 and first
Put submodule 102.
Wherein, the grid resets the grid that submodule 101 connects initial voltage end Vint and DTFT.The grid resets submodule
Block 101 is used for the grid that initial voltage end Vint initial voltage is write to DTFT.
First pole resets the first pole that submodule 102 connects tertiary voltage end V3 and DTFT.First pole resets submodule
102 are used to write tertiary voltage end V3 voltage to DTFT the first pole.
Or the replacement module 10 includes grid as shown in Figure 3 b and resets the pole of submodule 101 and second replacement submodule 103.
Wherein, the grid resets the connected mode of submodule 101 and acted on same as above.
In addition, the second pole resets the second pole that submodule 103 connects tertiary voltage end V3 and DTFT.Second pole resets son
Module 103 is used to write tertiary voltage end V3 voltage to DTFT the second pole.
Based on said structure, the set-up mode different below according to module 10 is reset, to the different structure that has of acquisition
Image element circuit is illustrated.
Embodiment one
In the present embodiment, the set-up mode of writing module 30, compensating module 40 and light emitting control module 50 is same as above,
Here is omitted.
On this basis, as shown in figure 4, the grid, which resets submodule 101, includes the 5th transistor M5.Wherein, the 5th is brilliant
Body pipe M5 grid connects the 5th gating signal end G5, and the first pole connects DTFT grid, the second pole and initial voltage end Vint
It is connected.
Based on this, by the above-mentioned data voltage end Data of tertiary voltage end V3 connections.Also, include in above-mentioned replacement module 10
In the case that first pole resets submodule 102, the writing module 30 is multiplexed with above-mentioned first pole and resets submodule 102.Now, should
First pole, which resets submodule 102, includes above-mentioned the first transistor M1.
In addition, when replacement module 10 is also connected with luminescent device L anode, the replacement module 10 also includes the 6th transistor
M6.6th transistor M6 grid connects the 6th gating signal end G6, the first pole connection luminescent device L anode, the second pole
It is connected with initial voltage end Vint.
Below in conjunction with the timing diagram of each signal end shown in Fig. 5 a, Fig. 6 a and Fig. 7 a, to the pixel shown in Fig. 4
Circuit, the course of work in a picture frame are described in detail.
Wherein, it is using the first transistor M1 as N-type transistor in embodiment one, remaining transistor is P-type transistor, and respectively
Individual transistor is exemplified by enhancement transistor.
In addition, as shown in figure 4, the first gating signal end G1 being connected with the first transistor M1 grid and the 3rd is brilliant
Body pipe M3 grid the 3rd gating signal end G3 being connected and the 4th gating signal end being connected with the 4th transistor M4
G4 receives the signal of LED control signal end EM outputs；The second gating signal end being connected with second transistor M2 grid
G2 and the 6th gating signal end G6 being connected with the 6th transistor M6 grid receives the letter of the first scanning signal end S1 outputs
Number；The 5th gating signal end G5 being connected with the 5th transistor M5 grid receives the letter of the second scanning signal end S2 outputs
Number.
Wherein, an above-mentioned picture frame includes reset phase P1, write-in compensated stage P2 and glow phase P3.
Specifically, in the reset phase P1 of a picture frame, as shown in Figure 5 a, S2=0, S1=1, EM=1, Data=
Vref；Wherein, " 0 " represents low level in the utility model embodiment, and " 1 " represents high level.
In the case, as shown in Figure 5 b, under the control of the second scanning signal end S2 output low level signals, the 5th is brilliant
Body pipe M5 is turned on, and the Vint initial voltages exported in initial voltage end are transmitted to DTFT grid by the 5th transistor M5.This
When DTFT grid voltages Vg=VB=Vint.
Further, since the first transistor M1 is N-type transistor, so in the high level letter of LED control signal end EM outputs
Number control under, the first transistor M1 conducting so that data voltage end Data output reference voltage Vref pass through first crystal
Pipe M1 is transmitted to DTFT source electrode.Now, DTFT source voltages Vs=VA=Vref.
Based on this, as shown in Figure 5 a, by adjusting Vref size, DTFT gate source voltage Vgs=Vg-Vs can make it that
=Vint-Vref ＜ Vth so that the DTFT (ON-Bias) in the conduction state.So, when the picture in each sub-pix
For plain circuit after above-mentioned reset phase P1, the DTFT in each sub-pix is in same ON-Bias states.
In addition, remaining transistor is in cut-off state.
In the write-in compensated stage P2 of a picture frame, as shown in Figure 6 a, S2=1, S1=0, EM=1, Data=Vdata.
In the case, as shown in Figure 6 b, under LED control signal end EM control, the first transistor M1 is held on
State, now, the data voltage Vdata of data voltage end Data outputs are transmitted to DTFT source by the first transistor M1
Pole.Now, the source voltage Vs=V of the DTFTA=Vdata, it is achieved thereby that the write-in of data voltage.
Based on this, it is low level that storage capacitance Cst, which can maintain node B, and now DTFT is turned on.On this basis,
Under scan signal end S1 control, second transistor M2 conductings.Now, DTFT grid voltage Vg and drain voltage Vd phases
Together, i.e. Vg=Vd.Now, Vgd=Vg-Vd=0>Vth, Vth are negative.Therefore the DTFT is in saturation state.
In the case, data voltage end Data data voltage Vdata passes through the first transistor M1, DTFT and second
Transistor M2 is charged to storage capacitance Cst, and storage capacitance Cst will be charged to the grid of the DTFT (i.e. B points) again,
Untill B point voltages reach Vdata+Vth.Because work as VBDuring=Vdata+Vth, DTFT gate source voltage Vgs=Vg-Vs=
Vdata+Vth-Vdata=Vth, now it is in cut-off state for DTFT.Wherein, for P-type transistor enhancement transistor and
Speech, cut-off condition is Vgs >=Vth, and Vth is negative value.So, DTFT threshold voltage vt h is locked to the grid of the DTFT
Pole, it is achieved thereby that being compensated to the threshold voltage vt h of the DTFT.
In addition, under the first scanning signal end S1 control, the 6th transistor M6 conductings, so as to by initial voltage end Vint
Initial voltage exported by the 6th transistor M6 to luminescent device L anode, by entering to lighting transistor L anode
Row is reset to improve the contrast of display picture.Remaining transistor is in cut-off state.
In the glow phase P3 of a picture frame, as shown in Figure 7a, S2=1, S1=1, EM=0, Data=0.
In the case, as shown in Figure 7b, under LED control signal end EM control, third transistor M3 and the 4th is brilliant
Body pipe M4 is turned on.Now, the voltage V of A pointsA=ELVDD.In the presence of storage capacitance Cst, the voltage of B points keeps VB=
Vdata+Vth.Now, the gate source voltage Vgs=Vg-Vs=V of the DTFTB-VA=(Vdata+Vth)-ELVDD=Vdata+
Vth-ELVDD ＜ Vth, Vth are negative value.Therefore DTFT conductings.In addition, remaining transistor is in cut-off state.
Based on this, the driving current I for flowing through above-mentioned luminescent device L is：
IOLED=K/2 × (Vgs-Vth)2
=K/2 × (Vdata+Vth-ELVDD-Vth)2
=K/2 × (Vdata-ELVDD)2。 (1)
Wherein, K is the current constant for being associated with DTFT, technological parameter and physical dimension with DTFT, such as electron transfer
Rate μ, the electric capacity C of unit areaox, breadth length ratio W/L etc. it is relevant.
In the prior art, the threshold voltage vt h drifts of the DTFT between different pixels unit, and cause each DTFT threshold
Threshold voltage Vth is not quite similar.From above formula (1), for driving luminescent device L to carry out luminous driving current IOLEDWith
DTFT threshold voltage vt h is unrelated, so as to eliminate influences of the DTFT threshold voltage vt h to luminescent device L luminosity, carries
The high homogeneity of luminescent device L brightness.
It should be noted that foregoing description is using the first transistor M1 as N-type transistor, remaining transistor is that p-type is brilliant
The explanation carried out exemplified by body pipe.When the first transistor M1 is P-type transistor, and remaining transistor is N-type transistor, control process
It can similarly obtain, but need to overturn part control signal.
Embodiment two
In the present embodiment, the set-up mode of writing module 30, compensating module 40 and light emitting control module 50 is same as above,
Here is omitted.
In addition, as shown in figure 8, the grid, which resets submodule 101, includes above-mentioned 5th transistor M5.5th transistor
Connected mode is identical with embodiment one.
Based on this, reset by tertiary voltage end V3 connection first voltage end ELVDD, and resetting module 10 including the first pole
In the case of submodule 102, a part for the light emitting control module 50 is multiplexed with the first pole and resets submodule 102.Now, this
One pole resets submodule 102 includes above-mentioned third transistor M3 as shown in Figure 8.
In addition, the image element circuit in the present embodiment can also include and the transistor M6 of one identical of embodiment the 6th.
Below in conjunction with the timing diagram of each signal end shown in Fig. 9 a, Figure 10 a and Figure 11 a, to the picture shown in Fig. 8
Plain circuit, the course of work in a picture frame are described in detail.
Wherein, it is using third transistor M3 as N-type transistor in embodiment two, remaining transistor is P-type transistor, and respectively
Individual transistor is exemplified by enhancement transistor.
In addition, as shown in figure 8, the first gating signal end G1 being connected with the first transistor M1 grid and the 3rd is brilliant
The 3rd gating signal end G3 that body pipe M3 grid is connected, the second gating signal being connected with second transistor M2 grid
End G2 receives the signal of the first scanning signal end S1 outputs；The 4th gating signal end G4 being connected with the 4th transistor M4 connects
Receive and dispatch the signal of optical control signal end EM outputs；The 5th gating signal end G5 that is connected with the 5th transistor M5 grid, with
The 6th gating signal end G6 that 6th transistor M6 grid is connected receives the signal of the second scanning signal end S2 outputs.
Specifically, in the reset phase P1 of a picture frame, as illustrated in fig. 9, S2=0, S1=1, EM=1, Data=0.
In the case, as shown in figure 9b, in the case where the second scanning signal end S2 exports low level control, the 5th transistor
M5 and the 6th transistor M6 conductings.Initial voltage end Vint initial voltage is transmitted to DTFT grid by the 5th transistor M5
Pole, and transmitted by the 6th transistor M6 to luminescent device L anode, with the grid to DTFT and luminescent device L sun respectively
Pole is reset.Now, DTFT grid voltages Vg=VB=Vint.
In addition, under the first scanning signal end S1 control, third transistor M3 conductings, DTFT source voltages Vs=VA=
ELVDD。
Based on this, DTFT gate source voltage Vgs=Vg-Vs=Vint-ELVDD ＜ Vth so that the DTFT is on shape
State (ON-Bias).In addition, remaining transistor is in cut-off state.
In the write-in compensated stage P2 of a picture frame, as shown in Figure 10 a, S2=1, S1=0, EM=1, Data=Vdata.
In the case, as shown in fig. lob, under the first scanning signal end S1 control, second transistor M2 and first
Transistor M1 is turned on.The data voltage Vdata of data voltage end Data outputs is transmitted to DTFT's by the first transistor M1
Source electrode.Now, the source voltage Vs=V of the DTFTA=Vdata, it is achieved thereby that the write-in of data voltage.
The second transistor M2 of conducting make it that DTFT grid voltage Vg is identical with drain voltage Vd, i.e. Vg=Vd.Herein
In the case of, data voltage end Data data voltage Vdata is by the first transistor M1, DTFT and second transistor M2 to this
DTFT grid (i.e. B points) is charged, untill B point voltages reach Vdata+Vth.So, DTFT threshold value electricity
Pressure Vth is locked to the grid of the DTFT, it is achieved thereby that being compensated to the threshold voltage vt h of the DTFT.In addition, remaining is brilliant
Body pipe ends.
In the glow phase P3 of a picture frame, as shown in fig. 11a, S2=1, S1=1, EM=0, Data=0.
In the case, as shown in figure 11b, under LED control signal end EM control, the 4th transistor M4 conductings,
Under first scanning signal end S1 control, third transistor M3 conductings.Now, the voltage V of A pointsA=ELVDD.The voltage of B points is protected
Hold VB=Vdata+Vth.Now, the gate source voltage Vgs=Vg-Vs=V of the DTFTB-VA=(Vdata+Vth)-ELVDD=
Vdata+Vth-ELVDD ＜ Vth, Vth are negative value.Therefore DTFT conductings.In addition, remaining transistor is in cut-off state.
Based on this, above-mentioned luminescent device L driving current I is flowed throughOLEDSame above-mentioned formula (1).It is luminous to thus be accordingly used in driving
Device L carries out luminous driving current IOLEDIt is unrelated with DTFT threshold voltage vt h.
It should be noted that foregoing description is using third transistor M3 as N-type transistor, remaining transistor is that p-type is brilliant
The explanation carried out exemplified by body pipe.When third transistor M3 is P-type transistor, and remaining transistor is N-type transistor, control process
It can similarly obtain, but need to overturn part control signal.
Embodiment three
In the present embodiment, the set-up mode of writing module 30, compensating module 40 and light emitting control module 50 is same as above,
Here is omitted.
In addition, as shown in figure 12, the grid resets the above-mentioned 5th transistor M5 of submodule 101.The company of 5th transistor
It is identical with embodiment one to connect mode.
Based on this, include the second pole by tertiary voltage end V3 connection reference voltage end Vref, and in above-mentioned replacement module 10
In the case of resetting submodule 102, second pole, which resets submodule 102, includes the 7th transistor M7, the 7th transistor M7 grid
Pole connects the 7th control signal end G7, and the first pole connection reference voltage end Vref, the second pole is connected with DTFT the second pole.
In addition, the image element circuit in the present embodiment can also include and the transistor M6 of one identical of embodiment the 6th.
Below in conjunction with the timing diagram of each signal end shown in Fig. 9 a, Figure 10 a and Figure 11 a, to shown in Figure 12
Image element circuit, the course of work in a picture frame are described in detail.
Wherein, it is using all transistors as P-type transistor in embodiment three, and each transistor is that enhancement transistor is
Example.
In addition, as shown in figure 12, the first gating signal end G1 being connected with the first transistor M1 grid and second is brilliant
Body pipe M2 grid the second gating signal end G2 being connected, the 6th gating signal being connected with the 6th transistor M6 grid
End G6 receives the signal of the first scanning signal end S1 outputs；The 3rd gating signal being connected with third transistor M3 grid
End G3, the 4th gating signal end G4 being connected with the 4th transistor M4 receive the signal of LED control signal end EM outputs；
The 5th gating signal end G5 that is connected with the 5th transistor M5 grid, it is connected with the grid of the 7th transistor M7
7th gating signal end G7 receives the signal of the second scanning signal end S2 outputs.
Specifically, in the reset phase P1 of a picture frame, as illustrated in fig. 9, S2=0, S1=1, EM=1, Data=0.
In the case, as depicted in fig. 13 a, in the case where the second scanning signal end S2 exports low level control, the 5th crystal
Pipe M5 and the 7th transistor M7 conductings.Initial voltage end Vint initial voltage is transmitted to DTFT grid by the 5th transistor M5
The grid voltage Vg=V of pole, now DTFTB=Vint.In addition, by the 7th transistor M7 of conducting, by reference voltage end
Vref voltage is transmitted to DTFT drain electrode.Because DTFT is in the conduction state, DTFT source voltages Vs=VA=Vref.
Based on this, DTFT gate source voltage Vgs=Vg-Vs=Vint-Vref ＜ Vth so that the DTFT is on shape
State (ON-Bias).In addition, remaining transistor is in cut-off state.
In the write-in compensated stage P2 of a picture frame, as shown in Figure 10 a, S2=1, S1=0, EM=1, Data=Vdata.
In the case, as illustrated in fig. 13b, under the first scanning signal end S1 control, second transistor M2, the first crystalline substance
Body pipe M1 and the 6th transistor M6 conductings.The data voltage Vdata of data voltage end Data outputs passes through the first transistor
M1 is transmitted to DTFT source electrode.Now, the source voltage Vs=V of the DTFTA=Vdata, it is achieved thereby that data voltage is write
Enter.
The second transistor M2 of conducting make it that DTFT grid voltage Vg is identical with drain voltage Vd, i.e. Vg=Vd.Herein
In the case of, data voltage end Data data voltage Vdata is by the first transistor M1, DTFT and second transistor M2 to this
DTFT grid (i.e. B points) is charged, untill B point voltages reach Vdata+Vth.So, DTFT threshold value electricity
Pressure Vth is locked to the grid of the DTFT, it is achieved thereby that being compensated to the threshold voltage vt h of the DTFT.
In addition, the 6th transistor M6 of conducting causes initial voltage end Vint initial voltage to transmit to luminescent device L's
Anode, the anode is reset.In addition, remaining transistor cutoff.
In the glow phase P3 of a picture frame, as shown in fig. 11a, S2=1, S1=1, EM=0, Data=0.
In the case, as shown in figure 13 c, under LED control signal end EM control, third transistor M3 and the 4th
Transistor M4 is turned on.Now, the voltage V of A pointsA=ELVDD.The voltage of B points keeps VB=Vdata+Vth.Now, the DTFT
Gate source voltage Vgs=Vg-Vs=VB-VA=(Vdata+Vth)-ELVDD=Vdata+Vth-ELVDD ＜ Vth, Vth are negative value.
Therefore DTFT conductings.In addition, remaining transistor is in cut-off state.
Based on this, above-mentioned luminescent device L driving current I is flowed throughOLEDSame above-mentioned formula (1).It is luminous to thus be accordingly used in driving
Device L carries out luminous driving current IOLEDIt is unrelated with DTFT threshold voltage vt h.
It should be noted that it is the explanation carried out exemplified by P-type transistor that foregoing description, which is all transistors,.When all
When transistor is P-type transistor, control process can similarly obtain, but need to overturn part control signal.
Example IV
In the present embodiment, the set-up mode of writing module 30, compensating module 40 and light emitting control module 50 is same as above,
Here is omitted.
In addition, as shown in figure 14, in the case where resetting module 10 and being also connected with luminescent device L anode, the replacement module
Grid in 10, which resets submodule 101, includes the 6th transistor M6；6th transistor M6 grid connects the 6th gating signal
G6 is held, the first pole connection luminescent device L anode, the second pole is connected with the initial voltage end Vint.
In addition, compensating module 40 is multiplexed with the part that grid resets submodule 101, the grid resets submodule 101 also
Including above-mentioned second transistor M2.Also, a part for light emitting control module 50 is multiplexed with one that grid resets submodule 101
Point, the grid, which resets submodule 101, also includes above-mentioned 4th transistor M4.
On this basis, by tertiary voltage end V3 connection data voltage end Data, and first is included in the replacement module 10
In the case that pole resets submodule 102, writing module 30 is multiplexed with above-mentioned first pole and resets submodule 102.In the case, should
First pole, which resets submodule 102, includes above-mentioned the first transistor M1.
Below in conjunction with the timing diagram of each signal end shown in Fig. 5 a, Fig. 6 a and Fig. 7 a, to the picture shown in Figure 14
Plain circuit, the course of work in a picture frame are described in detail.
Wherein, it is using the first transistor M1, second transistor M2 and the 4th transistor M4 as N-type crystal in example IV
Pipe, remaining transistor is P-type transistor, and each transistor is exemplified by enhancement transistor.
In addition, as shown in figure 14, the first gating signal end G1 being connected with the first transistor M1 grid and second is brilliant
The second gating signal end G2 that body pipe M2 grid is connected, the 3rd gating signal being connected with third transistor M3 grid
End G3 receives the signal of LED control signal end EM outputs；The 4th gating signal end G4 being connected with the 4th transistor M4 connects
Receive the signal of the first scanning signal end S1 outputs；The 6th gating signal end G6 being connected with the 6th transistor M6 receives second and swept
Retouch the signal of signal end S2 outputs.
Specifically, in the reset phase P1 of a picture frame, as shown in Figure 5 a, S2=0, S1=1, EM=1, Data=
Vref。
In the case, as shown in fig. 15 a, under LED control signal end EM control, the first transistor M1 and second
Transistor M2 is turned on；Under the first scanning signal end S1 control, the 4th transistor M4 conductings；The second scanning signal end S2's
Under control, the 6th transistor M6 conductings.Now, initial voltage end Vint initial voltage passes through the 6th transistor M6, the 4th crystalline substance
Body pipe M4 is transmitted to DTFT drain electrode, and is transmitted by second transistor M2 to DTFT grid.Now the DTFT grids, drain electrode
Voltage Vg=Vd=VB=Vint, and luminescent device L anode is reset.
In addition, pass through the first transistor M1 of conducting DTFT source voltages Vs=VA=Vref.
Based on this, DTFT gate source voltage Vgs=Vg-Vs=Vint-Vref ＜ Vth so that the DTFT is on shape
State (ON-Bias).In addition, remaining transistor is in cut-off state.
In the write-in compensated stage P2 of a picture frame, as shown in Figure 6 a, S2=1, S1=0, EM=1, Data=Vdata.
In the case, as illustrated in fig. 15b, under LED control signal end EM control, the first transistor M1 and second
Transistor M2 is tended to remain on.The data voltage Vdata of data voltage end Data outputs is transmitted by the first transistor M1
To DTFT source electrode.Now, the source voltage Vs=V of the DTFTA=Vdata, it is achieved thereby that the write-in of data voltage.
The second transistor M2 of conducting make it that DTFT grid voltage Vg is identical with drain voltage Vd, i.e. Vg=Vd.Herein
In the case of, data voltage end Data data voltage Vdata is by the first transistor M1, DTFT and second transistor M2 to this
DTFT grid (i.e. B points) is charged, untill B point voltages reach Vdata+Vth.So, DTFT threshold value electricity
Pressure Vth is locked to the grid of the DTFT, it is achieved thereby that being compensated to the threshold voltage vt h of the DTFT.
In the glow phase P3 of a picture frame, as shown in Figure 7a, S2=1, S1=1, EM=0, Data=0.
In the case, as shown in fig. 15 c, under LED control signal end EM control, third transistor M3 conductings；
Under first scanning signal end S1 control, the 4th transistor M4 conductings.Now, the voltage V of A pointsA=ELVDD.The voltage of B points is protected
Hold VB=Vdata+Vth.Now, the gate source voltage Vgs=Vg-Vs=V of the DTFTB-VA=(Vdata+Vth)-ELVDD=
Vdata+Vth-ELVDD ＜ Vth, Vth are negative value.Therefore DTFT conductings.In addition, remaining transistor is in cut-off state.
Based on this, above-mentioned luminescent device L driving current I is flowed throughOLEDSame above-mentioned formula (1).It is luminous to thus be accordingly used in driving
Device L carries out luminous driving current IOLEDIt is unrelated with DTFT threshold voltage vt h.
It should be noted that foregoing description is with the first transistor M1, second transistor M2 and the 4th transistor M4
For N-type transistor, remaining transistor is the explanation carried out exemplified by P-type transistor.When the first transistor M1, second transistor M2 with
And the 4th transistor M4 be P-type transistor, when remaining transistor is N-type transistor, control process can similarly obtain, but need pair
Part control signal is overturn.
Embodiment five
In the present embodiment, the set-up mode of writing module 30, compensating module 40 and light emitting control module 50 is same as above,
Here is omitted.
In addition, as shown in figure 16, grid in module 10 is reset reset submodule 101 include the 6th transistor M6 and
The second transistor that compensating module 40 is multiplexed and the 4th transistor M4 with the multiplexing of light emitting control module 50.Wherein, the 6th is brilliant
Body pipe M6, second transistor and the 4th transistor M4 set-up mode are identical with example IV.
On this basis, by tertiary voltage end V3 connection reference voltage end Vref, and the first pole is included resetting module 10
In the case of resetting submodule 102, first pole, which resets submodule 102, includes the 7th transistor M7, the 7th transistor M7's
Grid connects the 7th control signal end G7, and the first pole connection reference voltage end Vref, the second pole is connected with DTFT the first pole.
Below in conjunction with the timing diagram of each signal end shown in Fig. 9 a, Figure 10 a and Figure 11 a, the picture shown Figure 16
Plain circuit, the course of work in a picture frame are described in detail.
Wherein, it is using second transistor M2 and the 4th transistor M4 as N-type transistor in embodiment five, remaining transistor is
P-type transistor, and each transistor is exemplified by enhancement transistor.
In addition, as shown in figure 16, the first gating signal end G1 being connected with the first transistor M1 grid and the 4th is brilliant
The 4th gating signal end G4 that body pipe M4 is connected receives the signal of the first scanning signal end S1 outputs；With second transistor M2
Grid the second gating signal end G2, the 3rd gating signal end G3 that is connected with third transistor M3 grid that are connected it is equal
Receive the signal of LED control signal end EM outputs；The 6th gating signal end G6 being connected with the 6th transistor M6 and the 7th
The 7th gating signal end G7 that transistor M7 is connected receives the signal of the second scanning signal end S2 outputs.
Specifically, in the reset phase P1 of a picture frame, as illustrated in fig. 9, S2=0, S1=1, EM=1, Data=0.
In the case, as illustrated in fig 17 a, under LED control signal end EM control, second transistor M2 conductings；
Under first scanning signal end S1 control, the 4th transistor M4 conductings；Under the second scanning signal end S2 control, the 6th crystal
Pipe M6 and the 7th transistor M7 conductings.
Now, initial voltage end Vint initial voltage is transmitted to DTFT by the 6th transistor M6, the 4th transistor M4
Drain electrode, and transmitted by second transistor M2 to DTFT grid.Now the DTFT grids, drain voltage Vg=Vd=VB=
Vint, and luminescent device L anode is reset.
In addition, by the 7th transistor M7 of conducting, the source electrode of reference voltage end Vref voltage output to DTFT makes
Obtain DTFT source voltages Vs=VA=Vref.
Based on this, DTFT gate source voltage Vgs=Vg-Vs=Vint-Vref ＜ Vth so that the DTFT is on shape
State (ON-Bias).In addition, remaining transistor is in cut-off state.
In the write-in compensated stage P2 of a picture frame, as shown in Figure 10 a, S2=1, S1=0, EM=1, Data=Vdata.
In the case, as illustrated in fig. 17b, under LED control signal end EM control, second transistor M2 keeps leading
Logical state.Under the first scanning signal end S1 control, the first transistor M1 conductings, the data electricity of data voltage end Data outputs
Pressure Vdata is transmitted to DTFT source electrode by the first transistor M1.Now, the source voltage Vs=V of the DTFTA=Vdata,
It is achieved thereby that the write-in of data voltage.
The second transistor M2 of conducting make it that DTFT grid voltage Vg is identical with drain voltage Vd, i.e. Vg=Vd.Herein
In the case of, data voltage end Data data voltage Vdata is by the first transistor M1, DTFT and second transistor M2 to this
DTFT grid (i.e. B points) is charged, untill B point voltages reach Vdata+Vth.So, DTFT threshold value electricity
Pressure Vth is locked to the grid of the DTFT, it is achieved thereby that being compensated to the threshold voltage vt h of the DTFT.
In the glow phase P3 of a picture frame, as shown in fig. 11a, S2=1, S1=1, EM=0, Data=0.
In the case, as shown in fig. 17 c, under LED control signal end EM control, third transistor M3 conductings；
Under first scanning signal end S1 control, the 4th transistor M4 conductings.Now, the voltage V of A pointsA=ELVDD.The voltage of B points is protected
Hold VB=Vdata+Vth.Now, the gate source voltage Vgs=Vg-Vs=V of the DTFTB-VA=(Vdata+Vth)-ELVDD=
Vdata+Vth-ELVDD ＜ Vth, Vth are negative value.Therefore DTFT conductings.In addition, remaining transistor is in cut-off state.
Based on this, above-mentioned luminescent device L driving current I is flowed throughOLEDSame above-mentioned formula (1).It is luminous to thus be accordingly used in driving
Device L carries out luminous driving current IOLEDIt is unrelated with DTFT threshold voltage vt h.
It should be noted that foregoing description is using second transistor M2 and the 4th transistor M4 as N-type transistor, remaining
Transistor is the explanation that carries out exemplified by P-type transistor.When second transistor M2 and the 4th transistor M4 are P-type transistor, remaining
When transistor is N-type transistor, control process can similarly obtain, but need to overturn part control signal.
The utility model embodiment, which provides a kind of display device, includes any one image element circuit as described above.
It should be noted that the display device that the utility model embodiment is provided can be include light-emitting diode display or
The display device with electric current driving luminescent device including OLED display.The display device can be TV, mobile phone, flat board
Computer etc..
On this basis, above-mentioned display device includes display panel, is provided with the display panel and is arranged in matrix form
Sub-pix, above-mentioned image element circuit is arranged in each sub-pix.
In the case, when the grid of portion of transistor in above-mentioned image element circuit connects the first scanning signal end S1 or second
During scanning signal end, in addition to the first row sub-pix, in next line sub-pix the second scanning signal end S2 of image element circuit with
The first scanning signal end S1 of image element circuit is connected in lastrow sub-pix.So, the signal of adjacent rows sub-pix
Partial common is held, so as to reach the purpose for reducing signal end quantity so that wire structures are simpler.
The utility model embodiment provides a kind of method for being used to drive any one image element circuit as described above, a figure
As methods described includes in frame：
First, it is used in reset phase P1, replacement module 10 as shown in Figure 2 by initial voltage end Vint initial voltage
The grid of the DTFT into drive module 20 is write, and tertiary voltage end V3 voltage is write to DTFT the first pole.The DTFT
It is in the conduction state in reset phase P1.
Then, write-in compensated stage P2, writing module 30 by data voltage end Data data voltage Vdata write to
In drive module 20.
Compensating module 40 is used to compensate the threshold voltage of DTFT in drive module 20.
Finally, in glow phase P3, drive module 20 is in first voltage end ELVDD and second voltage end ELVSS and writes
Caused driving current I in the presence of entering to the data voltage Vdata of the drive module 20OLED.The light emitting control module 50 exists
By driving current I under LED control signal end EM controlOLEDTransmit to luminescent device L.Luminescent device L is used for according to driving electricity
Flow IOLEDLighted.
It should be noted that in above-mentioned image element circuit during the structure difference of modules, specific driving method is as described above
Described in embodiment one to embodiment five, here is omitted.In addition, the driving method of above-mentioned image element circuit has and foregoing implementation
Example identical technique effect, here is omitted.
It is described above, only specific embodiment of the present utility model, but the scope of protection of the utility model is not limited to
In this, any one skilled in the art can readily occur in change in the technical scope that the utility model discloses
Or replace, it should all cover within the scope of protection of the utility model.Therefore, the scope of protection of the utility model should be with the power
The protection domain that profit requires is defined.
Claims (12)
1. a kind of image element circuit, it is characterised in that including resetting module, drive module, writing module, compensating module, luminous control
Molding block and luminescent device；The drive module includes driving transistor, and the first pole of the driving transistor is write with described
Enter module to be connected；
The replacement module connection initial voltage end, tertiary voltage end, the drive module；The replacement module is used for by described in
The initial voltage at initial voltage end writes the grid of driving transistor in the drive module, and by the electricity at the tertiary voltage end
Pressure is write to the first pole of the driving transistor；The driving transistor is in the conduction state in reset phase；
Said write module connects data voltage end and the drive module；Said write module is used for the data voltage
The data voltage at end is write into the drive module；
The compensating module connects the drive module；The compensating module is used for driving transistor in the drive module
Threshold voltage compensates；
Light emitting control module connection LED control signal end, first voltage end, the drive module and the photophore
The anode of part；The negative electrode connection second voltage end of the luminescent device；The light emitting control module is used in the light emitting control
Under the control of signal end, the drive module at the first voltage end and the second voltage end and is write to the driving
Caused driving current in the presence of the data voltage of module, transmit to the luminescent device；The luminescent device is used for basis
The driving current is lighted.
2. image element circuit according to claim 1, it is characterised in that the replacement module is also connected with the luminescent device
Anode；The replacement module is used to write the initial voltage at the initial voltage end to the anode of the luminescent device.
3. image element circuit according to claim 1 or 2, it is characterised in that
Said write module includes the first transistor, and the grid of the first transistor connects the first gating signal end, the first pole
The data voltage end is connected, the second pole is connected with the first pole of the driving transistor；
The compensating module includes second transistor, and the grid of the second transistor connects the second gating signal end, the first pole
The grid of the driving transistor is connected, the second pole is connected with the second pole of the driving transistor；
The light emitting control module includes third transistor and the 4th transistor；The choosing of grid connection the 3rd of the third transistor
Messenger end, the first pole connect the first voltage end, and the second pole is connected with the first pole of the driving transistor；Described
The grid of four transistors connects the 4th gating signal end, and the first pole connects the second pole of the driving transistor, the second pole and institute
The anode for stating luminescent device is connected；
The drive module also includes storage capacitance；One end of the storage capacitance connects the first voltage end, the other end with
The grid of the driving transistor is connected.
4. image element circuit according to claim 3, it is characterised in that it is described replacement module include grid reset submodule and
First pole resets submodule；
The grid resets the grid that submodule connects the initial voltage end and the driving transistor；The grid resets son
Module is used for the grid that the initial voltage at the initial voltage end is write to the driving transistor；
First pole resets submodule and connects the tertiary voltage end and the first pole of the driving transistor；First pole
Submodule is reset to be used to write the voltage at the tertiary voltage end to the first pole of the driving transistor；
Or the replacement module includes the grid and resets submodule and second pole replacement submodule；Described second is extremely heavy
Put submodule and connect the tertiary voltage end and the second pole of the driving transistor；The second pole replacement submodule is used for will
The voltage at the tertiary voltage end is write to the second pole of the driving transistor.
5. image element circuit according to claim 4, it is characterised in that
The grid, which resets submodule, includes the 5th transistor, and the grid of the 5th transistor connects the 5th gating signal end,
First pole connects the grid of the driving transistor, and the second pole is connected with the initial voltage end.
6. image element circuit according to claim 4, it is characterised in that be also connected with the sun of the luminescent device in replacement module
In the case of pole, the grid, which resets submodule, includes the 6th transistor；The gating of grid connection the 6th of 6th transistor
Signal end, the first pole connect the anode of the luminescent device, and the second pole is connected with the initial voltage end；
The compensating module is multiplexed with the part that the grid resets submodule, and the grid resets submodule also including described
Second transistor；
A part for the light emitting control module is multiplexed with the part that the grid resets submodule, and the grid resets submodule
Block also includes the 4th transistor.
7. the image element circuit according to claim 5 or 6, it is characterised in that the tertiary voltage end connects the data electricity
Pressure side, include in the replacement module in the case that first pole resets submodule, said write module reuse is described the
One pole resets submodule；First pole, which resets submodule, includes the first transistor.
8. image element circuit according to claim 5, it is characterised in that the tertiary voltage end connects the first voltage
End, in the case where the replacement module includes first pole replacement submodule, a part for the light emitting control module is answered
Submodule is reset with for first pole；First pole, which resets submodule, includes the third transistor.
9. image element circuit according to claim 5, it is characterised in that the tertiary voltage end connects reference voltage end,
In the case that the replacement module includes second pole replacement submodule, second pole, which resets submodule, includes the 7th crystal
Pipe；The grid of 7th transistor connects the 7th control signal end, and the first pole connects the reference voltage end, the second pole and institute
The second pole for stating driving transistor is connected.
10. image element circuit according to claim 6, it is characterised in that the tertiary voltage end connects reference voltage end,
In the case that the replacement module includes first pole replacement submodule, first pole, which resets submodule, includes the 7th crystal
Pipe；The grid of 7th transistor connects the 7th control signal end, and the first pole connects the reference voltage end, the second pole and institute
The first pole for stating driving transistor is connected.
11. image element circuit according to claim 2, it is characterised in that be also connected with the luminescent device resetting module
In the case of anode, the replacement module also includes the 6th transistor；The gating letter of grid connection the 6th of 6th transistor
Number end, the first pole connect the anode of the luminescent device, and the second pole is connected with the initial voltage end.
12. a kind of display device, it is characterised in that including the image element circuit as described in claim any one of 1-11.
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| CN107358918A (en) * | 2017-08-25 | 2017-11-17 | 京东方科技集团股份有限公司 | A kind of image element circuit and its driving method, display device |
| CN108735160A (en) * | 2018-04-08 | 2018-11-02 | 信利（惠州）智能显示有限公司 | Organic light emitting display driving device and organic light emitting display |
| CN109584795A (en) * | 2019-01-29 | 2019-04-05 | 京东方科技集团股份有限公司 | Pixel-driving circuit, image element driving method and display device |
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| CN107358918A (en) * | 2017-08-25 | 2017-11-17 | 京东方科技集团股份有限公司 | A kind of image element circuit and its driving method, display device |
| WO2019037543A1 (en) * | 2017-08-25 | 2019-02-28 | 京东方科技集团股份有限公司 | Pixel circuit and driving method thereof, and display device |
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| CN108735160A (en) * | 2018-04-08 | 2018-11-02 | 信利（惠州）智能显示有限公司 | Organic light emitting display driving device and organic light emitting display |
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