CN207037643U - A kind of device that multiple I2C interface standard group equipment are supported based on SoC - Google Patents
A kind of device that multiple I2C interface standard group equipment are supported based on SoC Download PDFInfo
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Abstract
The utility model discloses a kind of device that multiple SPI interface standard groups are supported based on SoC, including complete programmable SoC, PS processors inside complete programmable SoC, PL field programmable gate arrays inside complete programmable SoC, AXI EBIs, EMIO data-interfaces, one AXI protocol parsing module, one I2C bus control module, PS processors carry an I2C controller, communicated between PS processors and PL field programmable gate arrays by AXI EBIs, pass through EMIO data interface communications between PS processors and PL field programmable gate arrays, SCL_O is set on EMIO data-interfaces, SCL_T, SCL_I, SDA_O, SDA_T, SDA_I signal ports.The utility model is solved the problems, such as based on SoC as I2C controller deficiencies in the circuit single plate of system control and algorithm process chip.
Description
Technical field
The present invention relates to integrated circuit control field, more particularly to a kind of SoC that is based on to support multiple I2C interface standard groups to set
Standby apparatus and method.
Background technology
Entirely programmable SoC (System-on-a-Chip) be integrated with arm processor (Advanced RISC Machines,
PS, Processing System) software programmable and field programmable gate array (PL, Programmable Logic)
Hardware programmable.Communication mode has AXI between PS processors and PL field programmable gate arrays inside programmable SoC entirely
(Advanced extensible Interface) and EMIO (Extendable multiplexed I/O).
AXI (Advanced extensible Interface) is a kind of bus protocol, and the agreement is that ARM companies propose
AMBA (Advanced Microcontroller Bus Architecture) 3.0 agreements in most important part, be a kind of
Towards high-performance, high bandwidth, low latency bus on chip.Its address/control and data phase are separation, support not lining up
Data transfer, while in burst transfer, it is only necessary to first address, while the read-write data channel that separates and support
Outstanding transmission accesses and out of order access, and is more prone to carry out timing closure.AXI is a new high property in AMBA
Can agreement.AXI technologies enrich existing AMBA standard contents, meet very-high performance and the design of complicated on-chip system (SoC)
Demand.AXI in complete programmable SoC mainly by read/write address bus (RW_ADDR), read data bus (RD_DATA), write number
According to bus (WR_DATA), handshake composition (Handshake).
MDAS (Multiservice Distributed Access System Solution) is a kind of multi-service distribution
System, Duo Jia operators, multi-standard, multicarrier, and integrated wlan system can be supported, a step, which solves voice and data service, to be needed
Ask, compared with traditional analog compartment system, be provided simultaneously with mixed networking, delay compensation, automatic carrier track, up bottom make an uproar it is low
Feature.
MDAS multi-services compartment system is made up of access unit (MAU), expanding element (MEU) and far-end unit (MRU).
Digitization system subdivision in MDAS has the double systems of cdma system, GSM/DCS/WCDMA double-standards system, GSM/DCS/TD-SDMA
Formula system, while 2G, 3G mobile communication service are provided, wlan system is integrated, meet that the high-rate wireless data of user pass
Defeated demand.
The system group network ability of MDAS multi-service compartment systems, 1 MAU access unit can 4 MEU expanding elements of band, 1
MEU expanding elements can 8 MRU far-end units of band, 1 MAU access unit can be with 4*8*8=256 platform MRU far-end units.MAU connects
Enter unit, MEU expanding elements are connected with before MRU far-end units by optical module with optical fiber.
The content of the invention
For problems of the prior art, the purpose of the present invention is using at the PS inside complete programmable SoC chip
The software programmable of device and the hardware programmable of PL field programmable gate arrays are managed, is realized a kind of multiple based on SoC supports
The apparatus and method of I2C interface standard group equipment.
In order to realize foregoing invention purpose, the technical solution adopted by the present invention is：One kind supports multiple I2C to connect based on SoC
The device of mouth standard group equipment, it is characterised in that：Including the PS processors inside complete programmable SoC, complete programmable SoC, Quan Ke
Program SoC inside PL field programmable gate arrays, AXI EBIs, EMIO data-interfaces, an AXI protocol parsing module,
One I2C bus control module, the PS processors carry an I2C controller, can be compiled in the PS processors and PL scenes
Communicated between journey gate array by the AXI EBIs, at the same the PS processors and PL field programmable gate arrays it
Between by the EMIO data interface communications, SCL_O, SCL_T, SCL_I, SDA_O, SDA_ are set on the EMIO data-interfaces
T, SDA_I signal port, be additionally provided with inside the PL field programmable gate arrays a described AXI protocol parsing module and
One I2C bus control module.
The I2C buses of the I2C controllers of the PS processors are made up of following 6 signals：
1) SCL_I is that the serial clock of I2C data/address bus inputs the triple gate from external equipment；
2) SCL_O is that the serial clock of I2C data/address bus is output to the triple gate of external equipment；
3) SCL_T is that the serial clock output of I2C data/address bus enables the triple gate of external equipment；
4) SDA_I is the serial date transfer of I2C data/address bus from the triple gate of external equipment；
5) SDA_O is that the serial data of I2C data/address bus is output to the triple gate of external equipment；
6) SDA_T is that the serial data output of I2C data/address bus enables the triple gate of external equipment.
The data bit width of the read/write address bus (RW_ADDR) of the AXI EBIs is 32bit；Read data bus
(RD_DATA) data bit width is that 32bit, the data bit width of write data bus (WR_DATA) are 32bit；Parsed in AXI protocol
A control register CH_SEL is defined to I2C bus control modules in module, this register address is 0x00000080, number
It is 3bit (CH_SEL [2 according to bit wide:0]), CH_SEL controls the channel selecting of I2C buses.
The CH_SEL signal deciding PS processing that the I2C bus control modules pass through AXI bus marcos according to PS processors
I2C buses between device and PL field programmable gate arrays are connected to one in the I2C buses of multiple connection external equipments；
Two signals are defined inside I2C bus control modules, are I2C_SCL, I2C_SDA respectively；The PL field programmable gate arrays
The I2C bus signals connected with external equipment are all bidirectional data ports.
The present invention discloses a kind of method that multiple I2C interface standard group equipment are supported based on SoC, step includes：
Step 1: the system software of PS processors is according to demand, determine the I2C controllers of current PS processors with it is multiple outer
One in portion's I2C interface standard group equipment is communicated；
Step 2: PS processors control CH_SEL concrete numerical value by AXI EBIs and AXI protocol parsing module,
Select an exterior I 2C interface standard group equipment；
Step 3: numerical value of the I2C bus control modules according to CH_SEL control signals, controls I2C inside PS processors
The I2C buses of device are connected to the I2C buses of corresponding external equipment；
Step 4: one in the I2C controllers and exterior I 2C interface standard group equipment of PS processors is communicated.
The implementation of AXI protocol parsing module：
Step 1, the handshake for waiting PS processors to be sended over by AXI EBIs；
Whether step 2, the data for judging address bus are 0x00000080；
If step 3, the data of address bus are 0x00000080, continue to judge it is currently to write behaviour according to handshake
Work or read operation；
Step 4, if the data of write operation and RW_ADDR address bus are 0x00000080, the low of WR_DATA
3bit data are assigned to CH_SEL；
Step 5, if the data of read operation and RW_ADDR address bus are 0x00000080, CH_SEL is assigned to
RD_DATA low 3bit, high 29bit data are entered as 0.
The implementation of I2C bus control unit modules：
Step 1, SCL_O and SCL_T take or are assigned to I2C_SCL, SDA_O and SDA_T and take or be assigned to I2C_SDA；
Step 2, when PS processors I2C controllers as master controller need operate external equipment when, CH_SEL control
One in the I2C controllers of signal deciding PS processors and outside 8 I2C interface standard group equipment is communicated；
Step 3, when the I2C buses of the I2C controllers of PS processors are in output state, external equipment I2C buses and
The one-to-one relationship of I2C controller bus signals inside PS processors；
Step 4, when the I2C controller buses signal of PS processors is in input state, external equipment I2C buses and PS
The one-to-one relationship of I2C controller bus signals inside processor.
Beneficial effect：
1：The present invention utilizes the I2C controller and may be programmed entirely inside SoC that PS processors carry in complete programmable SoC
PL field programmable gate arrays solve system need control 8 I2C addresses identical external equipments demand.If without this
Invention, just at least needs 6 I2C control chips to meet system design considerations, saves hardware purchase cost in circuit.
2：Because this design is all completed inside complete programmable SoC, simplify and may be programmed the outer of SoC on circuit board entirely
Portion's circuit, the reduction PCB circuit board number of plies can be entered, further reduce PCB production costs.
3：Because the programmable peripheral circuits of SoC on circuit boards further simplify entirely, it is possible to reduce circuit board
Debug time, lift efficiency of research and development.
Brief description of the drawings
Fig. 1 is the apparatus structure schematic diagram that multiple I2C interface standard group equipment are supported based on SoC of the embodiment of the present invention.
Fig. 2 is the workflow diagram of the AXI protocol parsing module of the embodiment of the present invention.
Embodiment
For the ease of the understanding of those skilled in the art, the present invention is made further with reference to embodiment and accompanying drawing
It is bright.
The present embodiment is that solve based on SoC as I2C controllers in the circuit single plate of system control and algorithm process chip
The problem of insufficient.The I2C controller and complete programmable SoC that the present embodiment is carried using PS processors in complete programmable SoC
Internal PL field programmable gate arrays, which solve system, to be needed to control the demand of 8 I2C addresses identical external equipments.
The device that multiple SPI interface standard group equipment are supported based on SoC of the present embodiment, including entirely at programmable SoC, PS
Manage device, PL field programmable gate arrays, AXI EBIs, EMIO data-interfaces, an AXI protocol parsing module, an I2C
Bus control module, the full PS processors that may be programmed inside SoC carry an I2C controller, described complete programmable
The PL field programmable gate arrays inside SoC, pass through institute between the PS processors and PL field programmable gate arrays
The communication of AXI EBIs is stated, while passes through the EMIO data between the PS processors and PL field programmable gate arrays
Interface communication, described that SCL_O, SCL_T, SCL_I be set on EMIO data-interfaces, SDA_O, SDA_T, SDA_I signal ports,
Described an AXI protocol parsing module and an I2C bus marco are additionally provided with inside the PL field programmable gate arrays
Module.
PS processors inside complete programmable SoC support two independent I2C controllers, and the two I2C controllers can be with
Actively (Master) and passive (slave) two kinds of mode of operations are operated in, it can support the operating clock rate of I2C buses most
Height arrives 400Kb/s.The I2C buses of the I2C controllers of PS processors are made up of following 6 signals inside complete programmable SoC：
1：SCL_I is that the serial clock of I2C data/address bus inputs the triple gate from external equipment；
2:SCL_O is that the serial clock of I2C data/address bus is output to the triple gate of external equipment；
3:SCL_T is that the serial clock output of I2C data/address bus enables the triple gate of external equipment；
4:SDA_I is the serial date transfer of I2C data/address bus from the triple gate of external equipment；
5:SDA_O is that the serial data of I2C data/address bus is output to the triple gate of external equipment；
6:SDA_T is that the serial data output of I2C data/address bus enables the triple gate of external equipment.
The I2C buses of I2C controllers pass through PS processors and the EMIO of PL field programmable gate arrays inside PS processors
Interface is connected to PL field programmable gate array internal programmable logics, then again by PL field programmable gate arrays inside
FPGA is connected to field programmable gate array FPGA common I/O port, and finally programmable gate displays the general of FPGA at the scene
Logical I/O port connects with the I2C controlling bus interfaces of external equipment.
Controlled at one using may be programmed SoC entirely as system in the circuit single plate with algorithm process, if in circuit single plate
Based on the same equipment of I2C interface standard group more than 2, and the I2C controlling bus address of this same equipment be it is fixed,
Thus need more than 2 I2C controllers individually to control with these external equipments respectively to be connected, because if hanging over an I2C
In bus, the address between equipment will conflict, it is impossible to normal work.
Such as need 8 SFP (Small in the MEU expanding elements circuit single plate design of MADS multi-service compartment systems
Form-factor Pluggable) optical module bi-directional transceiver, the I2C bus address of optical module bi-directional transceiver is all fixed
A0h and A2h, if this 8 optical module bi-directional transceivers all hang over device address in an I2C controlling bus and can conflicted, because
This just needs 8 independent I2C controllers on MEU veneers.
As shown in figure 1, it is the apparatus structure signal that multiple I2C interface standard group equipment are supported based on SoC of the present embodiment
Figure.
The data bit width of the read/write address bus (RW_ADDR) of AXI buses is 32bit；Read data bus (RD_DATA)
Data bit width is that 32bit, the data bit width of write data bus (WR_DATA) are 32bit.
A control register CH_SEL is defined to I2C bus control modules in AXI protocol parsing module, this deposit
Device address is 0x00000080, and data bit width is 3bit (CH_SEL [2:0]), CH_SEL controls the channel selecting of I2C buses.
The implementation of AXI protocol parsing module is as follows：
1：The handshake for waiting PS processors to be sended over by AXI EBIs,
2：Whether the data for judging address bus are 0x00000080,
3：If the data of address bus are 0x00000080, continue according to handshake judge be currently write operation also
It is read operation,
4：If the data of write operation and RW_ADDR address bus are 0x00000080, WR_DATA low 3bit numbers
According to being assigned to CH_SEL；
5:If the data of read operation and RW_ADDR address bus are 0x00000080, CH_SEL is assigned to RD_
DATA low 3bit, high 29bit data are entered as 0.
The workflow of AXI protocol parsing module is as shown in Figure 2.
I2C bus control modules according to PS processors by the CH_SEL signal deciding PS processors of AXI bus marcos and
I2C buses between PL field programmable gate arrays are connected to one in the I2C buses of 8 connection external equipments.It is total in I2C
Line traffic control inside modules define two signals, are I2C_SCL, I2C_SDA respectively.PL field programmable gate arrays and external equipment
I2C bus signals (SCL_0, SDA_0, SCL_1, SDA_1, SCL_2, SDA_2, SCL_3, SDA_3, SCL_4, the SDA_ of connection
4, SCL_5, SDA_5, SCL_6, SDA_6, SCL_7, SDA_7) all it is bidirectional data port.
The workflow implementation of I2C bus control unit modules is as follows：
1：SCL_O and SCL_T takes or is assigned to I2C_SCL, SDA_O and SDA_T and takes or be assigned to I2C_SDA；
2：When the I2C controllers of PS processors need to operate external equipment as master controller, CH_SEL control signals
Determine that one in the I2C controllers and outside 8 I2C interface standard group equipment of PS processors is communicated.
3：When the I2C buses of the I2C controllers of PS processors are in output state, at external equipment I2C buses and PS
The corresponding relation for managing I2C controller bus signals inside device is as follows：
If CH_SEL==0 and I2C_SCL==0, SCL_0 output 0, otherwise SCL_0 exports high resistant；
If CH_SEL==0 and I2C_SDA==0, SDA_0 output 0, otherwise SDA_0 exports high resistant；
If CH_SEL==1 and I2C_SCL==0, SCL_1 output 0, otherwise SCL_1 exports high resistant；
If CH_SEL==1 and I2C_SDA==0, SDA_1 output 0, otherwise SDA_1 exports high resistant；
If CH_SEL==2 and I2C_SCL==0, SCL_2 output 0, otherwise SCL_2 exports high resistant；
If CH_SEL==2 and I2C_SDA==0, SDA_2 output 0, otherwise SDA_2 exports high resistant；
If CH_SEL==3 and I2C_SCL==0, SCL_3 output 0, otherwise SCL_3 exports high resistant；
If CH_SEL==3 and I2C_SDA==0, SDA_3 output 0, otherwise SDA_3 exports high resistant；
If CH_SEL==4 and I2C_SCL==0, SCL_4 output 0, otherwise SCL_4 exports high resistant；
If CH_SEL==4 and I2C_SDA==0, SDA_4 output 0, otherwise SDA_4 exports high resistant；
If CH_SEL==5 and I2C_SCL==0, SCL_5 output 0, otherwise SCL_5 exports high resistant；
If CH_SEL==5 and I2C_SDA==0, SDA_5 output 0, otherwise SDA_5 exports high resistant；
If CH_SEL==6 and I2C_SCL==0, SCL_6 output 0, otherwise SCL_6 exports high resistant；
If CH_SEL==6 and I2C_SDA==0, SDA_6 output 0, otherwise SDA_6 exports high resistant；
If CH_SEL==7 and I2C_SCL==0, SCL_7 output 0, otherwise SCL_7 exports high resistant；
If CH_SEL==7 and I2C_SDA==0, SDA_7 output 0, otherwise SDA_7 exports high resistant；
4：When the I2C controller buses signal of PS processors is in input state, external equipment I2C buses and PS processing
The corresponding relation of I2C controller bus signals is as follows inside device：
If CH_SEL==0, SCL_0 are assigned to SCL_I, SDA_0 is assigned to SDA_I；
If CH_SEL==1, SCL_1 are assigned to SCL_I, SDA_1 is assigned to SDA_I；
If CH_SEL==2, SCL_2 are assigned to SCL_I, SDA_2 is assigned to SDA_I；
If CH_SEL==3, SCL_3 are assigned to SCL_I, SDA_3 is assigned to SDA_I；
If CH_SEL==4, SCL_4 are assigned to SCL_I, SDA_4 is assigned to SDA_I；
If CH_SEL==5, SCL_5 are assigned to SCL_I, SDA_5 is assigned to SDA_I；
If CH_SEL==6, SCL_6 are assigned to SCL_I, SDA_6 is assigned to SDA_I；
If CH_SEL==7, SCL_7 are assigned to SCL_I, SDA_7 is assigned to SDA_I.
The method that multiple I2C interface standard group equipment are supported based on SoC of the present embodiment, step：
1：The system working software of PS processors determines the I2C controllers of current PS processors according to system design considerations
Communicated with one in 8 exterior I 2C interface standard group equipment；
2：PS processors control CH_SEL concrete numerical value by AXI EBIs and AXI protocol parsing module, select one
Individual exterior I 2C interface standards group equipment；
3：I2C bus control modules are according to the numerical value of CH_SEL control signals, I2C controllers inside PS processors
I2C buses are connected to the I2C buses of corresponding external equipment；
4：One in the I2C controllers and exterior I 2C interface standard group equipment of PS processors is communicated.
The technological thought of embodiment above only to illustrate the invention, it is impossible to protection scope of the present invention is limited with this, it is all
It is any change for being done on the basis of technical scheme according to technological thought proposed by the present invention, each falls within present invention protection model
Within enclosing.
Claims (5)
- A kind of 1. device that multiple SPI interface standard group equipment are supported based on SoC, it is characterised in that：Including complete programmable SoC, The PL field programmable gate arrays inside PS processors, complete programmable SoC, AXI EBIs inside complete programmable SoC, EMIO data-interfaces, an AXI protocol parsing module, an I2C bus control module, the PS processors carry an I2C Controller, communicated between the PS processors and PL field programmable gate arrays by the AXI EBIs, while in institute State between PS processors and PL field programmable gate arrays by the EMIO data interface communications, on the EMIO data-interfaces SCL_O, SCL_T, SCL_I are set, and SDA_O, SDA_T, SDA_I signal ports, the PL field programmable gate arrays inside is also It is provided with described an AXI protocol parsing module and an I2C bus control module.
- 2. the device of multiple SPI interface standard group equipment is supported based on SoC according to claim 1, it is characterised in that described The I2C buses of the I2C controllers of PS processors are made up of following 6 signals：1) SCL_I is that the serial clock of I2C data/address bus inputs the triple gate from external equipment；2) SCL_O is that the serial clock of I2C data/address bus is output to the triple gate of external equipment；3) SCL_T is that the serial clock output of I2C data/address bus enables the triple gate of external equipment；4) SDA_I is the serial date transfer of I2C data/address bus from the triple gate of external equipment；5) SDA_O is that the serial data of I2C data/address bus is output to the triple gate of external equipment；6) SDA_T is that the serial data output of I2C data/address bus enables the triple gate of external equipment.
- 3. the device of multiple SPI interface standard group equipment is supported based on SoC according to claim 1, it is characterised in that：It is described The data bit width of the read/write address bus (RW_ADDR) of AXI EBIs is 32bit；The data of read data bus (RD_DATA) Bit wide is that 32bit, the data bit width of write data bus (WR_DATA) are 32bit；I2C buses are given in AXI protocol parsing module Control module defines a control register CH_SEL, and this register address is 0x00000080, and data bit width is 3bit (CH_SEL[2:0]), CH_SEL controls the channel selecting of I2C buses.
- 4. the device of multiple SPI interface standard group equipment is supported based on SoC according to claim 1, it is characterised in that：It is described I2C bus control modules can by the CH_SEL signal deciding PS processors of AXI bus marcos and PL scenes according to PS processors I2C buses between programming gate array are connected to one in the I2C buses of multiple connection external equipments；In I2C bus marcos Inside modules define two signals, are I2C_SCL, I2C_SDA respectively；The PL field programmable gate arrays and external equipment connect The I2C bus signals connect are all bidirectional data ports.
- 5. the device of multiple SPI interface standard group equipment is supported based on SoC according to claim 1, it is characterised in that described The I2C buses of I2C bus control modules are made up of following 6 signals：1) SCL_I is that the serial clock of I2C data/address bus inputs the triple gate from external equipment；2) SCL_O is that the serial clock of I2C data/address bus is output to the triple gate of external equipment；3) SCL_T is that the serial clock output of I2C data/address bus enables the triple gate of external equipment；4) SDA_I is the serial date transfer of I2C data/address bus from the triple gate of external equipment；5) SDA_O is that the serial data of I2C data/address bus is output to the triple gate of external equipment；6) SDA_T is that the serial data output of I2C data/address bus enables the triple gate of external equipment.
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