CN206977523U

CN206977523U - The multiplex system of incoming call ID detections

Info

Publication number: CN206977523U
Application number: CN201720744222.3U
Authority: CN
Inventors: 王国民; 郭栋
Original assignee: Sichuan Sea Communications Polytron Technologies Inc
Current assignee: Sichuan Sea Communications Polytron Technologies Inc
Priority date: 2017-06-23
Filing date: 2017-06-23
Publication date: 2018-02-06
Anticipated expiration: 2027-06-23

Abstract

The utility model discloses the multiplex system of incoming call ID detections, including multiple user interface circuits, the FPGA being connected with each user interface circuit, the CPU being connected with FPGA；Each user interface circuit includes speech A/D convertor circuit, the bell flowing detecting circuit being connected with speech A/D convertor circuit；The logic control element that the FPGA is connected including Boll traits port with bell flowing detecting circuit, the speech selecting switch being connected with logic control element, the ID detection units being connected with speech selecting switch, speech selecting switch are connected with bell flowing detecting circuit；The CPU is connected with ID detection units and reads the testing result of ID detection units, and CPU is also connected with logic control element；The logic control element integrated timer.The utility model uses the multiplexing of FPGA different periods, without setting an ID detection circuit respectively to every user's line, detects circuit using only an ID and just can detect a plurality of user's line.

Description

The multiplex system of incoming call ID detections

Technical field

It the utility model is related to the multiplex system of incoming call ID detections.

Background technology

In a comprehensive communication network, interconnecting between heterogeneous networks is essential.Such as dedicated network With interconnecting for public telephone communication network PSTN.Typically, two schemes are associated with the mutual of PSTN, one kind is believed by No.7 The E1 group road interconnection of order, this mutual contact mode need the cooperation of PSTN network operator.It is another most simple and it is most Be to be interconnected by way of analog junction.This method only needs one or several PSTN user's line, i.e., we are normal The outside line said.

Each outside line is equivalent to PSTN user's line, and according to international standard, its id information is in first time ring About sent out afterwards after 200ms, if user needs, ID detection circuits just must be specially designed on subscriber terminal equipment, such as greatly Telephone set with caller identification known to family.It is just necessary if dedicated network is interconnected by analog junction (outside line) and PSTN ID detection circuits are designed in the interchanger of dedicated network.

In a special comprehensive communication network, it may be necessary to a plurality of outside line, or outside line quantity be it is uncertain, by with Family is according to interim setting is actually needed, at this moment, if each user interface that may be configured to outside line is all designed with ID inspections Slowdown monitoring circuit, very big waste certainly will be caused, and increase hardware cost.Such as we develop " WJS-I pattern synthesis access with In switching equipment ", 30 user's lines are shared, each user's line can be configured to outside line, if in all 30 users ID detection circuits are all designed on line, cost can be greatly increased.But if only choosing wherein several then again limits use Flexibility.

Utility model content

The purpose of this utility model is to provide the multiplex system of incoming call ID detections, mainly solve it is existing to every with The problem of family line carries out ID detections and increases cost.

To achieve these goals, the technical solution adopted in the utility model is as follows：

The multiplex system of incoming call ID detections, including multiple user interface circuits, are connected with each user interface circuit FPGA, the CPU being connected with FPGA；

Each user interface circuit includes speech A/D convertor circuit, the ringing-current inspection being connected with speech A/D convertor circuit Slowdown monitoring circuit；

The FPGA includes the logic control element that Boll traits port is connected with bell flowing detecting circuit, with logic control list The speech selecting switch of member connection, the ID detection units being connected with speech selecting switch, speech selecting switch and Boll traits electricity Road connects；

The CPU is connected with ID detection units and reads the testing result of ID detection units, central processing list Member is also connected with logic control element；

The logic control element integrated timer.

Specifically, the FPGA also includes buffering area, and the buffering area is connected with ID detection units, caching ID detection units Testing result is simultaneously read for CPU.The buffering area uses FLASH.

Preferably, the FPGA uses EP2C35 chips.

Further, the speech selecting switch is multi-path voice selecting switch, is connect per a user is connected respectively all the way Mouth circuit, the on/off on multi-path voice selecting switch road is controlled by logic control element.

Preferably, the CPU uses MT family chips.

Compared with prior art, the utility model has the advantages that：

The utility model is multiplexed by the FPGA of different periods, detects success rate 99.9%, the utility model only has With two or above outside line, and can just be clashed during outside line incoming call simultaneously more than two, when clashing, compared with Early detecting that the outside line of ring can successfully be detected its ID, remaining circuit will be unable to successfully detect, but in actual applications, typically The negligible amounts of outside line are set, while the probability of incoming call is very low, thus the probability clashed is also very low.Due to using The multiplexing of FPGA different periods, it is therefore not necessary to an ID detection circuit be set respectively to every user's line, using only one ID detection circuits just can detect a plurality of user's line, both cost-effective, also increase the flexibility used.

Brief description of the drawings

Fig. 1 is the system block diagram of the utility model-embodiment.

Embodiment

With reference to embodiment and accompanying drawing, the utility model is described in further detail, and embodiment of the present utility model includes But it is not limited to the following example.

Embodiment

As shown in figure 1, the multiplex system of incoming call ID detections, including multiple user interface circuits, with user interface electricity The FPGA of road connection, the CPU being connected with FPGA, user interface circuit includes speech A/D convertor circuit, with speech AD The bell flowing detecting circuit of change-over circuit connection, the connection of FPGA and bell flowing detecting circuit.

FPGA includes the logic control element being connected with bell flowing detecting circuit, the speech selection being connected with logic control element Switch, the ID detection units being connected with speech selecting switch, the buffering area being connected with ID detection units, the buffering area and centre Manage unit connection；Logic control element integrated timer, ringing-current logic control element are connected with CPU, speech selection Switch is connected with bell flowing detecting circuit.The buffering area of the present embodiment uses FLASH.

The FPGA of the present embodiment uses EP2C35 chips.

The course of work of the present utility model is as follows：

S1, the Boll traits result of bell flowing detecting circuit are output to FPGA logic control element, FPGA in a manner of level All the time wait for and detect the level；

S2, when FPGA detect the Boll traits level of certain user interface circuit for it is effective when, it is first determined whether being the Ring, if it is, performing step S3；

S3, etc. after first time ring terminates, then the 100ms that is delayed starts speech selecting switch and timer, and by the user Digital voice be output to ID detection units, while user interface circuit sequence number is reported to CPU；ID detections are single The testing result of member is stored in a fixed buffering area, is actively read by CPU；

S4, timer then, recover speech selecting switch immediately, and timer is reset.

Multiplexed by the FPGA of different periods, detect success rate 99.9%, the utility model is only with two Or above outside line, and can just be clashed during outside line incoming call simultaneously more than two, when clashing, relatively early detect is shaken The outside line of bell can successfully be detected its ID, and remaining circuit will be unable to successfully detect, but in actual applications, general setting outside line Negligible amounts, while the probability of incoming call is very low, thus the probability clashed is also very low.

According to above-described embodiment, the utility model can be realized well.What deserves to be explained is based on said structure design On the premise of, to solve same technical problem, some made on the utility model are without substantial change or profit Color, the essence of used technical scheme is still as the utility model, therefore it should also be as in protection model of the present utility model In enclosing.

Claims

1. the multiplex system for ID detections of sending a telegram here, it is characterised in that including multiple user interface circuits, with each user interface The FPGA of circuit connection, the CPU being connected with FPGA；

Each user interface circuit includes speech A/D convertor circuit, the Boll traits electricity being connected with speech A/D convertor circuit Road；

The FPGA includes the logic control element that Boll traits port is connected with bell flowing detecting circuit, connects with logic control element The speech selecting switch connect, the ID detection units being connected with speech selecting switch, speech selecting switch connect with bell flowing detecting circuit Connect；

The CPU is connected with ID detection units and reads the testing result of ID detection units, and CPU is also It is connected with logic control element；

The logic control element integrated timer.

2. the multiplex system of incoming call ID detections according to claim 1, it is characterised in that the FPGA also includes slow Area is rushed, the buffering area is connected with ID detection units, is cached the testing result of ID detection units and is read for CPU.

3. the multiplex system of incoming call ID detections according to claim 1, it is characterised in that the FPGA is used EP2C35 chips.

4. the multiplex system of incoming call ID detections according to claim 1, it is characterised in that the speech selecting switch For multi-path voice selecting switch, per a user interface circuit is connected respectively all the way, multi-path voice is controlled by logic control element The on/off on selecting switch road.

5. the multiplex system of incoming call ID detections according to claim 1, it is characterised in that the CPU Using MT family chips.