CN206963050U - A kind of I2S audio codec circuitries - Google Patents

A kind of I2S audio codec circuitries Download PDF

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Publication number
CN206963050U
CN206963050U CN201720970175.4U CN201720970175U CN206963050U CN 206963050 U CN206963050 U CN 206963050U CN 201720970175 U CN201720970175 U CN 201720970175U CN 206963050 U CN206963050 U CN 206963050U
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China
Prior art keywords
pin
chip
electric capacity
loudspeaker
circuitries
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CN201720970175.4U
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Chinese (zh)
Inventor
刘军
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Guangzhou Xingyi Electronic Technology Co Ltd
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Guangzhou Xingyi Electronic Technology Co Ltd
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Priority to CN201720970175.4U priority Critical patent/CN206963050U/en
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Abstract

The utility model discloses the parallel interface and series resistance R1 access high level VCC5 that the pin 26 of a kind of I2S audio codec circuitries, including chip U2, the chip U2 meets electric capacity C3 and electric capacity C5;Chip U2 pin 31 connects electric capacity C1 and electric capacity C2 parallel interface and ground connection.The I2S audio codec circuitries, preposition amplification and loudspeaker with reference to stereo difference microphone, earphone and difference, the driving of three-dimensional sound ray output, reduce necessary external module during application, direct drive earphone and loudspeaker are realized, without additional power amplifier;The encoding and decoding integration of audio format data is realized simultaneously.

Description

A kind of I2S audio codec circuitries
Technical field
Audio codec circuitry technical field is the utility model is related to, especially a kind of I2S audio codec circuitries.
Background technology
Current Cortex-M family chips are extremely popularized, should in handheld device and amusement equipment in all kinds of control systems With very extensive.But the Cortex-M family chips that ST is representative do not have support audio coding decoding function on hardware.
Utility model content
The purpose of this utility model is to provide a kind of I2S audio codec circuitries, while realizes audio format data Encoding and decoding integration, to solve the problems mentioned in the above background technology.
To achieve the above object, the utility model provides following technical scheme:A kind of I2S audio codec circuitries, bag The pin 26 for including chip U2, the chip U2 connects electric capacity C3 and electric capacity C5 parallel interface and series resistance R1 access high level VCC5;Chip U2 pin 31 connects electric capacity C1 and electric capacity C2 parallel interface and ground connection;Chip U2 pin 13 and 14 and after connecing Series resistance R7 is connected to high level VCC3, and chip U2 pin 12,24 and 33 is simultaneously grounded after connecing, chip U2 pin 14 and pin Shunt-wound capacitance C7 and electric capacity C8 are gone back between 33;The series resistance R14 of pin 18 of the chip U2 is simultaneously grounded;The chip U2's draws After pin 29 and pin 30 distinguish series capacitance C4 and electric capacity C6, it is coupled with 1,2 binding posts of loudspeaker;The chip U2's Pin 23 and pin 25 are coupled with loudspeaker SPK signals positive pole and loudspeaker SPK signal negative poles;The pin 1 of the chip U2 Series capacitance C16 and electric capacity C18 is connected on microphone MIC signal ends 1 respectively with pin 4, and chip U2 pin 2 and pin 5 divide Other series capacitance C17 and electric capacity C19 are connected on microphone MIC signal ends 2;The pin 19 and pin 20 of the chip U2 is distinguished Output pulse width audio signal modulation after series capacitance C20 and electric capacity C21;The series resistance R13 of pin 32 of the chip U2 It is connected on microphone MIC signal ends 1;The series capacitance C24 of pin 27 and electric capacity C26 of the chip U2 is connected to microphone MIC letters On number end 1, parallel resistance R15 on electric capacity C24 one end and resistance R13 one end also shunt-wound capacitance C25, electric capacity C26.
As further program of the utility model:3 binding posts of the loudspeaker are also attached to simulated audio signal LINE input interface end 3, and be grounded.
As further program of the utility model:Pin 3 and pin 6 the difference series capacitance C9 and electricity of the chip U2 Hold C10, and be coupled with simulated audio signal LINE input interface end 1 and 2.
As further program of the utility model:The model WM8978 of the chip U2.
Compared with prior art, the utility model beneficial effect:
This I2S audio codec circuitries, realize that high-performance stereo is more by chip U2 and effective peripheral circuit Media Digital signal coder function.12 DAC&ADC are realized, up to 192K@24bit audio signals can be played;The circuit Adjusted with section EQ, support 3D audios;The preposition amplification of the circuit combination stereo difference microphone and loudspeaker, earphone and difference Point, the driving of three-dimensional sound ray output, reduce necessary external module during application, realize direct drive earphone and loudspeaker, without Additional power amplifier;The encoding and decoding integration of audio format data is realized simultaneously.
Brief description of the drawings
Fig. 1 is circuit theory diagrams of the present utility model.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out Clearly and completely describing, it is clear that described embodiment is only the utility model part of the embodiment, rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made The every other embodiment obtained, belong to the scope of the utility model protection.
Referring to Fig. 1, in the utility model embodiment, a kind of I2S audio codec circuitries, including chip U2, chip U2 model WM8978, realize that high-performance stereo multimedia digital signal is compiled by chip U2 and effective peripheral circuit Code device function, realizes 12 DAC&ADC, can play up to 192K@24bit audio signals;Chip U2 pin 26 connects electric capacity C3 and electric capacity C5 parallel interface and series resistance R1 access high level VCC5;Chip U2 pin 31 connects electric capacity C1 and electric capacity C2 parallel interface and ground connection;Chip U2 pin 13 and 14 simultaneously meets rear series resistance R7 and is connected to high level VCC3, chip U2's Pin 12,24 and 33 is simultaneously grounded after connecing, and shunt-wound capacitance C7 and electric capacity C8 are gone back between chip U2 pin 14 and pin 33;Chip U2 The series resistance R14 of pin 18 and be grounded;After chip U2 pin 29 and pin 30 difference series capacitance C4 and electric capacity C6, respectively It is connected on 1,2 binding posts of loudspeaker;3 binding posts of loudspeaker are also attached to simulated audio signal LINE input interface end 3, And it is grounded;Chip U2 pin 3 and pin 6 difference series capacitance C9 and electric capacity C10, and it is coupled with simulated audio signal LINE Input interface end 1 and 2 on;Chip U2 pin 23 and pin 25 is coupled with loudspeaker SPK signals positive pole and loudspeaker SPK Signal negative pole, loudspeaker SPK signals positive pole and loudspeaker SPK signal negative poles are connected to and are arranged on the loudspeaker that development board bottom carries On;Series capacitance C16 and electric capacity C18 is connected on microphone MIC signal ends 1 chip U2 pin 1 and pin 4 respectively, chip U2 Pin 2 and pin 5 series capacitance C17 and electric capacity C19 is connected on microphone MIC signal ends 2 respectively;Chip U2 pin 19 With output pulse width audio signal modulation after the difference of pin 20 series capacitance C20 and electric capacity C21;Chip U2 pin 32 is connected Resistance R13 is connected on microphone MIC signal ends 1;The chip U2 series capacitance C24 of pin 27 and electric capacity C26 is connected to microphone MIC On signal end 1, parallel resistance R15 on electric capacity C24 one end and resistance R13 one end also shunt-wound capacitance C25, electric capacity C26.
The I2S audio codec circuitries, there is section EQ regulations, support 3D audios;The circuit combination stereo difference wheat The preposition amplification of gram wind and loudspeaker, earphone and difference, the driving of three-dimensional sound ray output, reduce necessary outer set during application Part, direct drive earphone and loudspeaker are realized, without additional power amplifier;The encoding and decoding one of audio format data is realized simultaneously Change.
It is obvious to a person skilled in the art that the utility model is not limited to the details of above-mentioned one exemplary embodiment, and And in the case of without departing substantially from spirit or essential attributes of the present utility model, it can realize that this practicality is new in other specific forms Type.Therefore, no matter from the point of view of which point, embodiment all should be regarded as exemplary, and is nonrestrictive, this practicality is new The scope of type limits by appended claims rather than described above, it is intended that the equivalency fallen in claim is contained All changes in justice and scope are included in the utility model.Any reference in claim should not be considered as limitation Involved claim.
Moreover, it will be appreciated that although the present specification is described in terms of embodiments, not each embodiment is only wrapped Containing an independent technical scheme, this narrating mode of specification is only that those skilled in the art should for clarity Using specification as an entirety, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art It is appreciated that other embodiment.

Claims (4)

1. a kind of I2S audio codec circuitries, including chip U2, it is characterised in that:The pin 26 of the chip U2 connects electric capacity C3 and electric capacity C5 parallel interface and series resistance R1 access high level VCC5;Chip U2 pin 31 connects electric capacity C1 and electric capacity C2 parallel interface and ground connection;Chip U2 pin 13 and 14 simultaneously meets rear series resistance R7 and is connected to high level VCC3, chip U2's Pin 12,24 and 33 is simultaneously grounded after connecing, and shunt-wound capacitance C7 and electric capacity C8 are gone back between chip U2 pin 14 and pin 33;The core The piece U2 series resistance R14 of pin 18 is simultaneously grounded;Pin 29 and pin 30 the difference series capacitance C4 and electric capacity of the chip U2 After C6, it is coupled with 1,2 binding posts of loudspeaker;The pin 23 and pin 25 of the chip U2 is coupled with loudspeaker SPK Signal positive pole and loudspeaker SPK signal negative poles;Pin 1 and pin 4 difference the series capacitance C16 and electric capacity C18 of the chip U2 It is connected on microphone MIC signal ends 1, series capacitance C17 and electric capacity C19 are connected to Mike respectively for chip U2 pin 2 and pin 5 On wind MIC signal ends 2;It is wide that pulse is exported after pin 19 and pin 20 difference the series capacitance C20 and electric capacity C21 of the chip U2 Spend audio signal modulation;The series resistance R13 of pin 32 of the chip U2 is connected on microphone MIC signal ends 1;The chip U2 The series capacitance C24 of pin 27 and electric capacity C26 be connected on microphone MIC signal ends 1, electric capacity C24 one end and resistance R13 one end are also Parallel resistance R15 on shunt-wound capacitance C25, electric capacity C26.
A kind of 2. I2S audio codec circuitries according to claim 1, it is characterised in that:3 wiring of the loudspeaker Post is also attached to simulated audio signal LINE input interface end 3, and is grounded.
A kind of 3. I2S audio codec circuitries according to claim 1, it is characterised in that:The pin 3 of the chip U2 Distinguish series capacitance C9 and electric capacity C10 with pin 6, and be coupled with simulated audio signal LINE input interface end 1 and 2.
A kind of 4. I2S audio codec circuitries according to claim 1, it is characterised in that:The model of the chip U2 For WM8978.
CN201720970175.4U 2017-08-04 2017-08-04 A kind of I2S audio codec circuitries Active CN206963050U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201720970175.4U CN206963050U (en) 2017-08-04 2017-08-04 A kind of I2S audio codec circuitries

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201720970175.4U CN206963050U (en) 2017-08-04 2017-08-04 A kind of I2S audio codec circuitries

Publications (1)

Publication Number Publication Date
CN206963050U true CN206963050U (en) 2018-02-02

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CN (1) CN206963050U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109814468A (en) * 2019-03-20 2019-05-28 广州市星翼电子科技有限公司 A kind of Internet of Things development board based on STM32L4 chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109814468A (en) * 2019-03-20 2019-05-28 广州市星翼电子科技有限公司 A kind of Internet of Things development board based on STM32L4 chip

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