CN206948274U

CN206948274U - A kind of control circuit, biasing circuit

Info

Publication number: CN206948274U
Application number: CN201720660824.0U
Authority: CN
Inventors: 马军; 苏强; 奕江涛; 李阳
Original assignee: Shang Rui Microelectronics (shanghai) Co Ltd
Current assignee: Shang Rui Microelectronics (shanghai) Co Ltd
Priority date: 2017-06-08
Filing date: 2017-06-08
Publication date: 2018-01-30
Anticipated expiration: 2027-06-08

Abstract

The utility model discloses a kind of control circuit, and applied to biasing circuit, the biasing circuit includes：The first transistor and second transistor；The grid of the first transistor and the grid of second transistor connect；The first transistor and second transistor are to be amplified to obtain the transistor of bias direct current electric current with reference to DC current by the input of the biasing circuit；The control circuit includes：By the first DC voltage compared with the second DC voltage, the detection circuit of comparative result is obtained；And adjust first DC voltage and the second DC voltage using comparative result so that the drain terminal DC voltage of the first transistor and the drain terminal DC voltage identical adjustment circuit of second transistor in biasing circuit work；First DC voltage is the drain terminal DC voltage of the first transistor；Second DC voltage is the drain terminal DC voltage of second transistor.The utility model also discloses a kind of biasing circuit simultaneously.

Description

Control circuit and bias circuit

Technical Field

The utility model relates to a power amplifier's bias circuit especially relates to a control circuit, bias circuit.

Background

The power amplifier is an active circuit, and a bias circuit is needed to provide a proper bias direct current and bias direct voltage to normally operate so as to meet various indexes of the power amplifier, such as linearity, efficiency, power level and the like.

In some applications, the reference dc current and the bias state of each bias device need to be adjusted according to different requirements, different powers are generated by using the same bias circuit, and various indexes of the power amplifier, such as linearity and power consumption, need to be satisfied.

In the prior art, the adjustable bias circuit is used for realizing the output of different powers, but the defects are as follows: the direct current control precision is poor, the debugging is inconvenient, and the process deviation and the temperature drift of the bias device cause the output power and the linearity to drift.

Therefore, how to control the same bias circuit to generate different power outputs and satisfy the stability index of linearity is a problem to be solved urgently at present.

SUMMERY OF THE UTILITY MODEL

For solving the technical problem that exists now, the embodiment of the utility model provides a control circuit, biasing circuit.

The embodiment of the utility model provides a technical scheme is so realized:

the embodiment of the utility model provides a control circuit is applied to biasing circuit, biasing circuit includes: a first transistor and a second transistor; the grid electrode of the first transistor is connected with the grid electrode of the second transistor; the first transistor and the second transistor are transistors which amplify an input reference direct current of the bias circuit to obtain a bias direct current, and the second transistor obtains a target output signal based on an input signal of the bias circuit by using the bias direct current; the control circuit includes:

the detection circuit is used for comparing the first direct current voltage with the second direct current voltage to obtain a comparison result; and the number of the first and second groups,

the comparison result is used for adjusting the first direct current voltage and the second direct current voltage, so that the drain end direct current voltage of the first transistor is the same as the drain end direct current voltage of the second transistor in the bias circuit work;

the first direct current voltage is the drain end direct current voltage of the first transistor; the second direct current voltage is the direct current voltage of the drain terminal of the second transistor.

In the above scheme, the adjusting circuit controls the conduction degree of the first transistor and the second transistor by using the comparison result to adjust the first direct current voltage and the second direct current voltage.

In the above scheme, the adjusting circuit is an adjusting circuit that controls the conduction degree of the first transistor and the second transistor by pulling up or pulling down the gate dc voltages of the first transistor and the second transistor using the comparison result to adjust the first dc voltage and the second dc voltage.

An embodiment of the utility model provides a bias circuit, include:

a first transistor;

a second transistor; the grid electrode of the first transistor is connected with the grid electrode of the second transistor; the first transistor and the second transistor amplify an input reference direct current of the bias circuit to obtain a bias direct current; the second transistor obtains a target output signal based on an input signal of the bias circuit by using the bias direct current;

the voltage generation circuit controls the third transistor to output a target output signal by using the generated first bias direct-current voltage matched with the power grade, so that the target output signal meets a preset linear relation; and

a control circuit; the control circuit includes: the detection circuit is used for comparing the first direct current voltage with the second direct current voltage to obtain a comparison result; the adjusting circuit adjusts the first direct current voltage and the second direct current voltage by using the comparison result, so that the drain end direct current voltage of the first transistor is the same as the drain end direct current voltage of the second transistor in the work of the biasing circuit; the first direct current voltage is the drain end direct current voltage of the first transistor; the second direct current voltage is the direct current voltage of the drain terminal of the second transistor.

In the above scheme, the adjusting circuit controls the conduction degree of the first transistor and the second transistor by using the comparison result to adjust the first dc voltage and the second dc voltage.

In the above solution, the voltage generating circuit is a voltage generating circuit that generates a second bias dc voltage matched to a power class, where the second bias dc voltage is used as a gate dc voltage of the first transistor and the second transistor; the first bias direct current voltage and the second bias direct current voltage meet a preset condition; the second direct current voltage changes along with the changes of the first bias direct current voltage and the second bias direct current voltage.

In the above scheme, the voltage generation circuit is a voltage generation circuit that generates at least one first bias dc voltage matched with a power class by using at least one resistor and at least one current source, and each first bias dc voltage controls one third transistor and outputs a target output signal, so that the target output signal satisfies a preset linear relationship.

The embodiment of the utility model provides a control circuit, biasing circuit compare first direct current voltage and second direct current voltage, obtain the comparison result; the first direct current voltage is the drain end direct current voltage of the first transistor; the second direct current voltage is the direct current voltage of the drain terminal of the second transistor; adjusting the first direct current voltage and the second direct current voltage by using the comparison result, so that the drain end direct current voltage of the first transistor is the same as the drain end direct current voltage of the second transistor in the operation of the biasing circuit; wherein a gate of the first transistor is connected to a gate of a second transistor; the first transistor and the second transistor amplify an input reference direct current of the bias circuit to obtain a bias direct current, and the second transistor obtains a target output signal based on an input signal of the bias circuit by using the bias direct current. In an embodiment of the present invention, the first dc voltage and the second dc voltage are adjusted by using a comparison result of the first dc voltage and the second dc voltage, so that the drain dc voltage of the first transistor is the same as the drain dc voltage of the second transistor. Therefore, the bias circuit can obtain more stable performance in terms of power level and linearity under the influence of external factors such as temperature, process drift and the like.

Drawings

FIG. 1 is a first schematic diagram of a bias circuit according to the related art;

FIG. 2 is a schematic diagram of a bias circuit in the related art;

fig. 3 is a schematic diagram of a control circuit according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a second bias circuit according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a structure of a three-bias circuit according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a structure of a four-bias circuit according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a five-bias circuit structure according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a six-bias circuit structure according to an embodiment of the present invention;

fig. 9 is a schematic flow chart of a seventh control method according to an embodiment of the present invention;

fig. 10 is a schematic flowchart of an implementation method of an eight-bias circuit according to an embodiment of the present invention.

Detailed Description

At present, a circuit composition structure of a bias circuit is shown in fig. 1, wherein RFin is an alternating current (radio frequency) input signal; RFout is the power of the output; ccomple is a signal coupling capacitance; vbat is the power supply; mref1, Mref2 are offset reference tubes; mmir is a direct current output pipe; mcas is a cascode transistor; l is a load inductance; itrim is a reference direct current source; rtrim is the tuning resistance.

The operating principle of the bias circuit shown in fig. 1 is as follows: under the action of bias direct current provided by a bias circuit, amplifying alternating current input signals RFin by different amplification factors to obtain different output powers RFout; the input reference direct current Iref of the bias circuit is amplified through Mref2 and Mmir to obtain bias direct current; bias voltages are generated by Itrim, Rtrim, Mref1, Mref2 to Mcas to meet the bias requirements of the power amplifier. The specific working process comprises the following steps: when the resistance value of the Rtrim adjusting resistor is zero, since Mref2 is connected with the gate of the mm, and the drain-side direct-current voltages of Mref2 and mm are equal, the ratio of the direct current flowing through Mref2 to the direct current flowing through mm is equal to the ratio of the size (channel width) of Mref2 to the size (channel width) of mm, so that under the condition that the ratio is fixed, the amplified bias direct current can be output on mm by adjusting the size of the Itrim reference direct-current source; but has the following drawbacks: when the resistance value of the Rtrim adjusting resistor is not zero, the drain dc voltages of Mref2 and mrir are not equal because the drain dc voltage of mrir is equal to the gate dc voltage of Mref2 plus the voltage drop of Rtrim minus the gate-source dc voltage of Mcas, and the drain dc voltage of Mref2 is equal to the gate dc voltage of Mref2, so that the ratio of the dc current flowing through Mref2 to the dc current flowing through mrir is not equal to the ratio of the dimension (channel width) of Mref2 to the dimension (channel width) of mrir, resulting in poor dc control accuracy.

The cascode transistor Mcas in the bias circuit shown in fig. 1 shields the influence of the power supply Vbat on the bias dc current, and according to the requirement of the output power level, the voltage on the gate of the cascode transistor Mcas is adjusted by Itrim and Rtrim, and the input reference dc current of the bias circuit is amplified by Mref2 and mm, so as to meet the bias requirement of the power amplifier.

However, the bias circuit shown in fig. 1 has the following disadvantages: firstly, when the resistance value of the adjusting resistor Rtrim is not equal to zero, the direct current voltages at the drain ends of Mref2 and Mmir are mismatched, and the direct current flowing through Mmir is not proportional to the direct current flowing through Mref2, so that the control accuracy of the direct current is poor; secondly, the direct current (bias direct current) flowing through Mmir and the adjusting direct current (Itrim) are mutually coupled, so that the debugging is inconvenient; thirdly, the process deviation and the temperature drift of Mref1, Mref2, Mcas, Mmir and Rtrim make the drain terminal direct current voltages of Mref2 and Mmir unable to follow each other, so that the power and the linearity of the output of the bias circuit drift.

The bias circuit shown in fig. 2 is produced based on the defects of the bias circuit shown in fig. 1. As shown in FIG. 2, RFin is the alternating current (radio frequency) input signal; RFout is the power of the output; ccomple is a signal coupling capacitance; vbat is the power supply; mref2 is an offset reference tube; mmir is a direct current output pipe; mcas is a cascode transistor; l is a load inductance; itrim is the regulated dc current source; rtrim is the tuning resistance; iref is a reference dc current source.

The operating principle of the bias circuit shown in fig. 2 is as follows: under the action of bias direct current provided by a bias circuit, amplifying alternating current input signals RFin by different amplification factors to obtain different output powers RFout; the input reference direct current Iref of the bias circuit is amplified through Mref2 and Mmir to obtain bias direct current; and generating a bias voltage to the Mcas through the Rtrim and the Itrim so as to meet the bias requirement of the power amplifier. The specific working process is as follows: when adjusting Itrim or Rtrim to make the drain voltages of Mref2 and Mmir equal, since the gate dc potentials of Mref2 and Mmir are equal, the ratio of the dc current flowing through Mref2 to the dc current flowing through Mmir is equal to the ratio of the size (channel width) of Mref2 to the size (channel width) of Mmir; however, when Rtrim or Itrim changes, the drain dc voltage of mm is caused to change, which causes the drain dc voltage of Mref2 not to be equal to that of mm, and therefore, the ratio of the dc current flowing through Mref2 to the dc current flowing through mm is not equal to the ratio of the size of Mref2 to the size of mm, which causes poor control accuracy of the dc current.

The advantages of the bias circuit shown in fig. 2 over the bias dc circuit shown in fig. 1 are: the adjustment direct current source Itrim and the reference direct current source Iref are separated from each other, so that the debugging is more convenient.

The bias circuit shown in fig. 2 still has the following disadvantages: the direct current voltage at the drain ends of the first current collector, the Mref2 and the Mmir is mismatched, and the direct current control accuracy is poor; secondly, the process deviation and temperature drift of Mref1, Mref2, Mcas, Mmir, Rtrim affect the drain terminal dc voltage of Mref2, Mmir, so that the power and linearity of the bias circuit output drift.

Based on this, in various embodiments of the present invention: comparing the first direct current voltage with the second direct current voltage to obtain a comparison result; the first direct current voltage is the drain end direct current voltage of a first transistor of the bias circuit; the second direct current voltage is the direct current voltage of the drain terminal of a second transistor of the bias circuit; adjusting the first direct current voltage and the second direct current voltage by using the comparison result, so that the drain end direct current voltage of the first transistor is the same as the drain end direct current voltage of the second transistor in the operation of the biasing circuit; the grid electrode of the first transistor is connected with the grid electrode of the second transistor through a resistor for attenuating alternating current signals; the first transistor and the second transistor are used for amplifying an input reference direct current of the bias circuit to obtain a bias direct current, and the second transistor obtains a target output signal based on an input signal of the bias circuit by using the bias direct current.

Example one

As shown in fig. 3, the control circuit provided in this embodiment includes: a detection circuit 31, an adjustment circuit 32; wherein,

the detection circuit 31 is configured to compare the first dc voltage with the second dc voltage to obtain a comparison result; the first direct current voltage is the drain end direct current voltage of the first transistor; the second direct current voltage is the direct current voltage of the drain terminal of the second transistor;

the adjusting circuit 32 is configured to adjust the first dc voltage and the second dc voltage according to the comparison result, so that the drain dc voltage of the first transistor is the same as the drain dc voltage of the second transistor during the operation of the bias circuit.

The grid electrode of the first transistor is connected with the grid electrode of the second transistor through a resistor for attenuating alternating current signals; the first transistor and the second transistor are used for amplifying an input reference direct current of the bias circuit to obtain a bias direct current, and the second transistor obtains a target output signal based on an input signal of the bias circuit by using the bias direct current.

In practical application, the input signal of the bias circuit can be a radio frequency input signal, the target output signal of the bias circuit can be radio frequency output signals with different power levels, and when the power levels of the target output signals are different, the bias circuit is required to provide different bias direct currents; here, by adjusting the magnitude of the input reference dc current of the bias circuit, the first transistor and the second transistor amplify the input reference dc current of the bias circuit to obtain a bias dc current meeting the actual requirement, and the second transistor obtains target output signals of different power levels based on the input signal of the bias circuit by using the bias dc current.

In practical application, when the bias circuit works and the gate dc voltage of the first transistor changes to cause the drain dc voltages of the first transistor and the second transistor to change, the detection circuit 31 detects and compares the first dc voltage (the drain dc voltage of the first transistor) and the second dc voltage (the drain dc voltage of the second transistor) to obtain a comparison result; the adjusting circuit 32 controls the gate dc voltages of the first transistor and the second transistor by using the comparison result, and realizes that the drain dc voltage of the first transistor is equal to the drain dc voltage of the second transistor by adjusting the impedances of the first transistor and the second transistor.

When the drain dc voltage of the second transistor changes and the drain dc voltage of the first transistor remains unchanged, the detection circuit 31 detects and compares the first dc voltage (the drain dc voltage of the first transistor) and the second dc voltage (the drain dc voltage of the second transistor) to obtain a comparison result; the adjusting circuit 32 controls the gate dc voltages of the first transistor and the second transistor by using the comparison result, and realizes that the drain dc voltage of the first transistor changes along with the change of the drain dc voltage of the second transistor by adjusting the impedances of the first transistor and the second transistor, thereby finally ensuring that the drain dc voltage of the first transistor is equal to the drain dc voltage of the second transistor.

In one embodiment, the function of the control circuit may be implemented by an operational amplifier.

Because the grid of the first transistor is connected with the grid of the second transistor through the resistor attenuating the alternating current signal, the grid direct current voltage of the first transistor is the same as the grid direct current voltage of the second transistor, and meanwhile, the drain direct current voltage of the first transistor is also the same as the drain direct current voltage of the second transistor, wherein the ratio of the direct current flowing through the first transistor to the direct current flowing through the second transistor is equal to the ratio of the size of the first transistor to the size of the second transistor.

In one embodiment, the adjusting circuit 32 is specifically configured to: and controlling the conduction degrees of the first transistor and the second transistor by using the comparison result so as to adjust the first direct current voltage and the second direct current voltage.

The conduction degree refers to the change of the direct current voltage of the drain terminals of the first transistor and the second transistor by changing the impedance of the first transistor and the second transistor.

In one embodiment, the adjusting circuit 32 is specifically configured to: and controlling the conduction states of the first transistor and the second transistor by pulling up or pulling down the direct current voltages of the grids of the first transistor and the second transistor by using the comparison result so as to adjust the first direct current voltage and the second direct current voltage.

In practical application, due to the influence of temperature drift or other reasons, the gate dc voltages of the first transistor and the second transistor may change, and when the gate dc voltages of the first transistor and the second transistor are large, the gate dc voltages of the first transistor and the second transistor need to be pulled down, so that the stability of the gate dc voltages of the first transistor and the second transistor can be ensured. The implementation process of the pull-down comprises the following steps: driving an N-channel metal oxide semiconductor field effect transistor (NMOS) by using the comparison result, wherein the drain terminal of the NMOS is connected with the grids of the first transistor and the second transistor, and the source terminal of the NMOS is grounded;

when the gate dc voltages of the first transistor and the second transistor are small, the gate dc voltages of the first transistor and the second transistor need to be pulled up, so that the gate dc voltages of the first transistor and the second transistor can be ensured to be stable. The implementation process of the pull-up comprises the following steps: and driving the NMOS by using the comparison result, and increasing the grid direct current voltage of the first transistor and the grid direct current voltage of the second transistor by reducing the pull-down capability of the NMOS.

In practical application, a P-channel metal oxide semiconductor field effect transistor (PMOS) can be used to provide bias direct current and load for an NMOS, and a source end direct current of the PMOS receives a path of bias direct current.

In the embodiment of the present invention, the adjusting circuit 32 directly controls the conduction degree of the first transistor and the second transistor by using the comparison result obtained by the detecting circuit 31 to adjust the first dc voltage and the second dc voltage; alternatively, the adjusting circuit 32 uses the comparison result obtained by the detecting circuit 31 to pull up or pull down the gate dc voltages of the first transistor and the second transistor, and controls the conduction degrees of the first transistor and the second transistor, so as to adjust the first dc voltage and the second dc voltage. In the two modes, when the bias circuit works, the fact that the direct current voltages of the drain ends of the first transistor and the second transistor follow each other to be equal is guaranteed. When the drain direct-current voltages of the first transistor and the second transistor are the same, and the gate-source direct-current voltages of the first transistor and the second transistor are the same, the ratio of the direct current flowing through the first transistor to the direct current flowing through the second transistor is equal to the ratio of the size of the first transistor to the size of the second transistor; according to the ratio, the first transistor and the second transistor can amplify the input reference direct current of the bias circuit to obtain different bias direct currents, and therefore the direct current control accuracy of the bias circuit can be improved.

In addition, the second transistor can obtain target output signals of different power levels based on the input signal of the bias circuit by using the bias direct current, and can obtain more stable performance in terms of power level and linearity.

Example two

As shown in fig. 4, the bias circuit provided in this embodiment includes: a first transistor 41, a second transistor 42, a voltage generation circuit 43, a third transistor 44, and a control circuit 45; wherein,

the gate of the first transistor 41 is connected to the gate of the second transistor 42 via a resistor that attenuates an ac signal; the first transistor 41 and the second transistor 42 are configured to amplify an input reference dc of the bias circuit to obtain a bias dc; the second transistor obtains a target output signal by using the bias direct current and based on an input signal of the bias circuit;

the voltage generating circuit 43 is configured to control the third transistor 44 to output the target output signal by using the generated first bias dc voltage matched with the power level, so that the target output signal satisfies a preset linear relationship;

the preset linear relationship may be that a ratio of a harmonic signal to a fundamental frequency signal in the target output signal satisfies a preset value.

The control circuit 45 includes: the detection circuit 31 is configured to compare the first dc voltage with the second dc voltage to obtain a comparison result; the first dc voltage is a drain dc voltage of the first transistor 41; the second dc voltage is a drain dc voltage of the second transistor 42; the adjusting circuit 32 is configured to adjust the first dc voltage and the second dc voltage according to the comparison result, so that the drain dc voltage of the first transistor 41 is the same as the drain dc voltage of the second transistor 42 during the operation of the bias circuit.

In practical application, the bias circuit utilizes the control circuit 45 to adjust the bias states of the first transistor 41 and the second transistor 42, and generates different bias direct currents by combining the first transistor 41 and the second transistor 42 through adjusting the input reference direct current; the second transistor 42 can obtain target output signals of different power levels based on the input signal of the bias circuit by using the bias direct current, and the bias circuit can achieve more stable performance in terms of power level and linearity.

The magnitude of the output power generated by the bias circuit is related to factors such as the magnitude of the bias current and the magnitude of the input ac signal.

In practical application, when the bias circuit operates, and when the gate dc voltage of the first transistor 41 changes and the drain dc voltages of the first transistor 41 and the second transistor 42 change, the detection circuit 31 detects and compares the first dc voltage (equivalent to the drain dc voltage of the first transistor) and the second dc voltage (equivalent to the drain dc voltage of the second transistor) to obtain a comparison result; the adjusting circuit 32 controls the gate dc voltages of the first transistor 41 and the second transistor 42 by using the comparison result, and adjusts the impedances of the first transistor 41 and the second transistor 42 to make the drain dc voltage of the first transistor 41 equal to the drain dc voltage of the second transistor 42.

When the drain dc voltage of the second transistor 42 changes and the drain dc voltage of the first transistor 41 remains unchanged, the detection circuit 31 detects and compares the first dc voltage (equivalent to the drain dc voltage of the first transistor) and the second dc voltage (equivalent to the drain dc voltage of the second transistor), so as to obtain a comparison result; the adjusting circuit 32 controls the gate dc voltages of the first transistor 41 and the second transistor 42 by using the comparison result, and by adjusting the impedances of the first transistor 41 and the second transistor 42, the drain dc voltage of the first transistor 41 changes along with the change of the drain dc voltage of the second transistor 42, so as to finally ensure that the drain dc voltage of the first transistor 41 is equal to the drain dc voltage of the second transistor 42.

In one embodiment, the adjusting circuit 32 is specifically configured to: using the comparison result, the conduction degree of the first transistor 41 and the second transistor 42 is controlled to adjust the first dc voltage and the second dc voltage.

Here, the on-state refers to a change in the drain-side dc voltage of the first transistor 41 and the second transistor 42 by changing the impedance of the first transistor 41 and the second transistor 42.

In one embodiment, the adjusting circuit 32 is specifically configured to: using the comparison result, the gate dc voltages of the first transistor 41 and the second transistor 42 are pulled up or down to control the on-states of the first transistor 41 and the second transistor 42, so as to adjust and equalize the first dc voltage and the second dc voltage. In practical application, the first dc voltage and the second dc voltage are not equal to each other due to temperature, process drift, or a change in working conditions.

In an embodiment, the voltage generating circuit 43 is specifically configured to generate at least one first bias dc voltage matched to the power level by using at least one resistor and at least one current source, where each first bias dc voltage controls one third transistor 44 and outputs the target output signal, so that the target output signal satisfies a preset linear relationship.

Here, the voltage generating circuit 43 may be connected in series through at least one resistor and a current source to obtain a series circuit, and at least one current source is introduced into a bypass of the series circuit, one end of each current source introduced into the bypass is connected to a connection point between the resistors, and the other end of each current source introduced into the bypass is connected to the dc power source of the bias circuit.

In practical application, when the power level of a target output signal output by the bias circuit is required to be larger, the direct current power supply of the bias circuit needs to be increased, here, at least one third transistor 44 is required to increase the withstand voltage, at least one first bias direct current voltage matched with the power level is generated by at least one resistor and at least one current source, each first bias direct current voltage controls one third transistor 44, and the target output signal is sequentially input from the source terminal of the third transistor 44 and output from the drain terminal of the third transistor 44, so that the target output signal meets the preset linear relation.

In an embodiment, the voltage generating circuit 43 is further configured to generate a second bias dc voltage matched to the power level, where the second bias dc voltage is used as the gate dc voltage of the first transistor 41 and the second transistor 42; the first bias direct current voltage and the second bias direct current voltage meet a preset condition; the second direct current voltage changes along with the changes of the first bias direct current voltage and the second bias direct current voltage.

The first bias direct-current voltage and the second bias direct-current voltage meet preset conditions, namely the difference value of the first bias direct-current voltage and the second bias direct-current voltage is adjusted through an adjustable resistor and a constant current source. That is, the difference between the first bias dc voltage and the second bias dc voltage is equal to the voltage drop across the adjustable resistor.

The number of the third transistors 44 is at least one, which can satisfy withstand voltage when increasing the dc power supply of the bias circuit, and can also provide a suitable dc input voltage range for the detection input terminal of the detection circuit 31, that is, when the bias circuit operates, when outputting target output signals of different power levels, it is necessary to select a suitable second dc voltage as the dc bias condition of the bias circuit.

In one embodiment, the bias circuit further comprises: an inductor, a direct current power supply; one end of the inductor is connected to the dc power supply, and the other end of the inductor is connected to the drain of the third transistor 44, wherein,

the inductor is used as an alternating current load;

and the direct current power supply is used for supplying power to the biasing circuit.

In the embodiment of the present invention, when the bias circuit works, when the bias circuit makes the gate-source dc voltages of the first transistor 41 and the second transistor 42 the same and the drain dc voltage the same, the ratio of the dc current flowing through the first transistor 41 to the dc current flowing through the second transistor 42 is always equal to the ratio of the sizes of the first transistor 41 and the second transistor 42, and the sizes (the widths of the channels) of the first transistor 41 and the second transistor 42 are related to the process, therefore, the control accuracy of the dc current can be improved, and more stable performance can be obtained in terms of power level and linearity; the drain dc voltage of the second transistor 42 varies with the variation of the first bias dc voltage and the second bias dc voltage, and the difference between the first bias dc voltage and the second bias dc voltage is equal to the voltage drop across the adjustable resistor.

The voltage generating circuit 43 generates at least one first bias direct current voltage matched with the power level by using at least one resistor and at least one current source, each first bias direct current voltage controls one third transistor 44, the target output signal is sequentially input from the source terminal of the third transistor 44 and output from the drain terminal of the third transistor 44, so that the target output signal meets a preset linear relation, the bias circuit can obtain more stable performance in the aspects of the power level and the linearity, and the debugging is more flexible.

When the second bias dc voltage changes due to the temperature, the adjusting circuit 32 can still ensure that the drain dc voltages of the first transistor 41 and the second transistor 42 are the same, so that the temperature influence can be offset;

EXAMPLE III

This embodiment is a specific application example of the circuit shown in fig. 4.

In the present embodiment, as shown in fig. 5, the bias circuit 51 includes: an NMOS tube Mref, an NMOS tube Mmir, an NMOS tube Mcas, an operational amplifier OPamp, a direct current source Iref, a direct current source Itrim, a resistor Rtrim, a resistor Rbias1, a capacitor Cbias1, a resistor Rbias2, a capacitor Cbias2, a resistor Rbias3, a capacitor Cbias3, an inductor L, a direct current power supply Vbat, an input alternating current signal RFin and an output power RFout; the grid of the NMOS tube Mref is connected with the grid of the NMOS tube Mmir through a resistor Rbias1 attenuating a small alternating current input signal RFin, the drain terminal of the NMOS tube Mref is connected with the positive phase input terminal of the operational amplifier OPamp, the drain terminal of the NMOS tube Mmir is connected with the negative phase input terminal of the operational amplifier OPamp through a resistor Rbias2, the NMOS tube Mref is connected with a direct current source Iref, the drain terminal of the NMOS tube Mmir is connected with the source terminal of the NMOS tube Mcas, the resistor Rbias1, the capacitor Cbias1, the resistor Rbias2, the capacitor Cbias2, the resistor Rbias3 and the capacitor Cbias3 form a low-pass filter for collecting a direct current signal; wherein,

the first transistor 41 is an NMOS transistor Mref;

the second transistor 42 is an NMOS transistor Mmir;

the voltage generation circuit 43 includes: a direct current source Itrim, a resistor Rtrim;

the third transistor 44 is an NMOS transistor Mcas;

the control circuit 45 includes: an operational amplifier OPamp.

The operating principle of the bias circuit shown in fig. 5 is:

the bias states of the NMOS tube Mref and the NMOS tube Mmir are adjusted through the operational amplifier OPamp, different bias direct currents can be obtained through adjusting the size of the direct current source Iref, and target output signals with different power levels can be obtained through the NMOS tube Mmir through the bias direct currents and the input alternating current signal RFin.

The specific process of the operational amplifier OPamp adjusting the bias states of the NMOS transistor Mref and the NMOS transistor Mmir includes:

when an alternating current signal RFin is input and the bias circuit works, the impedance of a direct current source Iref is much larger than the impedance of the source end of an NMOS tube Mcas, so that the total impedance of the drain end of the NMOS tube Mref is larger than the total impedance of the drain end of the NMOS tube Mmir. Therefore, the negative feedback loop has larger gain than the positive feedback loop, and the whole circuit is a negative feedback system. Wherein the negative feedback loop comprises: the operational amplifier OPamp is connected with the input end of the drain terminal of the NMOS tube Mref, the operational amplifier OPamp, the gate electrode of the NMOS tube Mref, the NMOS tube Mref and the drain terminal of the NMOS tube Mref; the positive feedback loop includes: the operational amplifier OPamp is connected with the input end of the drain end of the NMOS tube Mmir, the operational amplifier OPamp, the grid electrode of the NMOS tube Mmir, the NMOS tube Mmir and the drain end of the NMOS tube Mref; the negative feedback system comprises the negative feedback loop and a positive feedback loop.

When the second dc voltage (equivalent to the drain dc voltage of the NMOS transistor mm) is higher than the first dc voltage (equivalent to the drain dc voltage of the NMOS transistor Mref), the operational amplifier OPamp will drive the gate dc voltages of the NMOS transistor Mref and the NMOS transistor mm to decrease, so that the drain dc voltage of the NMOS transistor Mref and the drain dc voltage of the NMOS transistor mm will both increase, but the drain dc voltage of the NMOS transistor Mref will increase more, so that the drain dc voltage of the NMOS transistor Mref and the drain dc voltage of the NMOS transistor mm tend to be equal. When the second dc voltage (equivalent to the drain dc voltage of the NMOS transistor mm) is lower than the first dc voltage (equivalent to the drain dc voltage of the NMOS transistor Mref), the operational amplifier OPamp will drive the gate dc voltages of the NMOS transistor Mref and the NMOS transistor mm to increase, so that the drain dc voltage of the NMOS transistor Mref and the drain dc voltage of the NMOS transistor mm will both decrease, but the drain dc voltage of the NMOS transistor Mref decreases more, so that the drain dc voltage of the NMOS transistor Mref and the drain dc voltage of the NMOS transistor mm tend to be equal.

When the resistance Rtrim or Itrim is adjusted, the drain end direct current voltage of the NMOS tube Mmir is caused to change, the drain end direct current voltage of the NMOS tube Mref and the drain end direct current voltage of the NMOS tube Mmir generate a difference value, when the drain end direct current voltage of the NMOS tube Mmir is higher than the drain end direct current voltage of the NMOS tube Mref, the operational amplifier OPamp drives the gate end direct current voltage of the NMOS tube Mref and the gate end direct current voltage of the NMOS tube Mmir to be reduced, the drain end direct current voltage of the NMOS tube Mref and the drain end direct current voltage of the NMOS tube Mmir are both increased, but the drain end direct current voltage of the NMOS tube Mref is increased more; when the drain end direct current voltage of the NMOS tube Mmir is lower than the drain end direct current voltage of the NMOS tube Mref, the operational amplifier OPamp drives the gate end direct current voltages of the NMOS tube Mref and the NMOS tube Mmir to be increased, so that the drain end direct current voltage of the NMOS tube Mref and the drain end direct current voltage of the NMOS tube Mmir are both reduced, but the drain end direct current voltage of the NMOS tube Mref is reduced more; finally, the negative feedback system enables the drain end direct current voltage of the NMOS tube Mref and the drain end direct current voltage of the NMOS tube Mmir to be approximately equal.

When the gate-source direct current voltage and the drain direct current voltage of the NMOS tube Mmir and the NMOS tube Mref are equal, the direct current flowing through the NMOS tube Mmir is equal to the value of Iref multiplied by the ratio of the sizes of the NMOS tube Mref and the NMOS tube Mmir, and the direct current flowing through the NMOS tube Mmir is the bias direct current of the bias circuit.

The embodiment of the present invention provides a voltage generating circuit 43, which utilizes a dc current source Itrim, a resistor Rtrim, to generate a first bias dc voltage at the gate of Mcas, and generate a second bias dc voltage at the gate of Mref and Mmir, wherein the difference between the first bias dc voltage and the second bias dc voltage is the voltage on the resistor Rtrim. The gate of the Mcas is connected with the resistor Rtrim after being filtered by the resistor Rbias3 and the capacitor Cbias 3. The first bias direct-current voltage generates a gate-source direct-current voltage which subtracts the Mcas to obtain a drain terminal voltage (second direct-current voltage) of the Mmir, and the second direct-current voltage changes along with the changes of the first bias direct-current voltage and the second bias direct-current voltage.

Here, the voltage generation circuit 43 may generate the first bias dc voltage and the second bias dc voltage in the manners of the fourth embodiment and the fifth embodiment.

In the embodiment of the present invention, in the operation of the bias circuit, the hardware programmable dc current source Itrim and the resistor Rtirm are used to generate the adjusting voltage Vtrim, which is expressed by the following formula: vtrim is Itrim × Rtrim, so that the gate of the NMOS transistor Mcas has a controllable voltage Vtrim relative to the gate of the NMOS transistor mm, thereby controlling the drain dc voltages of the NMOS transistor Mref and the NMOS transistor mm, and allowing the drain dc voltage of the NMOS transistor Mref and the drain dc voltage of the NMOS transistor mm to follow each other, thereby greatly improving the dc control accuracy of the bias circuit;

since the voltage at one end of the resistor Rtrim is the same as the gate dc voltage of the NMOS transistor Mref, the dc current flowing through the resistor Rtrim is absorbed by the output terminal of the operational amplifier OPamp. Here, one end of the resistor Rtrim may be connected to the gate of the NMOS transistor Mref, or a resistor without dc current may be connected to the gate of the NMOS transistor Mref, so that the difference between the gate voltage of the NMOS transistor Mcas and the gate voltage of the NMOS transistor Mref and the NMOS transistor Mmir is determined only by the resistor Rtrim and the dc current source Itrim, which is more convenient for debugging;

by utilizing the programmable hardware direct current source Itrim and the programmable hardware direct current source Iref to cooperate with the adjustment of the bias states of the NMOS tube Mref and the NMOS tube Mmir in the bias circuit, the bias direct current and the bias direct voltage with better advantages can be respectively selected according to different power levels, so that the bias circuit obtains better performance in the aspects of power level, efficiency, linearity and the like.

Example four

In the present embodiment, as shown in fig. 6, the bias circuit includes: an NMOS tube Mref, an NMOS tube Mmir, an NMOS tube Mcas3, an NMOS tube Mcas4, an operational amplifier OPamp, a direct current source Iref, a direct current source Itrim, a resistor Rtrim1, a resistor Rtrim2, a resistor Rbias1, a capacitor Cbias1, a resistor Rbias2, a capacitor Cbias2, a resistor Rbias3, a capacitor Cbias3, a resistor Rbias4, a capacitor Cbias4, an inductor L, a direct current source Vbat, an input alternating current signal RFin and an output end RFout; the drain terminal of the NMOS tube Mref is connected with the positive phase input terminal of the operational amplifier OPamp, and the drain terminal of the NMOS tube Mmir is connected with the negative phase input terminal of the operational amplifier OPamp through a resistor Rbias 2; wherein,

the first transistor 41 is an NMOS transistor Mref;

the second transistor 42 is an NMOS transistor Mmir;

the voltage generation circuit 43 includes: a direct current source Itrim, a resistor Rtrim1 and a resistor Rtrim 2;

the third transistor 44 is an NMOS transistor Mcas3 and an NMOS transistor Mcas 4;

the control circuit 45 includes: an operational amplifier OPamp.

The operating principle of the bias circuit shown in fig. 6 is:

when an alternating current signal RFin is input and the bias circuit works, the impedance of a direct current source Iref is much larger than the impedance of the source end of an NMOS tube Mcas, so that the total impedance of the drain end of the NMOS tube Mref is larger than the total impedance of the drain end of the NMOS tube Mmir. Therefore, the negative feedback loop has larger gain than the positive feedback loop, and the whole circuit is a negative feedback system. Wherein the negative feedback loop comprises: the operational amplifier OPamp is connected with the input end of the drain terminal of the NMOS tube Mref, the operational amplifier OPamp, the gate electrode of the NMOS tube Mref, the NMOS tube Mref and the drain terminal of the NMOS tube Mref; the positive feedback loop includes: the operational amplifier OPamp is connected with the input end of the drain end of the NMOS tube Mmir, the operational amplifier OPamp, the grid electrode of the NMOS tube Mmir, the NMOS tube Mmir and the drain end of the NMOS tube Mmir; the negative feedback system comprises the negative feedback loop and a positive feedback loop.

By using a direct current source Itrim, a resistor Rtrim1 and a resistor Rtrim2, a first bias direct current voltage is generated at the gates of the NMOS transistor Mcas3 and the NMOS transistor Mcas4, respectively, a second bias direct current voltage is generated at the gates of the NMOS transistor Mref and the NMOS transistor Mmir, and the difference between the first bias direct current voltage and the second bias direct current voltage is the sum of the voltages of the resistor Rtrim1 and the resistor Rtrim 2.

The first bias dc voltage at the gate of the NMOS transistor Mcas4 subtracts the gate-source dc voltage at the NMOS transistor Mcas3 and the NMOS transistor Mcas4 to obtain the drain dc voltage (equivalent to the second dc voltage in the first embodiment) of the NMOS transistor Mmir, and the second dc voltage varies with the first bias dc voltage and the second bias dc voltage.

EXAMPLE five

In the present embodiment, as shown in fig. 7, the bias circuit includes: an NMOS tube Mref, an NMOS tube Mmir, an NMOS tube Mcas3, an NMOS tube Mcas4, an operational amplifier OPamp, a direct current source Iref, a direct current source Itrim1, a direct current source Itrim2, a resistor Rtrim1, a resistor Rtrim2, a resistor Rbias1, a capacitor Cbias1, a resistor Rbias2, a capacitor Cbias2, a resistor Rbias3, a capacitor Cbias3, a resistor Rbias4, a capacitor Cbias4, an inductor L, a direct current power supply Vbat, an input alternating current signal RFin and an output end RFout; the drain terminal of the NMOS tube Mref is connected with the positive phase input terminal of the operational amplifier OPamp, and the drain terminal of the NMOS tube Mmir is connected with the negative phase input terminal of the operational amplifier OPamp through a resistor Rbias 2; wherein,

the first transistor 41 is an NMOS transistor Mref;

the second transistor 42 is an NMOS transistor Mmir;

the voltage generation circuit 43 includes: direct current source Itrim1, direct current source Itrim2, resistor Rtrim1 and resistor Rtrim 2;

the control circuit 45 includes: an operational amplifier OPamp.

The operating principle of the bias circuit shown in fig. 7 is:

The direct current source Itrim1 and the resistor Rtrim1 are used for generating a first bias direct current voltage at the NMOS transistor Mcas3, the direct current source Itrim2, the resistor Rtrim1 and the resistor Rtrim2 are used for generating another first bias direct current voltage at the grid electrode of the NMOS transistor Mcas4, a second bias direct current voltage is generated at the grid electrodes of the NMOS transistor Mref and the NMOS transistor Mmir, the NMOS transistor Mcas3 and the NMOS transistor Mcas4 are respectively controlled through each first bias direct current voltage, the grid direct current voltages of the NMOS transistor Mcas3 and the NMOS transistor Mcas4 can be respectively debugged, and debugging is more flexible.

The first bias dc voltage at the gate of the NMOS transistor Mcas4 subtracts the gate-source dc voltages at the NMOS transistor Mcas3 and the NMOS transistor Mcas4 to obtain the drain dc voltage (corresponding to the second dc voltage in the first embodiment) of the NMOS transistor Mmir, and the second dc voltage varies with the first bias dc voltage and the second bias dc voltage.

EXAMPLE six

In the present embodiment, as shown in fig. 8, the bias circuit 81 includes: an NMOS tube Mref, an NMOS tube Mmir, an NMOS tube Mcas, an operational amplifier OPampA, a direct current source Iref, a direct current source Itrim, a resistor Rtrim, a resistor Rbias1, a capacitor Cbias1, a resistor Rbias2, a capacitor Cbias2, a resistor Rbias3, a capacitor Cbias3, an NMOS tube Mn1, a P-channel metal oxide semiconductor field effect transistor (PMOS) Mp1, an inductor L, a direct current power supply Vbat, an input alternating current signal RFin and an output end RFout; the drain terminal of the NMOS tube Mref is connected with the negative phase input terminal of the operational amplifier OPampA, and the drain terminal of the NMOS tube Mmir is connected with the positive phase input terminal of the operational amplifier OPampA through a resistor Rbias 2; wherein,

the first transistor 41 is an NMOS transistor Mref;

the second transistor 42 is an NMOS transistor Mmir;

the third transistor 44 is an NMOS transistor Mcas;

the control circuit 45 includes: an operational amplifier OPampA.

The operating principle of the bias circuit shown in fig. 8 is:

when an alternating current signal RFin is input and the bias circuit works, and due to the influence of temperature or other factors, when the grid direct current voltage of at least one of the NMOS tube Mref and the NMOS tube Mmir changes, the comparison result output by the output end of the operational amplifier OPamp is utilized, and the grid direct current voltage of the NMOS tube Mref and the grid direct current voltage of the NMOS tube Mmir are pulled up or pulled down, so that the conduction states of the NMOS tube Mref and the NMOS tube Mmir are controlled, and the first direct current voltage and the second direct current voltage are adjusted and are equal.

When the gate dc voltages of the NMOS transistor Mref and the NMOS transistor Mmir are large, the gate dc voltages of the NMOS transistor Mref and the NMOS transistor Mmir need to be pulled down, so that the gate dc voltages of the NMOS transistor Mref and the NMOS transistor Mmir can be ensured to be stable. The implementation process of the pull-down comprises the following steps: the comparison result output by the operational amplifier OPamp is used for driving the NMOS tube Mn1, and the source end of the NMOS tube Mn1 is grounded, so that the grid direct-current voltage of the NMOS tube Mref and the grid direct-current voltage of the NMOS tube Mmir can be pulled down;

when the gate dc voltages of the NMOS transistor Mref and the NMOS transistor Mmir are small, the gate dc voltages of the NMOS transistor Mref and the NMOS transistor Mmir need to be pulled up, so that the gate dc voltages of the NMOS transistor Mref and the NMOS transistor Mmir can be ensured to be stable. The implementation process of the pull-up comprises the following steps: the NMOS transistor Mn1 is driven by the comparison result to reduce the pull-down capability of the NMOS transistor Mn1, so that the gate dc voltages of the NMOS transistor Mref and the NMOS transistor Mmir rise. The PMOS tube Mp1 provides a bias direct current and a load to the NMOS tube Mn1, and the source end direct current of the PMOS tube Mp1 receives a path of bias direct current Ibias.

When an alternating current signal RFin is input and the bias circuit works, the impedance of a direct current source Iref is much larger than the impedance of the source end of an NMOS tube Mcas, so that the total impedance of the drain end of the NMOS tube Mref is larger than the total impedance of the drain end of the NMOS tube Mmir. Therefore, the negative feedback loop has larger gain than the positive feedback loop, and the whole circuit is a negative feedback system. Wherein the negative feedback loop comprises: the operational amplifier OPampA and the input end connected with the drain terminal of the NMOS tube Mref, the operational amplifier OPampA, the grid electrode of the NMOS tube Mn1, the drain terminal of the NMOS tube Mn1, the grid electrode of the NMOS tube Mref, the NMOS tube Mref and the drain terminal of the NMOS tube Mref; the positive feedback loop includes: the operational amplifier OPampA and the NMOS tube Mmir are connected with the drain end of the input end, the operational amplifier OPampA, the gate electrode of the NMOS tube Mn1, the drain end of the NMOS tube Mn1, the gate electrode of the NMOS tube Mmir, the NMOS tube Mmir and the drain end of the NMOS tube Mmir; the negative feedback system comprises the negative feedback loop and a positive feedback loop.

When the second dc voltage (equivalent to the drain dc voltage of the NMOS transistor mm) is higher than the first dc voltage (equivalent to the drain dc voltage of the NMOS transistor Mref), the operational amplifier opampapa drives the gate dc voltages of the NMOS transistor Mref and the NMOS transistor mm to decrease, so that the drain dc voltage of the NMOS transistor Mref and the drain dc voltage of the NMOS transistor mm will both increase, but the drain dc voltage of the NMOS transistor Mref increases more, so that the drain dc voltage of the NMOS transistor Mref and the drain dc voltage of the NMOS transistor mm tend to be equal. When the second dc voltage (equivalent to the drain dc voltage of the NMOS transistor mm) is lower than the first dc voltage (equivalent to the drain dc voltage of the NMOS transistor Mref), the operational amplifier opampapa drives the gate dc voltages of the NMOS transistor Mref and the NMOS transistor mm to increase, so that the drain dc voltage of the NMOS transistor Mref and the drain dc voltage of the NMOS transistor mm will both decrease, but the drain dc voltage of the NMOS transistor Mref decreases more, so that the drain dc voltage of the NMOS transistor Mref and the drain dc voltage of the NMOS transistor mm tend to be equal.

When the resistance Rtrim or Itrim is adjusted, the drain end direct current voltage of the NMOS tube Mmir is caused to change, the drain end direct current voltage of the NMOS tube Mref and the drain end direct current voltage of the NMOS tube Mmir generate a difference value, when the drain end direct current voltage of the NMOS tube Mmir is higher than the drain end direct current voltage of the NMOS tube Mref, the operational amplifier OPampA drives the gate end direct current voltage of the NMOS tube Mref and the gate end direct current voltage of the NMOS tube Mmir to be reduced, the drain end direct current voltage of the NMOS tube Mref and the drain end direct current voltage of the NMOS tube Mmir are both increased, but the drain end direct current voltage of the NMOS tube Mref is increased more; when the drain end direct current voltage of the NMOS tube Mmir is lower than the drain end direct current voltage of the NMOS tube Mref, the operational amplifier OPampA drives the gate end direct current voltages of the NMOS tube Mref and the NMOS tube Mmir to be increased, so that the drain end direct current voltage of the NMOS tube Mref and the drain end direct current voltage of the NMOS tube Mmir are both reduced, but the drain end direct current voltage of the NMOS tube Mref is reduced more; finally, the negative feedback system enables the drain end direct current voltage of the NMOS tube Mref and the drain end direct current voltage of the NMOS tube Mmir to be approximately equal.

The direct current source Itrim and the resistor Rtrim are utilized to generate a first bias direct current voltage at the grid electrode of the NMOS tube Mcas, a second bias direct current voltage is generated at the grid electrodes of the NMOS tube Mref and the NMOS tube Mmir, and the difference value between the first bias direct current voltage and the second bias direct current voltage is the voltage on the resistor Rtrim. The gate-source dc voltage on the NMOS transistor Mcas is subtracted from the first bias dc voltage to obtain the drain dc voltage (corresponding to the second dc voltage in the first embodiment) of the NMOS transistor Mmir, where the second dc voltage varies with the first bias dc voltage and the second bias dc voltage.

EXAMPLE seven

Based on the above embodiment circuit, the embodiment of the present invention further provides a control method, as shown in fig. 9, the method includes the following steps:

step 901: comparing the first direct current voltage with the second direct current voltage to obtain a comparison result; the first direct current voltage is the drain end direct current voltage of a first transistor of the bias circuit; the second direct current voltage is the direct current voltage of the drain terminal of the second transistor of the bias circuit.

Step 902: and adjusting the first direct current voltage and the second direct current voltage by using the comparison result so that the drain end direct current voltage of the first transistor is the same as the drain end direct current voltage of the second transistor in the working process of the biasing circuit.

The grid electrode of the first transistor is connected with the grid electrode of the second transistor through a resistor for attenuating alternating current signals; the first transistor and the second transistor amplify an input reference direct current of the direct current bias circuit to obtain a bias direct current, and the second transistor obtains a target output signal based on an input signal of the bias circuit by using the bias direct current.

The bias circuit can generate different output powers, and meanwhile, the input reference direct current and the bias states of the first transistor and the second transistor are adjusted according to actual requirements, so that the bias circuit obtains more stable performance in the aspects of power level and linearity.

In practical application, when the bias circuit works and the grid direct-current voltage of the first transistor changes to cause the drain direct-current voltages of the first transistor and the second transistor to change, the first direct-current voltage (equivalent to the drain direct-current voltage of the first transistor) and the second direct-current voltage (equivalent to the drain direct-current voltage of the second transistor) are compared to obtain a comparison result; and controlling the direct current voltage of the grid electrodes of the first transistor and the second transistor by using the comparison result, and realizing that the direct current voltage of the drain end of the first transistor is equal to the direct current voltage of the drain end of the second transistor by adjusting the impedance of the first transistor and the impedance of the second transistor.

When the drain end direct current voltage of the second transistor changes and the drain end direct current voltage of the first transistor keeps unchanged, comparing the first direct current voltage (equivalent to the drain end direct current voltage of the first transistor) with the second direct current voltage (equivalent to the drain end direct current voltage of the second transistor) to obtain a comparison result; and controlling the direct current voltage of the grid electrodes of the first transistor and the second transistor by using the comparison result, and realizing that the direct current voltage of the drain end of the first transistor changes along with the change of the direct current voltage of the drain end of the second transistor by adjusting the impedance of the first transistor and the impedance of the second transistor, thereby finally ensuring that the direct current voltage of the drain end of the first transistor is equal to the direct current voltage of the drain end of the second transistor.

When the gate-source direct current voltage of the first transistor is the same as the gate-source direct current voltage of the second transistor, and the drain direct current voltage of the first transistor is also the same as the drain direct current voltage of the second transistor, the ratio of the direct current flowing through the first transistor to the direct current flowing through the second transistor is equal to the ratio of the size of the first transistor to the size of the second transistor.

In one embodiment, the adjusting the first dc voltage and the second dc voltage using the comparison result includes:

and controlling the conduction degree of the first transistor and the second transistor by using the comparison result so as to adjust the first direct current voltage and the second direct current voltage to be equal.

and controlling the conduction degree of the first transistor and the second transistor by pulling up or pulling down the grid direct current voltage of the first transistor and the grid direct current voltage of the second transistor by using the comparison result so as to adjust the first direct current voltage and the second direct current voltage to be equal. In practical application, the first direct current voltage and the second direct current voltage are not equal to each other due to temperature, process drift or the influence of changes of working conditions.

Example eight

In order to implement the bias circuit, an embodiment of the present invention further provides an implementation method of a bias circuit, as shown in fig. 10, the method includes the following steps:

step 1001: the first transistor and the second transistor amplify input reference direct current of a bias circuit to obtain bias direct current, and the second transistor obtains a target output signal by using the bias direct current and based on an input signal of the bias circuit;

step 1002: controlling a third transistor to output the target output signal by using the generated first bias direct-current voltage matched with the power grade, so that the target output signal meets a preset linear relation;

in the working process of the bias circuit, comparing the first direct-current voltage with the second direct-current voltage to obtain a comparison result; the first direct current voltage is the drain end direct current voltage of the first transistor; the second direct current voltage is the direct current voltage of the drain terminal of the second transistor; and adjusting the first direct current voltage and the second direct current voltage by using the comparison result so that the drain end direct current voltage of the first transistor is the same as the drain end direct current voltage of the second transistor in the working process of the biasing circuit.

In practical application, the drain terminal direct current voltage of the first transistor and the drain terminal direct current voltage of the second transistor follow each other in the operation of the bias circuit by adjusting the bias states of the first transistor and the second transistor, namely adjusting the first direct current voltage and the second direct current voltage by using the comparison result of the first direct current voltage and the second direct current voltage; then, by adjusting the input reference direct current of the bias circuit, the first transistor and the second transistor can amplify the input reference direct current to generate different bias direct currents; the second transistor can obtain target output signals with different power levels based on the input signal of the bias circuit by using the bias direct current, and the target output signals are output by using the third transistor, so that the bias circuit can obtain more stable performance in the aspects of power level and linearity.

In one embodiment, the adjusting the first dc voltage and the second dc voltage using the comparison result includes: and controlling the conduction degrees of the first transistor and the second transistor by using the comparison result so as to adjust the first direct current voltage and the second direct current voltage.

In one embodiment, the adjusting the first dc voltage and the second dc voltage using the comparison result includes: and controlling the conduction degree of the first transistor and the second transistor by pulling up or pulling down the grid direct-current voltage of the first transistor and the grid direct-current voltage of the second transistor by using the comparison result so as to adjust the first direct-current voltage and the second direct-current voltage.

In an embodiment, the method further comprises:

generating a second bias direct-current voltage matched with the power grade, wherein the second bias direct-current voltage is used as the grid direct-current voltage of the first transistor and the grid direct-current voltage of the second transistor; the first bias direct current voltage and the second bias direct current voltage meet a preset condition; the second direct current voltage changes along with the changes of the first bias direct current voltage and the second bias direct current voltage. The first bias direct-current voltage and the second bias direct-current voltage meet preset conditions, namely the difference value of the first bias direct-current voltage and the second bias direct-current voltage is adjusted through an adjustable resistor and a constant current source. That is, the difference between the first bias dc voltage and the second bias dc voltage is equal to the voltage drop across the adjustable resistor.

In an embodiment, the method further comprises:

and generating at least one first bias direct current voltage matched with the power grade by using at least one resistor and at least one current source, wherein each first bias direct current voltage controls one third transistor and outputs a target output signal, so that the target output signal meets a preset linear relation.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A control circuit for use in a bias circuit, the bias circuit comprising: a first transistor and a second transistor; the grid electrode of the first transistor is connected with the grid electrode of the second transistor; the first transistor and the second transistor are transistors which amplify an input reference direct current of the bias circuit to obtain a bias direct current, and the second transistor obtains a target output signal based on an input signal of the bias circuit by using the bias direct current; the control circuit includes:

2. The control circuit of claim 1, wherein the adjustment circuit is an adjustment circuit for adjusting the first DC voltage and the second DC voltage by controlling the conduction degree of the first transistor and the second transistor according to the comparison result.

3. The control circuit of claim 1, wherein the adjustment circuit is an adjustment circuit for adjusting the first dc voltage and the second dc voltage by controlling the conduction levels of the first transistor and the second transistor by pulling up or pulling down the dc voltages at the gates of the first transistor and the second transistor according to the comparison result.

4. A bias circuit, comprising:

a first transistor;

5. The bias circuit of claim 4, wherein the adjustment circuit is an adjustment circuit for adjusting the first DC voltage and the second DC voltage by controlling the conduction degree of the first transistor and the second transistor according to the comparison result.

6. The bias circuit of claim 4, wherein the adjusting circuit is an adjusting circuit for adjusting the first DC voltage and the second DC voltage by controlling the conduction degree of the first transistor and the second transistor by pulling up or pulling down the DC voltages of the gates of the first transistor and the second transistor according to the comparison result.

7. The bias circuit of claim 4,

the voltage generating circuit is a voltage generating circuit which generates a second bias direct-current voltage matched with the power grade, and the second bias direct-current voltage is used as grid direct-current voltages of the first transistor and the second transistor; the first bias direct current voltage and the second bias direct current voltage meet a preset condition; the second direct current voltage changes along with the changes of the first bias direct current voltage and the second bias direct current voltage.

8. The bias circuit of claim 4,

the voltage generating circuit is a voltage generating circuit which generates at least one first bias direct current voltage matched with the power grade by using at least one resistor and at least one current source, and each first bias direct current voltage controls one third transistor and outputs a target output signal so that the target output signal meets a preset linear relation.