CN206922750U - A kind of three-phase narrow-band high-speed power line carrier module realized using single-chip - Google Patents
A kind of three-phase narrow-band high-speed power line carrier module realized using single-chip Download PDFInfo
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- CN206922750U CN206922750U CN201720897295.6U CN201720897295U CN206922750U CN 206922750 U CN206922750 U CN 206922750U CN 201720897295 U CN201720897295 U CN 201720897295U CN 206922750 U CN206922750 U CN 206922750U
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Abstract
The utility model describes a kind of three-phase narrow-band high-speed power line carrier module realized using single-chip, it includes model STCOMET main process task chip, the main process task chip is connected by the first SPI interface with FLASH memory modules, the main process task chip is also connected by the first I2C interface with EEPROM memory modules, and described main process task chip, FLASH memory modules and EEPROM memory modules are powered by 3.3V external power sources；The main process task chip also by bi-directional communication interface with couple and filter circuit module connect.Power line carrier, PLC of the present utility model uses OFDM modulation techniques, flank speed is up to 128kbps, without changing hardware, realize the protocol stack completely to communicate, different standardization areas can be applied to, I2C is also provided and SPI interface is used to be communicated with other peripheral hardwares, there is provided control and collection outside analog interface and digital interface realization, OEM or ODM can be carried out for his manufacturer.
Description
Technical field
It the utility model is related to a kind of high-speed power carrier module, especially a kind of three-phase arrowband realized using single-chip
High-speed power carrier module, belongs to internet of things field.
Background technology
In application fields such as remote meter reading, Street lamps controls, power line carrier, PLC has anti-interference strong, networking than radio communication
The huge advantages such as success rate height, there is boundless application prospect.In the development of the electrical carrier communication technology, first generation electricity
Power carrier wave uses FSK modulation technology, has the shortcomings that speed is low, poor anti-interference, makes the Consumer's Experience of product can not improve, hinders
The application of power line carrier, PLC.Second generation power carrier uses OFDM modulation techniques, has anti-interference strong, traffic rate
The advantage of high, networking flexibility and information security, being widely regarded as current intelligent grid circle, most securely and reliably and most cost is imitated
The communication pattern of benefit, therefore carried out first G3-PLC Applied D emonstrations at the beginning of south electric network 2015 in Shenzhen.
But because the development difficulty of power line carrier, PLC is larger, therefore domestic electrical carrier module is main still at present
It is current also still immature even if there is the research based on OFDM modulation techniques based on FSK adjustment technologies.In addition, the core of domestic manufacturers
Piece is the agreement for realizing physical layer and low MAC layer, can only realize simplex mode, and not only communication efficiency is low, and
Extension is also extremely difficult.
Therefore, the PLC technology that ammeter industry mainly uses at present is still based on FSK modulation technology, really transmission
Speed is 300bps ~ 600bps, this technology poor anti jamming capability, and meter reading success rate can not still make customer satisfaction completely.At present
Although also there is a small number of products for using OFDM modulation techniques, speed is only in 1kbps, and without the raising of essence, and technology is still
Non- full maturity.As can be seen that current power carrier only realizes CSMA-CA algorithms substantially, for bus contention, in this base
Simple routing algorithm is realized on plinth, the function of protocol stack is very weak, therefore can only be simplex, causes user's body
Test excessively poor, also seriously limit the popularization of power carrier product.
Utility model content
For above-mentioned deficiency of the prior art, main purpose of the present utility model is solve existing current power carrier
Technical communication speed is relatively low, and extension it is highly difficult the problem of, and provide it is a kind of with high-speed communication and be easy to extension adopt
The three-phase narrow-band high-speed power line carrier module realized with single-chip.
The technical solution of the utility model：A kind of three-phase narrow-band high-speed power line carrier module realized using single-chip, its
It is characterised by, include model STCOMET main process task chip, the main process task chip passes through the first SPI interface and FLASH
Memory module is connected, and the main process task chip is also connected by the first I2C interface with EEPROM memory modules, described main process task
Chip, FLASH memory modules and EEPROM memory modules are powered by 3.3V external power sources；The main process task chip is also by double
To communication interface with couple and filter circuit module connect, described coupling and filter circuit module include transformer T1, transformation
The device T1 pin of primary coil first connects one end of inductance L1 one end, inductance L2 one end and inductance L3, inductance L1 respectively
The other end connect electric capacity C1 one end and diode TVS1 negative pole respectively, the inductance L2 other end connects electric capacity C2's respectively
One end and diode TVS2 negative pole, the inductance L3 other end connect electric capacity C3 one end and diode TVS3 negative pole respectively,
The A phases of the electric capacity C1 outside three phase mains of other end connection, the B phases of the electric capacity C2 outside three phase mains of other end connection, electric capacity
The C phases of the C3 outside three phase mains of other end connection, diode TVS1 positive pole connect diode TVS2 positive pole, two poles respectively
The primary coil second pin of pipe TVS3 positive pole, the zero line N of outside three phase mains and transformer T1；Transformer T1 secondary wire
Enclose the first pin and connect diode TVS5 negative pole and resistance R2 one end, transformer T1 secondary coil second pin point respectively
Not Lian Jie diode TVS4 negative pole and resistance R1 one end, diode TVS5 positive pole is connected simultaneously with diode TVS4 positive pole
Ground connection, the resistance R2 other end connect diode TVS6 negative pole, inductance L5 one end, electric capacity C7 one end, electric capacity C6 respectively
One end and electric capacity C5 one end, the electric capacity C5 other end is connected with the TX interfaces on main process task chip, the resistance R1 other end
Diode TVS6 positive pole, the inductance L5 other end, the electric capacity C7 other end, electric capacity C8 one end and electric capacity C10 is connected respectively
One end, the electric capacity C10 other end is connected with the RX interfaces on main process task chip；The electric capacity C8 other end is another with electric capacity C6's
End is connected and is grounded.
The utility model realizes power line carrier module using STCOMET single-chips, and the chip is double ARM core chips,
One of kernel realizes physical layer and low MAC layer function, i.e. OFDM modulation techniques and CSMA-CA and MESH organization algorithms.
Another ARM kernel is used for realizing complete protocol stack, including G3 protocol stacks and lwIP protocol stacks.Communication is externally provided to connect
Mouth, digital interface and analog interface etc..
Change the parameter of coupling and some devices of filter circuit, it is possible to support different frequency ranges, you can to cover
CENELEC-A, FCC and ARIB frequency range, flank speed is up to 128kbps, without changing hardware.
Universal electric power carrier module is externally provided outside serial ports communicated with ppu, also provides I2C and SPI interface
For being communicated with other peripheral hardwares, there is provided control and collection outside analog interface and digital interface realization, can be for his factory
Business carries out OEM or ODM.In the chips, lwIP protocol stacks have been transplanted, Internet is realized on G3 protocol stacks basis（IPv6）
And transport layer（UDP and ICMP）, realize the protocol stack completely to communicate.Also entered simultaneously using FreeRTOS real time operating systems
Row software architecture, it is comprehensive using queue, signal, task dispatching technology, the coupling of program is removed, makes program that there is extension well
Property, adapt in different application scenarios.Can be by corresponding firmware code remote download into chip, it is possible to realize different
Standard, such as ITU-T G.9903 (G3-PLC), ITU-T G.9904 (PRIME), IEEE P1901.2, can be applied to not
Same standardization areas.
Optimally, the model M25P16-VMN6P of the FLASH memory modules.
Optimally, the model AT24C512 of the EEPROM memory modules.
Optimally, the second SPI interface and the second I2C interface are additionally provided with the main process task chip.
Optimally, the first power input interface, second source input interface and the 3rd are provided with the main process task chip
Power input interface, first power input interface access 3.3V external power sources, and second source input interface is accessed outside 5V
Power supply, the 3rd power input interface access 15V external power sources.
Optimally, serial ports, PWM interfaces, analog signal interface and data signal are additionally provided with the main process task chip to connect
Mouthful.
Relative to prior art, the utility model has the advantages that：
1st, power line carrier, PLC of the present utility model uses OFDM modulation techniques, can cover CENELEC-A, FCC and
ARIB frequency ranges, flank speed, without changing hardware, have higher traffic rate up to 128kbps.
2nd, software architecture is carried out due to employing FreeRTOS real time operating systems in main process task chip, synthesis uses team
Row, signal, task dispatching technology, the coupling of program is removed, makes program that there is good autgmentability, is adapted in different applications
Scene transplants lwIP protocol stacks, and Internet is realized on G3 protocol stacks basis（IPv6）And transport layer（UDP and ICMP）, realize
The protocol stack of complete communication.
3rd, the utility model downloads to corresponding firmware code inside SPI FLASH in chip, it is possible to realizes different
Standard, such as ITU-T G.9903 (G3-PLC), ITU-T G.9904 (PRIME), IEEE P1901.2, can be applied to
Different standardization areas.
4th, the utility model is externally provided outside serial ports communicated with ppu using universal electric power carrier module, also
I2C and SPI interface is provided to be used to be communicated with other peripheral hardwares, there is provided analog interface and digital interface realize outside control and
Collection, OEM or ODM can be carried out for his manufacturer.
Brief description of the drawings
Fig. 1 is a kind of circuit structure for the three-phase narrow-band high-speed power line carrier module realized using single-chip of the utility model
Block diagram.
Fig. 2 is the circuit theory diagrams of coupling and filter circuit module in the utility model.
In figure, 1-main process task chip, 2-FLASH memory modules, 3-EEPROM memory modules, 4-coupling and filtered electrical
Road module.
Embodiment
The utility model is described in further detail with reference to the accompanying drawings and detailed description.
As depicted in figs. 1 and 2, a kind of three-phase narrow-band high-speed power carrier mould realized using single-chip of the present utility model
Block, includes model STCOMET main process task chip 1, and the main process task chip 1 is stored by the first SPI interface and FLASH
Module 2 is connected, and the main process task chip 1 is also connected by the first I2C interface with EEPROM memory modules 3, described main process task
Chip 1, FLASH memory modules 2 and EEPROM memory modules 3 are powered by 3.3V external power sources；The main process task chip 1 is also logical
Cross bi-directional communication interface and couple and filter circuit module 4 connects, described coupling and filter circuit module 4 include transformer
T1, transformer the T1 pin of primary coil first connect one end of inductance L1 one end, inductance L2 one end and inductance L3 respectively,
The inductance L1 other end connects electric capacity C1 one end and diode TVS1 negative pole respectively, and the inductance L2 other end connects electricity respectively
Hold C2 one end and diode TVS2 negative pole, the inductance L3 other end connects electric capacity C3 one end and diode TVS3 respectively
Negative pole, the A phases of the electric capacity C1 outside three phase mains of other end connection, the B phases of the electric capacity C2 outside three phase mains of other end connection,
The C phases of the electric capacity C3 outside three phase mains of other end connection, diode TVS1 positive pole connect respectively diode TVS2 positive pole,
The primary coil second pin of diode TVS3 positive pole, the zero line N of outside three phase mains and transformer T1；Transformer T1 time
The level pin of coil first connects diode TVS5 negative pole and resistance R2 one end respectively, and transformer T1 secondary coil second draws
Pin connects diode TVS4 negative pole and resistance R1 one end, diode TVS5 positive pole and diode TVS4 positive pole phase respectively
Connect and be grounded, the resistance R2 other end connects diode TVS6 negative pole, inductance L5 one end, electric capacity C7 one end, electricity respectively
Hold C6 one end and electric capacity C5 one end, the electric capacity C5 other end is connected with the TX interfaces on main process task chip, and resistance R1's is another
One end connects diode TVS6 positive pole, the inductance L5 other end, the electric capacity C7 other end, electric capacity C8 one end and electric capacity respectively
C10 one end, the electric capacity C10 other end are connected with the RX interfaces on main process task chip；The electric capacity C8 other end is with electric capacity C6's
The other end is connected and is grounded.
In the utility model, the model M25P16-VMN6P of the FLASH memory modules 2.The EEPROM stores mould
The model AT24C512 of block 3.The second SPI interface and the second I2C interface are additionally provided with the main process task chip 1.Described
Main process task chip 1 is provided with the first power input interface, second source input interface and the 3rd power input interface, and described first
Power input interface accesses 3.3V external power sources, second source input interface access 5V external power sources, the 3rd power input interface
Access 15V external power sources.Serial ports, PWM interfaces, analog signal interface and data signal are additionally provided with the main process task chip 1
Interface.
In the utility model, A phase, B phase, C phase and zero line N are connected with coupling transformer, and coupling transformer passes through filtered electrical
Road, what filter circuit came out sends and receives signal and is connected with main process task chip.Here coupling transformer and filter circuit integrate
It is coupling and filter circuit module 4 afterwards.It is main process chip power supply that outside provides 3.3V, 5V and 15V three-way power for module,
Wherein 3.3V also powers for FLASH memory modules 2 and EEPROM memory modules 3.Main process task chip 1 is the core of whole module.
It is internally integrated AFE(analog front end), realizes analog-to-digital conversion and filtering of power carrier signal etc..It is internally integrated metering module, realizes
The collection of the parameters such as voltage, electric current, power.It is internally integrated two ARM kernels, one of kernel be used to realizing physical layer and
Low MAC layer function, i.e. OFDM modulation techniques and CSMA-CA and MESH organization algorithms.Another ARM kernel is used for realizing completely
Protocol stack, including G3 protocol stacks and lwIP protocol stacks etc..In addition, it also provides abundant peripheral hardware, such as SPI interface, I2C connects
Mouth, serial ports etc..
Main process task chip 1 is attached by SPI interface and FLASH memory modules 2, and FLASH memory modules 2 are used to store
The data that power carrier uses, such as power carrier configuration information, routing table etc..Main process task chip 1 by I2C interface with
EEPROM memory modules 3 are attached, and EEPROM memory modules 3 are used to store application data, as electric parameter, application configuration are joined
Number etc..
Main process task chip 1 externally provides serial ports, is attached with ppu, applications is realized power carrier
Transmitting-receiving etc..Main process task chip 1 externally also provides I2C and SPI interface, can be attached with other external equipments.Main process task core
Piece 1 externally provides pwm signal, can be used for the control of external equipment, such as LED light modulation.Main process task chip 1 externally provides mould
Intend interface, realize the collection of analog signal.Main process task chip 1 externally provides digital interface, realizes the collection sum of data signal
Control of word equipment etc..
When coupling and filter circuit module 4 work, the power carrier signal from three-phase is coupled to AFE(analog front end) processing.
The data for needing to send also are sent on three-phase by same AFE(analog front end) through over-coupled transformer.AFE(analog front end) receives brewed
Good data signal is amplified, it would be desirable to which the data of transmission are sent on three-phase by coupling transformer.AFE(analog front end) passes through
Coupling transformer receives the power carrier data on three-phase, and the data received are filtered etc. with relevant treatment and is converted into counting
Word signal.
Coupling and filter circuit module 4 mainly realize coupling and the filtering process of power carrier signal, change coupling and filter
The parameter of some devices of wave circuit, it is possible to support different frequency ranges, you can to cover CENELEC-A, FCC and ARIB frequency range,
Flank speed is up to 128kbps, without changing hardware.
Coupling and the operation principle of filter circuit module 4：Inductance L1 and electric capacity C1 is used for the decompression and filtering of A phases.Similarly, it is electric
Feel decompression and filtering that L2 and electric capacity C2 is used for B phases.Inductance L3 and electric capacity C3 is used for the decompression and filtering of C phases.Diode TVS1,
Diode TVS2 and diode TVS3 is for Anti-surging processing.Three-phase signal just obtains power carrier after over-coupled transformer T1
Signal.Diode TVS4, diode TVS5 and the diode TVS6 of coupling transformer secondary end are also used for Anti-surging processing.Inductance
L5, electric capacity C5, electric capacity C6, electric capacity C7, electric capacity C8, electric capacity C10 form filter circuit.Change inductance L5, electric capacity C5, electric capacity C6,
Electric capacity C7, electric capacity C8, electric capacity C10, inductance L1, inductance L2, inductance L3 parameter value, it is possible to different frequency ranges is supported, without
Need to change hardware.
It should be noted that main process task chip 1 of the present utility model carries out software using FreeRTOS real time operating systems
Framework, it is comprehensive using queue, signal, task dispatching technology, the coupling of program is removed, makes program that there is good autgmentability, energy
It is adapted to different application scenarios transplanting lwIP protocol stacks, Internet is realized on G3 protocol stacks basis（IPv6）And transport layer
（UDP and ICMP）, realize the protocol stack completely to communicate.The memory space of FLASH memory modules 2 is 2MB, can be not only used for depositing
The data of G3 protocol stacks are stored up, can be also used for storing firmware, corresponding firmware code can be downloaded in FLASH memory modules 2
In the chip of face, it is possible to realize different standards, as ITU-T G.9903 (G3-PLC), ITU-T G.9904 (PRIME),
IEEE P1901.2 etc., different standardization areas can be applied to.
Key point of the present utility model is, the application of power carrier is realized using single-chip, is completed using the chip
The processing of power carrier AFE(analog front end), the processing such as collection, the metering of electric parameter are completed using the chip.Using the one of the chip
Individual kernel, realize OFDM modulation /demodulation, CSMA-CA algorithms, networking and routing algorithm etc..Using another kernel of the chip
Realize processing of G3 protocol stacks, lwIP protocol stacks etc..
Change the parameter of coupling and some devices of filter circuit, it is possible to support different frequency ranges, you can to cover
CENELEC-A, FCC and ARIB frequency range, flank speed is up to 128kbps, without changing hardware.
Software architecture is carried out using FreeRTOS real time operating systems, it is comprehensive using queue, signal, task dispatching technology, go
Except the coupling of program, make program that there is good autgmentability, adapt to transplant lwIP protocol stacks in different application scenarios,
G3 protocol stacks realize Internet on basis（IPv6）And transport layer（UDP and ICMP）, realize the protocol stack completely to communicate.
Corresponding firmware code is downloaded to inside SPI FLASH in chip, it is possible to realize different standards, such as ITU-T G.9903
(G3-PLC), ITU-T G.9904 (PRIME), IEEE P1901.2 etc., can be applied to different standardization areas.
It should be noted that above example is only to illustrate technical solutions of the utility model rather than restriction technologies scheme,
Although applicant is explained in detail with reference to preferred embodiment to the utility model, one of ordinary skill in the art should manage
Solution, those to technical solutions of the utility model carry out modification or equivalent substitution, it is impossible to depart from the technical program objective and
Scope, it all should cover among the utility model claims scope.
Claims (6)
1. a kind of three-phase narrow-band high-speed power line carrier module realized using single-chip, it is characterised in that including model
STCOMET main process task chip（1）, the main process task chip（1）Pass through the first SPI interface and FLASH memory modules（2）Even
Connect, the main process task chip（1）Also pass through the first I2C interface and EEPROM memory modules（3）Connection, described main process task chip
（1）, FLASH memory modules（2）With EEPROM memory modules（3）Powered by 3.3V external power sources；The main process task chip（1）
Also by bi-directional communication interface with coupling and filter circuit module（4）Connection, described coupling and filter circuit module（4）Including
Transformer T1, transformer the T1 pin of primary coil first connect inductance L1 one end, inductance L2 one end and inductance L3 respectively
One end, the inductance L1 other end connects electric capacity C1 one end and diode TVS1 negative pole, the inductance L2 other end point respectively
Not Lian Jie electric capacity C2 one end and diode TVS2 negative pole, the inductance L3 other end connects electric capacity C3 one end and two poles respectively
Pipe TVS3 negative pole, the A phases of the electric capacity C1 outside three phase mains of other end connection, the electric capacity C2 outside three-phase electricity of other end connection
The B phases in source, the C phases of the electric capacity C3 outside three phase mains of other end connection, diode TVS1 positive pole connect diode respectively
TVS2 positive pole, diode TVS3 positive pole, the zero line N of outside three phase mains and transformer T1 primary coil second pin；
The transformer T1 pin of secondary coil first connects diode TVS5 negative pole and resistance R2 one end, transformer T1 time respectively
Level coil second pin connects diode TVS4 negative pole and resistance R1 one end, diode TVS5 positive pole and diode respectively
TVS4 positive pole is connected and is grounded, and the resistance R2 other end connects diode TVS6 negative pole, inductance L5 one end, electric capacity respectively
One end of C7 one end, electric capacity C6 one end and electric capacity C5, the electric capacity C5 other end are connected with the TX interfaces on main process task chip,
The resistance R1 other end connects diode TVS6 positive pole, the inductance L5 other end, the electric capacity C7 other end, electric capacity C8 respectively
One end and electric capacity C10 one end, the electric capacity C10 other end are connected with the RX interfaces on main process task chip；The electric capacity C8 other end
It is connected and is grounded with the electric capacity C6 other end.
2. a kind of three-phase narrow-band high-speed power line carrier module realized using single-chip according to claim 1, its feature
It is, the FLASH memory modules（2）Model M25P16-VMN6P.
3. a kind of three-phase narrow-band high-speed power line carrier module realized using single-chip according to claim 2, its feature
It is, the EEPROM memory modules（3）Model AT24C512.
4. a kind of three-phase narrow-band high-speed power line carrier module realized using single-chip according to claim 3, its feature
It is, in the main process task chip（1）On be additionally provided with the second SPI interface and the second I2C interface.
5. a kind of three-phase narrow-band high-speed power line carrier module realized using single-chip according to claim 4, its feature
It is, in the main process task chip（1）It is provided with the first power input interface, second source input interface and the 3rd power input
Interface, the first power input interface access 3.3V external power sources, second source input interface access 5V external power sources, the 3rd
Power input interface accesses 15V external power sources.
6. a kind of three-phase narrow-band high-speed power line carrier module realized using single-chip according to claim 5, its feature
It is, in the main process task chip（1）On be additionally provided with serial ports, PWM interfaces, analog signal interface and digital signal interface.
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| CN201720897295.6U CN206922750U (en) | 2017-07-24 | 2017-07-24 | A kind of three-phase narrow-band high-speed power line carrier module realized using single-chip |
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| CN201720897295.6U CN206922750U (en) | 2017-07-24 | 2017-07-24 | A kind of three-phase narrow-band high-speed power line carrier module realized using single-chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111722527A (en) * | 2020-07-07 | 2020-09-29 | 电子科技大学 | Universal configurable digital control chip based on fuzzy self-adaptive PID |
-
2017
- 2017-07-24 CN CN201720897295.6U patent/CN206922750U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111722527A (en) * | 2020-07-07 | 2020-09-29 | 电子科技大学 | Universal configurable digital control chip based on fuzzy self-adaptive PID |
| CN111722527B (en) * | 2020-07-07 | 2021-12-10 | 电子科技大学 | Universal configurable digital control chip based on fuzzy self-adaptive PID |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder |
Address after: 400031 moonlight village 7-12, new street, Dadukou District, Chongqing Patentee after: Qin Long Address before: 400031 No. 176 Tong Street, Tong Jia Qiao, Shapingba District, Chongqing. Patentee before: Qin Long |
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| CP02 | Change in the address of a patent holder | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180123 Termination date: 20210724 |
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| CF01 | Termination of patent right due to non-payment of annual fee |