CN206892260U - A kind of phase tracking device of instrument for measuring partial discharge - Google Patents
A kind of phase tracking device of instrument for measuring partial discharge Download PDFInfo
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- CN206892260U CN206892260U CN201720768628.5U CN201720768628U CN206892260U CN 206892260 U CN206892260 U CN 206892260U CN 201720768628 U CN201720768628 U CN 201720768628U CN 206892260 U CN206892260 U CN 206892260U
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Abstract
The utility model overcomes the defects of phase alignment of existing instrument for measuring partial discharge, there is provided a kind of phase tracking device of new instrument for measuring partial discharge.The utility model includes phase acquisition module and phase checking module, by the way that the time of mistake 0 of phase acquisition module and the time of mistake 0 of phase checking module are compared, the initial phase at phase acquisition module counter can be released, so as to reach the purpose of phase tracking.The utility model is more accurately detected to phase, and the precision than prior art improves a lot, simple and efficient to handle, and the shelf depreciation test to electrical equipment has good booster action.
Description
Technical field
Phase tracking apparatus field is the utility model is related to, more particularly, to a kind of phase of instrument for measuring partial discharge
Follow-up mechanism.
Background technology
The new high voltage electric equipment for designing and manufacturing, the weak ring in insulation can be found in time by measurement of partial discharge
Section, prevent design and the mistake in manufacturing process and the improper use of material.Shelf depreciation test is to differentiate product insulation or set
A kind of important method of standby operational reliability.It can find the equipment deficiency that pressure test can not be found.Shelf depreciation is tested
One of big event of current power equipment preventive trial.
In shelf depreciation test, because the test point and shelf depreciation test point of instrument for measuring partial discharge are distant,
It is inconsistent to there is phase, the problem of shelf depreciation test point phase can not be examined.Existing way is to pass through real-time timepiece chip
The method of intercept signal zero crossing timing reaches the check purpose of phase.But the phase error of this method is close to 10 degree,
Accuracy deficiency, have impact on the test effect of instrument for measuring partial discharge.
Utility model content
The utility model overcomes the defects of phase alignment of above-mentioned existing instrument for measuring partial discharge, there is provided one
The phase tracking device of the new instrument for measuring partial discharge of kind, can more accurately be detected to phase.The letter of the utility model structure
It is single, it is simple and efficient to handle, it is applicable to a variety of environment.
In order to solve the above technical problems, the technical solution of the utility model is as follows：
A kind of phase tracking device of instrument for measuring partial discharge, including phase acquisition module and phase tracking module, phase
Acquisition module is attached by way of wireless connection with phase tracking module.
In a kind of preferable scheme, phase tracking device according to claim 1, described phase acquisition module
By being electrically connected with shelf depreciation test point, phase acquisition is carried out to synchronizing voltage caused by local discharge test point, phase is adopted
Collect module include the first low pass filter, the first analog-to-digital conversion module, the second analog-to-digital conversion module, the 3rd analog-to-digital conversion module,
First microprocessor, the first clock chip, the first counter, first frequency combiner circuit, the first GPS time service modules and serial ports turn
4G modules, its annexation are as follows：
Signal input part of the signal input part of first low pass filter as signal acquisition module, the first low pass filter
Signal input part electrically connected with shelf depreciation test point；
The signal output part of first low pass filter electrically connects with the signal input part of the first analog-to-digital conversion module；
The signal output part of first analog-to-digital conversion module electrically connects with the signal input part of the second analog-to-digital conversion module；
The signal output part of first analog-to-digital conversion module electrically connects with the signal input part of the 3rd analog-to-digital conversion module；
The signal output part of first analog-to-digital conversion module electrically connects with the signal input part of the first counter；
The signal output part of first counter electrically connects with first microprocessor；
The signal output part of first clock chip electrically connects with the signal input part of first frequency combiner circuit；
The signal output part of first clock chip electrically connects with the signal input part of the first counter；
The signal output part of first frequency combiner circuit electrically connects with the signal input part of the second analog-to-digital conversion module；
The signal output part of first frequency combiner circuit electrically connects with the signal input part of the 3rd analog-to-digital conversion module；
The signal output part of second analog-to-digital conversion module electrically connects with first microprocessor；
The signal output part of 3rd analog-to-digital conversion module electrically connects with first microprocessor；
The signal output part of first GPS time service modules electrically connects with first microprocessor；
The signal input part that first microprocessor turns 4G modules with serial ports electrically connects.
The workflow of phase acquisition module is as follows：
High-frequency Interference is removed by synchronizing voltage caused by shelf depreciation test point by the first low pass filter, then passed through
The sine wave of simulation is converted to Digital Square-Wave by the first analog-to-digital conversion module.Digital Square-Wave passes through the second analog-to-digital conversion module respectively
The phase that data signal crosses the phase at 0 ° of moment and it's 90 ° of moment pasts data signal is obtained with the 3rd analog-to-digital conversion module.First is micro-
Processor is by two phase informations and crosses 0 time progress precise phase tracking, the phase time of mistake 0 corrected.Then
Turn 4G modules by serial ports to send the phase time of mistake 0 after amendment.
In a kind of preferable scheme, described first microprocessor is FPGA.
In a kind of preferable scheme, described FPGA model is to match the XC65LX16 of company of SEL.
In a kind of preferable scheme, described phase checking module is played a game by being electrically connected with instrument for measuring partial discharge
The synchronizing signal that portion discharge tester receives carries out phase acquisition, and with shelf depreciation test point caused by synchronizing voltage phase
Collection information is contrasted, and phase checking module includes the second low pass filter, the 4th analog-to-digital conversion module, the 5th analog-to-digital conversion
Module, the 6th analog-to-digital conversion module, the second microprocessor, second clock chip, the second counter, second frequency combiner circuit,
2nd GPS time service modules and 4G turn serial port module, and its annexation is as follows：
Signal input part of the signal input part of second low pass filter as phase checking module, the second low pass filter
Signal input part electrically connected with instrument for measuring partial discharge；
The signal output part of second low pass filter electrically connects with the signal input part of the 4th analog-to-digital conversion module；
The signal output part of 4th analog-to-digital conversion module electrically connects with the signal input part of the 5th analog-to-digital conversion module；
The signal output part of 4th analog-to-digital conversion module electrically connects with the signal input part of the 6th analog-to-digital conversion module；
The signal output part of 4th analog-to-digital conversion module electrically connects with the signal input part of the second counter；
The signal output part of second counter electrically connects with the second microprocessor；
The signal output part of second clock chip electrically connects with the signal input part of second frequency combiner circuit；
The signal output part of second clock chip electrically connects with the signal input part of the second counter；
The signal output part of second frequency combiner circuit electrically connects with the signal input part of the 5th analog-to-digital conversion module；
The signal output part of second frequency combiner circuit electrically connects with the signal input part of the 6th analog-to-digital conversion module；
The signal output part of 5th analog-to-digital conversion module electrically connects with the second microprocessor；
The signal output part of 6th analog-to-digital conversion module electrically connects with the second microprocessor；
The signal output part of 2nd GPS time service modules electrically connects with the second microprocessor；
The signal input part that second microprocessor turns serial port module with 4G electrically connects.
The workflow of phase checking module is as follows：
The synchronizing signal received to instrument for measuring partial discharge is removed High-frequency Interference by the second low pass filter, then is passed through
The sine wave of simulation is converted to Digital Square-Wave by the 4th analog-to-digital conversion module.Digital Square-Wave passes through the 5th analog-to-digital conversion module respectively
The phase that data signal crosses the phase at 0 ° of moment and it's 90 ° of moment pasts data signal is obtained with the 6th analog-to-digital conversion module.Second is micro-
Processor is by two phase informations and crosses 0 time progress precise phase tracking, the phase time of mistake 0 corrected.Then
The phase time of mistake 0 of phase acquisition module with receiving compares, you can the anti-initial phase released at phase acquisition module,
So as to reach the purpose of phase tracking.
In a kind of preferable scheme, the second described microprocessor is FPGA.
In a kind of preferable scheme, described FPGA model is to match the XC65LX16 of company of SEL.
In a kind of preferable scheme, described wireless connection is attached by 4G modes.
Precise phase method for tracing principle is as follows：
Clock chip produces reference signal, and frequency is identical with surveyed synchronous signal frequency.Closed first by clock through overfrequency
Two orthogonal signalling of sinusoidal reference signals and cosine reference signal are produced into electricity.They are each led into two different ADC
Module (the second analog-to-digital conversion module and the 3rd analog-to-digital conversion module) or (the 5th analog-to-digital conversion module and the 6th analog-to-digital conversion mould
Block).Wait the triggering of analog-to-digital conversion module.
Surveyed synchronizing signal is converted to data signal by the first analog-to-digital conversion module or the 4th analog-to-digital conversion module, when
When signal crosses 0, the second analog-to-digital conversion module and the 3rd analog-to-digital conversion module are triggered (the 5th analog-to-digital conversion module and the 6th modulus
Modular converter is triggered), reference signal is sampled.It can determine that measured signal crosses the phase Q at 0 moment according to sampled value1
And Q2, the phase S1 and S2 at 90 degree of moment excessively.
Understood by calculating now because the error that clock frequency is brought is
I.e.
The amplitude normalization of quadrature signal, i.e.,Then
ε is quantization error in formula, ε=0.45LSB, LSB=U/2N, N=(SNR-1.8)/6.Therefore can be according to output
Signal to noise ratio snr calculates ε, so as to obtain time difference measurement error delta.
Compared with prior art, the beneficial effect of technical solutions of the utility model is：The utility model provides a kind of new
Instrument for measuring partial discharge phase tracking device, can precisely examine the phase of shelf depreciation test point.The utility model structure
Simply, it is simple and efficient to handle, it is applicable to a variety of environment.There is auxiliary work well to local discharge test to electrical equipment
With.
Brief description of the drawings
Fig. 1 is the utility model structure connection figure.
Embodiment
Accompanying drawing being given for example only property explanation, it is impossible to be interpreted as the limitation to this patent；
In order to more preferably illustrate the present embodiment, some parts of accompanying drawing have omission, zoomed in or out, and do not represent actual product
Size；
To those skilled in the art, it is to be appreciated that some known features and its explanation, which may be omitted, in accompanying drawing
's.
The technical solution of the utility model is described further with reference to the accompanying drawings and examples.
As shown in figure 1, a kind of phase tracking device of instrument for measuring partial discharge, including phase acquisition module and phase check and correction
Module, phase acquisition module are attached by way of 4G wireless connections with phase checking module.
Phase acquisition module includes LPF1, ADC1, ADC2, ADC3, FPGA1, the first clock chip, the first counter, the
One frequency synthesizer circuit, GPS time services 1 and serial ports turn 4G modules, and its annexation is as follows：
Signal input part of the LPF1 signal input part as signal acquisition module, LPF1 signal input part are put with local
Electrical testing points electrically connect；
LPF1 signal output part electrically connects with ADC1 signal input part；
ADC1 signal output part electrically connects with ADC2 signal input part；
ADC1 signal output part electrically connects with ADC3 signal input part；
ADC1 signal output part electrically connects with FPGA1 signal input part；
The signal output part of first counter electrically connects with FPGA1；
The signal output part of first clock chip electrically connects with the signal input part of first frequency combiner circuit；
The signal output part of first clock chip electrically connects with the signal input part of the first counter；
The signal output part of first frequency combiner circuit electrically connects with ADC2 signal input part；
The signal output part of first frequency combiner circuit electrically connects with ADC3 signal input part；
ADC2 signal output part electrically connects with FPGA1；
ADC3 signal output part electrically connects with FPGA1；
The signal output part of GPS time services 1 electrically connects with FPGA1；
The signal input part that FPGA1 turns 4G modules with serial ports electrically connects.
Phase checking module includes LPF2, ADC4, ADC5, ADC6, FPGA2, second clock chip, the second counter, the
Two frequency synthesizer circuits, GPS time services 2 and 4G turn serial port module, and its annexation is as follows：
Signal input part of the LPF2 signal input part as phase checking module, LPF2 signal input part are put with local
Electric tester electrically connects；
LPF2 signal output part electrically connects with ADC4 signal input part；
ADC4 signal output part electrically connects with ADC5 signal input part；
ADC4 signal output part electrically connects with ADC6 signal input part；
ADC4 signal output part electrically connects with FPGA2 signal input part；
The signal output part of second counter electrically connects with FPGA2；
The signal output part of second clock chip electrically connects with the signal input part of second frequency combiner circuit；
The signal output part of second clock chip electrically connects with the signal input part of the second counter；
The signal output part of second frequency combiner circuit electrically connects with ADC5 signal input part；
The signal output part of second frequency combiner circuit electrically connects with ADC6 signal input part；
ADC5 signal output part electrically connects with FPGA2；
ADC6 signal output part electrically connects with FPGA2；
The signal output part of GPS time services 2 electrically connects with FPGA2；
The signal input part that FPGA2 turns serial port module with 4G electrically connects.
Clock chip basic frequency is 32Khz in this implementation, and FPGA is the XC65LX16 for matching company of SEL, FPGA basic frequency
It is 50Mhz, ADC signal to noise ratio is 50dB.
The present embodiment course of work is as follows：
The workflow of phase acquisition module is as follows：By synchronizing voltage caused by shelf depreciation test point by LPF1 by height
Frequency interference is removed, then the sine wave of simulation is converted into Digital Square-Wave by ADC1.Digital Square-Wave passes through ADC2 and ADC3 respectively
Obtain the phase that data signal crosses the phase at 0 ° of moment and it's 90 ° of moment pasts data signal.FPGA1 passes through two phase informations and mistake
0 time carries out precise phase tracking, the phase time of mistake 0 corrected.Then 4G modules are turned by after amendment by serial ports
The phase time of mistake 0 send.
The workflow of phase checking module is as follows：To the synchronizing signal that instrument for measuring partial discharge receives by LPF2 by height
Frequency interference is removed, then the sine wave of simulation is converted into Digital Square-Wave by ADC4.Digital Square-Wave passes through ADC5 and ADC6 respectively
Obtain the phase that data signal crosses the phase at 0 ° of moment and it's 90 ° of moment pasts data signal.FPGA2 passes through two phase informations and mistake
0 time carries out precise phase tracking, the phase time of mistake 0 corrected.Then with the mistake 0 of the phase acquisition module received
Phase time compares, you can the anti-initial phase released at phase acquisition module, so as to reach the purpose of phase tracking.
The technique effect of the present embodiment：
The time difference precision of the present embodiment is within 0.1us, and the general time difference precision of prior art is in 0.03ms, time difference precision
300 times are improved, caused phase offset can be controlled below 1 degree, meet the precise acquisition requirement of phase.
Term the being given for example only property explanation of position relationship described in accompanying drawing, it is impossible to be interpreted as the limitation to this patent；
Obviously, above-described embodiment of the present utility model is only intended to clearly illustrate the utility model example, and
It is not the restriction to embodiment of the present utility model.For those of ordinary skill in the field, in described above
On the basis of can also make other changes in different forms.There is no need and unable to give all embodiments
It is exhaustive.All made within spirit of the present utility model and principle all any modification, equivalent and improvement etc., should be included in
Within the protection domain of the utility model claims.
Claims (8)
1. the phase tracking device of a kind of instrument for measuring partial discharge, it is characterised in that proofreaded including phase acquisition module and phase
Module, phase acquisition module are attached by way of wireless connection with phase checking module.
2. phase tracking device according to claim 1, described phase acquisition module by with shelf depreciation test point
Electrical connection, phase acquisition is carried out to synchronizing voltage caused by local discharge test point, it is characterised in that phase acquisition module includes
First low pass filter, the first analog-to-digital conversion module, the second analog-to-digital conversion module, the 3rd analog-to-digital conversion module, the first microprocessor
Device, the first clock chip, the first counter, first frequency combiner circuit, the first GPS time service modules and serial ports turn 4G modules, its
Annexation is as follows：
Signal input part of the signal input part of first low pass filter as signal acquisition module, the letter of the first low pass filter
Number input electrically connects with shelf depreciation test point；
The signal output part of first low pass filter electrically connects with the signal input part of the first analog-to-digital conversion module；
The signal output part of first analog-to-digital conversion module electrically connects with the signal input part of the second analog-to-digital conversion module；
The signal output part of first analog-to-digital conversion module electrically connects with the signal input part of the 3rd analog-to-digital conversion module；
The signal output part of first analog-to-digital conversion module electrically connects with the signal input part of the first counter；
The signal output part of first counter electrically connects with first microprocessor；
The signal output part of first clock chip electrically connects with the signal input part of first frequency combiner circuit；
The signal output part of first clock chip electrically connects with the signal input part of the first counter；
The signal output part of first frequency combiner circuit electrically connects with the signal input part of the second analog-to-digital conversion module；
The signal output part of first frequency combiner circuit electrically connects with the signal input part of the 3rd analog-to-digital conversion module；
The signal output part of second analog-to-digital conversion module electrically connects with first microprocessor；
The signal output part of 3rd analog-to-digital conversion module electrically connects with first microprocessor；
First GPS time service mouldsBlockSignal output part electrically connected with first microprocessor；
The signal input part that first microprocessor turns 4G modules with serial ports electrically connects.
3. phase tracking device according to claim 2, it is characterised in that described first microprocessor is FPGA.
4. phase tracking device according to claim 3, it is characterised in that described FPGA model is company of match SEL
XC65LX16.
5. phase tracking device according to claim 1, described phase checking module by with instrument for measuring partial discharge
Electrical connection, carries out phase acquisition to the synchronizing signal that instrument for measuring partial discharge receives, and with shelf depreciation test point caused by it is same
The phase acquisition information of step voltage is contrasted, and is characterised by, phase checking module includes the second low pass filter, the 4th modulus
Modular converter, the 5th analog-to-digital conversion module, the 6th analog-to-digital conversion module, the second microprocessor, second clock chip, second count
Device, second frequency combiner circuit, the 2nd GPS time service modules and 4G turn serial port module, and its annexation is as follows：
Signal input part of the signal input part of second low pass filter as phase checking module, the letter of the second low pass filter
Number input electrically connects with instrument for measuring partial discharge；
The signal output part of second low pass filter electrically connects with the signal input part of the 4th analog-to-digital conversion module；
The signal output part of 4th analog-to-digital conversion module electrically connects with the signal input part of the 5th analog-to-digital conversion module；
The signal output part of 4th analog-to-digital conversion module electrically connects with the signal input part of the 6th analog-to-digital conversion module；
The signal output part of 4th analog-to-digital conversion module electrically connects with the signal input part of the second counter；
The signal output part of second counter electrically connects with the second microprocessor；
The signal output part of second clock chip electrically connects with the signal input part of second frequency combiner circuit；
The signal output part of second clock chip electrically connects with the signal input part of the second counter；
The signal output part of second frequency combiner circuit electrically connects with the signal input part of the 5th analog-to-digital conversion module；
The signal output part of second frequency combiner circuit electrically connects with the signal input part of the 6th analog-to-digital conversion module；
The signal output part of 5th analog-to-digital conversion module electrically connects with the second microprocessor；
The signal output part of 6th analog-to-digital conversion module electrically connects with the second microprocessor；
2nd GPS time service mouldsBlockSignal output part electrically connected with the second microprocessor；
The signal input part that second microprocessor turns serial port module with 4G electrically connects.
6. phase tracking device according to claim 5, it is characterised in that the second described microprocessor is FPGA.
7. phase tracking device according to claim 6, it is characterised in that described FPGA model is company of match SEL
XC65LX16.
8. phase tracking device according to claim 1, it is characterised in that described wireless connection is entered by 4G modes
Row connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720768628.5U CN206892260U (en) | 2017-06-27 | 2017-06-27 | A kind of phase tracking device of instrument for measuring partial discharge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720768628.5U CN206892260U (en) | 2017-06-27 | 2017-06-27 | A kind of phase tracking device of instrument for measuring partial discharge |
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| Publication Number | Publication Date |
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| CN206892260U true CN206892260U (en) | 2018-01-16 |
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| CN201720768628.5U Active CN206892260U (en) | 2017-06-27 | 2017-06-27 | A kind of phase tracking device of instrument for measuring partial discharge |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108306641A (en) * | 2018-03-29 | 2018-07-20 | 广东电网有限责任公司 | A kind of phase frequency follow-up mechanism for partial discharge test |
| CN108375720A (en) * | 2018-03-29 | 2018-08-07 | 广东电网有限责任公司 | A kind of phase frequency tracing system for partial discharge test |
-
2017
- 2017-06-27 CN CN201720768628.5U patent/CN206892260U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108306641A (en) * | 2018-03-29 | 2018-07-20 | 广东电网有限责任公司 | A kind of phase frequency follow-up mechanism for partial discharge test |
| CN108375720A (en) * | 2018-03-29 | 2018-08-07 | 广东电网有限责任公司 | A kind of phase frequency tracing system for partial discharge test |
| CN108375720B (en) * | 2018-03-29 | 2023-04-28 | 广东电网有限责任公司 | Phase frequency tracking system for partial discharge test |
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