CN206773360U - Array base palte, display panel and display device - Google Patents
Array base palte, display panel and display device Download PDFInfo
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- CN206773360U CN206773360U CN201720236870.8U CN201720236870U CN206773360U CN 206773360 U CN206773360 U CN 206773360U CN 201720236870 U CN201720236870 U CN 201720236870U CN 206773360 U CN206773360 U CN 206773360U
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Abstract
This application discloses a kind of array base palte, display panel and display device.Array base palte includes underlay substrate, is arranged on multiple thin film transistor (TFT)s of underlay substrate side, and the light-shielding structure being arranged between thin film transistor (TFT) and underlay substrate；Thin film transistor (TFT) includes active layer, and active layer includes heavily doped region, lightly doped district and channel region；Orthographic projection of the light-shielding structure to the active layer at least lightly doped district of cover film transistor, channel region, part heavily doped region；The edge of light-shielding structure includes inclination angle area, and active layer includes the transition region formed above the area of inclination angle；Transition region is located at heavily doped region.The scheme of the application is by optimizing light-shielding structure, so that the transition region of active layer is located at the heavily doped region of thin film transistor (TFT), so as to lightly doped district and channel region of the transition region away from thin film transistor (TFT) with more crystal boundary, leakage current caused by being overlapped due to transition region with lightly doped district can be reduced, so as to improve the dimmed phenomenon of the display brightness of display panel.
Description
Technical field
The disclosure relates generally to Display Technique, more particularly to a kind of array base palte, display panel and display device.
Background technology
Mainly include array base palte, color membrane substrates and liquid crystal layer in usual liquid crystal display panel.Wherein array base palte includes
Multiple thin film transistor (TFT)s, multiple pixel electrodes and storage capacitance corresponding to each pixel electrode.Each film crystal is effective
The storage capacitance of pixel electrode corresponding to Yu Xiangqi provides voltage signal to drive liquid crystal rotation corresponding to the pixel electrode certain
Angle is so that display panel display image.
When display panel powers up work, voltage is provided to its corresponding pixel electrode when each thin film transistor (TFT) is opened
Signal；When each thin film transistor (TFT) is closed, storage capacitance corresponding to pixel electrode keeps the voltage signal until next time thin
Film transistor is again turned on.Thin film transistor (TFT) in ideal can be considered as a switch, the leakage current when it is closed, so deposit
The voltage signal free of losses that storing up electricity is held.And in practice, under thin film transistor (TFT) closed mode, produced due to the irradiation of light
Leakage current the voltage signal being stored in storage capacitance can be caused to lose so that display panel is in display image
Brightness is dimmed, influences display effect.
Utility model content
In view of drawbacks described above of the prior art or deficiency, it is expected to provide a kind of array base palte, display panel and display dress
Put, it is intended to solve at least one technical problem present in prior art.
In a first aspect, this application provides a kind of array base palte, array base palte includes underlay substrate, is arranged on underlay substrate
Multiple thin film transistor (TFT)s of side, and the light-shielding structure being arranged between thin film transistor (TFT) and underlay substrate；Thin film transistor (TFT)
Including active layer, active layer includes heavily doped region, lightly doped district and channel region；Orthographic projection of the light-shielding structure to active layer is at least covered
The lightly doped district of lid thin film transistor (TFT), channel region, part heavily doped region；The edge of light-shielding structure includes inclination angle area, active layer bag
Include the transition region to be formed above the area of inclination angle；Transition region is located at heavily doped region.
Optionally, array base palte also includes the first conductor layer and the second conductor layer, and thin film transistor (TFT) also includes grid, source
Pole/drain electrode, wherein grid extend in a first direction；Grid is arranged at the first conductor layer, and covers the position of channel region；Grid with
Gate insulator is provided between channel region；Source/drain is arranged at the second conductor layer, and covering part heavily doped region；Grid
Insulating barrier is provided between source/drain.
Optionally, heavily doped region includes source area and drain region, and active layer includes multiple transition regions；At least one transition region
It is located at drain region positioned at source area and/or at least one transition region.
Optionally, heavily doped region includes the first heavily doped region and the second heavily doped region, the first heavily doped region and second heavily doped
Miscellaneous area is located at the opposite sides of channel region respectively；Light-shielding structure includes Part I and Part II, and Part I is to active layer
The heavily doped region of projection covering part first, the heavily doped region of part second and channel region, projection of the Part II to active layer cover
The heavily doped region of cover second；Part I has the first width in the first direction, and Part II has in the first direction
Second width；Wherein, the second width is less than the first width.
Optionally, the second width is K, and channel region has the 3rd width L in the first direction；Wherein K-L >=2 μm.
Optionally, the inclination angle theta in light-shielding structure inclination angle area meets：16 ° of 26 ° of ＜ θ ＜.
Optionally, chi of the size of the crystal grain of transition region less than the crystal grain in the region in heavily doped region, outside transition region
It is very little.
Optionally, the thickness T of the light-shielding structure meets：300nm ＜ T ＜ 1500nm.
Second aspect, this application provides a kind of display panel, the display panel includes above-mentioned array base palte, display panel
Also include the color membrane substrates that are oppositely arranged with the array base palte, and be arranged on the array base palte and the color membrane substrates it
Between liquid crystal layer.
The third aspect, this application provides a kind of display device, including above-mentioned display panel.
The scheme of the application, by optimizing light-shielding structure so that the transition region of active layer is located at the heavily doped of thin film transistor (TFT)
Miscellaneous area, so as to lightly doped district and channel region of the transition region away from thin film transistor (TFT) of the active layer with more crystal boundary, it can drop
It is low due to transition region and lightly doped district it is overlapping caused by leakage current, so as to improve due to caused by leakage current in storage capacitance
Voltage signal loss caused by the dimmed phenomenon of display panel display brightness.
Brief description of the drawings
By reading the detailed description made to non-limiting example made with reference to the following drawings, the application's is other
Feature, objects and advantages will become more apparent upon：
Fig. 1 shows a kind of structural representation of existing array base palte；
Fig. 2 shows the part plan enlarged diagram of the transition region of thin film transistor (TFT) shown in Fig. 1；
Fig. 3 shows a kind of planar structure schematic diagram of thin film transistor (TFT) in array base palte shown in Fig. 1；
Fig. 4 A show a kind of cross section structure schematic diagram for array base palte that the embodiment of the present application provides；
Fig. 4 B show in array base palte shown in Fig. 4 A the planar structure schematic diagram of thin film transistor (TFT) and thin film transistor (TFT) with
The relative position relation schematic diagram of light-shielding structure；
Fig. 5 shows the planar structure schematic diagram of thin film transistor (TFT) in another array base palte that the embodiment of the present application provides
And the relative position relation schematic diagram of thin film transistor (TFT) and light-shielding structure；
Fig. 6 shows a kind of structural representation for display panel that the embodiment of the present application provides；
Fig. 7 shows a kind of structural representation for display device that the embodiment of the present application provides.
Embodiment
The application is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining relevant utility model, rather than the restriction to the utility model.Further need exist for illustrating
, for the ease of description, the part related to utility model is illustrate only in accompanying drawing.
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the application can phase
Mutually combination.Describe the application in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
Incorporated by reference to Fig. 1, Fig. 1 shows a kind of structural representation of existing array base palte..
Existing array base palte 100 includes underlay substrate 10, is arranged on the thin film transistor (TFT) of the side of underlay substrate 10 and sets
Put the light-shielding structure 12 between thin film transistor (TFT) and underlay substrate 10.
Thin film transistor (TFT) includes active layer, and active layer includes heavily doped region 131, lightly doped district 132 and channel region 133.
In addition, cushion 11 is provided between light-shielding structure 12 and thin film transistor (TFT).In thin film transistor (TFT) and substrate base
The purpose that light-shielding structure 12 is set between plate 10 is in order to avoid light enters from side of the underlay substrate 10 away from thin film transistor (TFT)
It is mapped in channel region 133 and the lightly doped district 132 of thin film transistor active layer.If there is the channel region that light incides active layer
Or it will have larger leakage current in lightly doped district, in thin film transistor (TFT) and flow through.
On the other hand, during manufacture craft, multiple light-shielding structures can be often initially formed in underlay substrate side；So
Afterwards cushion 11 is formed in side of the light-shielding structure away from underlay substrate；Formed again in side of the cushion 11 away from underlay substrate
One layer of polysilicon layer for being used to make thin film transistor (TFT) active area；Then having for multiple thin film transistor (TFT)s is formed in polysilicon layer
Active layer 13.Because multiple light-shielding structures 12 are separation, when this allows for being formed cushion 11 on light-shielding structure 12, delay
Layer 11 is rushed either to contact with underlay substrate 10 or contact with light-shielding structure 12.So that cushion 11 and polysilicon layer are close
Surface forms segment difference.So when forming polysilicon layer, polysilicon layer exists on the surface of cushion 11 to be formd near segment difference
One transition region 134.
Fig. 2 is refer to, Fig. 2 shows the part plan enlarged diagram of the transition region of thin film transistor (TFT) shown in Fig. 1.
As shown in Fig. 2 the crystallite dimension in the transition region 134 of polysilicon layer is less than the crystal grain chi in other regions of polysilicon
It is very little.So make it that the lattice defect in the transition region of polysilicon is more.Lattice defect is more to mean that easy light excites
Electron hole pair is formed, if the transition region of polysilicon layer is located at the intersection of lightly doped district or lightly doped district and heavily doped region, shape
Into electron hole pair easily occur ionize and form leakage current.
During actual fabrication array base palte, due to the deviation of manufacture craft, usually in the array base shown in Fig. 1
The thin-film transistor structure shown in Fig. 3 is formed in plate.Fig. 3 shows that one kind of thin film transistor (TFT) in array base palte shown in Fig. 1 is put down
Face structural representation
As shown in figure 3, the part heavily doped region 131 of the cover film transistor active layer 13 of light-shielding structure 12, part are gently mixed
Miscellaneous area 132 and channel region 133.That is, formed with transition region 134 in lightly doped district in active layer 13.This spline structure
Thin film transistor (TFT) is because the lattice defect in its transition region 134 is more, and can be by underlay substrate side incident ray
In the lightly doped district of irradiation, therefore the easy light of lattice defect in transition region 134 excites to form electron hole pair.It is being lightly doped
Electron hole pair in area easily occurs ionization and forms larger leakage current, can cause storage electricity corresponding with the thin film transistor (TFT)
The voltage signal stored in appearance reduces, and causes display panel display brightness dimmed.
For produced problem in above-mentioned existing array base palte manufacturing process, the embodiment of the present application is entered to above-mentioned light-shielding structure
Improvement is gone.
Show that a kind of cross section structure of array base palte of the embodiment of the present application offer shows incorporated by reference to Fig. 4 A and Fig. 4 B, Fig. 4 A
It is intended to；Fig. 4 B show the planar structure schematic diagram of thin film transistor (TFT) and thin film transistor (TFT) and shading in array base palte shown in Fig. 4 A
The relative position relation schematic diagram of structure.
The array base palte 200 that the present embodiment provides includes underlay substrate 20, is arranged on the multiple thin of the side of underlay substrate 20
Film transistor, and the light-shielding structure 22 being arranged between the thin film transistor (TFT) and the underlay substrate 20.
Thin film transistor (TFT) includes active layer 23, and active layer 23 includes heavily doped region 231, lightly doped district 232 and channel region
233。
In the present embodiment, light-shielding structure 22 can be stretched to extending out so that positive throwing of the light-shielding structure 22 to active layer 23
Lightly doped district 232, channel region 233 and the part heavily doped region 231 of shadow at least cover film transistor active layer 23.
The edge of light-shielding structure 22 includes inclination angle area 221, and active layer includes being formed in the inclination angle area 221 of light-shielding structure 22
The transition region 234 of side.In the present embodiment, the transition region 234 of above-mentioned active layer is arranged in heavily doped region 231.That is,
The transition region 234 of active layer is away from lightly doped district.
Further, manufacturing deviation be present in the technical process for making array base palte, allow in manufacturing deviation
In the range of, because the expansion of light-shielding structure is stretched so that the transition region 234 formed in active layer is still located in heavily doped region.
The array base palte and the thin film transistor (TFT) and light-shielding structure that are arranged on that the present embodiment provides, by heavy doping
Area, which expands, stretches light-shielding structure so that the transition with more crystal boundary formed due to light-shielding structure in thin film transistor active layer
Area is away from lightly doped district.It is deviated even if so making in the technical process of array base palte, the transition region in active layer is still
In heavily doped region.So, can reduce due to transition region and lightly doped district are overlapping and caused by leakage current, so as to
It is bright to improve the display image caused by leakage current changes of the voltage signal corresponding to thin film transistor (TFT) in storage capacitance
Spend dimmed phenomenon.
In some optional implementations of the present embodiment, array base palte also includes the first conductor layer and the second conductor layer.
First conductor layer can may be located remotely from underlay substrate 20 close to underlay substrate 20, the second conductor layer.Thin film transistor (TFT) also includes grid
Pole 25 and source/drain 27.Wherein, grid 25 is arranged in the first conductor layer.There is source/drain 27 to be arranged at the second conductor
In layer.
Grid 25 can extend in a first direction, and the channel region 233 of cover film transistor active area 23.
The covering part heavily doped region 231 of source/drain 27.
Insulating barrier 26 is provided between grid 25 and source/drain 27.It is exhausted that grid is provided between grid 25 and channel region
Edge layer 24.
In application scenes, above-mentioned light-shielding structure 22 can expand along the second direction vertical with above-mentioned first direction
Stretch so that the transition region with more crystal boundary formed due to the presence of light-shielding structure in thin film transistor active layer is remote
Lightly doped district is to improve light leakage current.So, only expand in one direction and stretch light-shielding structure, be advantageous to increase opening for pixel electrode
Mouth rate.
In some optional implementations of the present embodiment, heavily doped region 231 can include source area and drain region, active
It can include multiple transition regions 234 in layer.At least one transition region 234 is located at source area and/or at least one transition region is located at
In drain region.Wherein, orthographic projection of the source/drain 27 to active layer 23 covers above-mentioned source/drain region.Referring to Fig. 4 B, mistake
The part for crossing area 234 is located at the source/drain region that source/drain 27 is covered, and so, transition region 234 is with gently mixing
The distance in miscellaneous area 232 further zooms out, and the error due to preparation in the technique for preparing active layer lightly doped district is lightly doped
Area is offset, and also effectively transition region can be avoided to be formed in lightly doped district.
In some optional implementations of the present embodiment, the thickness T of light-shielding structure could be arranged in following scope
Any thickness, 300nm ＜ T ＜ 1500nm.
In some optional implementations of the present embodiment, the inclination angle area 221 of light-shielding structure 22 with buffer layer contacts
The value for the inclination angle theta that surface and the surface of underlay substrate are formed can select from following scope：16 ° of 26 ° of ＜ θ ＜.
The thickness T of light-shielding structure 22 is bigger, the thickness of the transition region 234 of active layer and the thickness difference in other regions of active layer
It is different bigger；The inclination angle theta in the inclination angle area 221 of light-shielding structure is bigger, then the thickness of the transition region 234 of active layer and other areas of active layer
The difference in thickness in domain is bigger.In order that the thickness relative equilibrium of active layer everywhere, it is desirable to which the thickness of light-shielding structure 22 gets over Bao Yuehao.
Meanwhile the value of the inclination angle theta in the inclination angle area of light-shielding structure 22 is the smaller the better.But then, its thicker shading of light-shielding structure 22
Effect is better., can be with for the active layer for balancing the shaded effect of above-mentioned light-shielding structure 22 with forming thickness relative equilibrium everywhere
While using the thickness for increasing light-shielding structure, the value of the inclination angle theta between light-shielding structure 22 and underlay substrate 20 is reduced.In reality
When border sets the thickness T and the inclination angle theta in the inclination angle area of light-shielding structure 22 of light-shielding structure 22, the equilibrium everywhere of active layer is considered
Property and the demand of leakage current set the thickness T of light-shielding structure 22 and inclination angle theta.
In some optional implementations of the present embodiment, the crystallite dimension of the transition region 234 in active layer has less than this
The crystallite dimension in the heavily doped region 231 outside transition region 234 in active layer.
It is understood that in the present embodiment, Fig. 4 A can be cross section structure schematic diagrams of Fig. 4 B along dotted line m1.
Please continue to refer to Fig. 5, thin film transistor (TFT) in another array base palte provided it illustrates the embodiment of the present application
The relative position relation schematic diagram of planar structure schematic diagram and thin film transistor (TFT) and light-shielding structure.
Identical with array base palte shown in Fig. 4 A, the array base palte 300 that the present embodiment provides includes underlay substrate, is arranged on lining
Multiple thin film transistor (TFT)s of substrate side and the light-shielding structure being arranged between thin film transistor (TFT) and underlay substrate.Array base
Plate 300 also includes the first conductor layer and the second conductor layer.
As shown in figure 5, the thin film transistor (TFT) in the array base palte that the present embodiment provides includes active layer 33, active layer 33 wraps
Include heavily doped region 331, lightly doped district 332, channel region 333.
Thin film transistor (TFT) also includes grid 35 and source/drain 37.Optionally, grid 35 can extend in a first direction.
Wherein, grid 35 is arranged in the first conductor layer；Source/drain is arranged in the second conductor layer.
Grid 35 covers the position of the channel region 333 of active layer 33.The position of the covering part heavily doped region of source/drain 37
Put.
In the array base palte 300 that the present embodiment provides, identical with array base palte shown in Fig. 4 A, light-shielding structure is equally to heavily doped
Miscellaneous area, which expands, stretches.The projection at least lightly doped district 332 of cover film transistor active layer 33, raceway groove of the light-shielding structure to active layer 33
Area 333 and part heavily doped region.So, the transition region 334 formed in active layer 33 due to light-shielding structure is located at heavy doping
So as to make the transition region that active layer is formed due to the presence of light-shielding structure away from lightly doped district and channel region to reduce light in area
Leakage current (leakage current that thin film transistor (TFT) is formed due to illumination is referred to as light leakage current), so as to improve display panel due to thin
The dimmed phenomenon of display brightness caused by the light leakage current of film transistor.
Unlike Fig. 4 A and Fig. 4 B illustrated embodiments, as shown in figure 5, heavily doped region includes the first heavily doped region 331
With the second heavily doped region 331 '.First heavily doped region 331 and the second heavily doped region 331 ' are respectively positioned at relative the two of channel region 333
Side.
In application scenes, the first heavily doped region 331 and the second heavily doped region 331 ' can be distinguished in a second direction
It is arranged on the opposite sides of channel region 333.Wherein, second direction can be orthogonal with first direction.
Light-shielding structure includes Part I 321 and Part II 322.The Part I 321 of light-shielding structure is to active layer 33
The first heavily doped region of orthographic projection covering part 331, the heavily doped region 331 ' of part second, lightly doped district 332 and channel region 333.
Orthographic projection covering part second heavily doped region 331 of the Part II 322 of light-shielding structure to active layer 33.
In some optional implementations of the present embodiment, the Part I 321 of light-shielding structure has in the first direction
First width P, the Part II 322 of light-shielding structure have the second width K in the first direction.Wherein second of light-shielding structure
Point 322 the second width K in the first direction is less than the first width P of the Part I 321 of light-shielding structure in the first direction.
In some optional implementations of the present embodiment, the channel region 333 of active layer 33 has the in the first direction
Three width L, then the channel region 333 of the second width K of the Part II 322 of light-shielding structure in the first direction and active layer 33 is along the
Meet following relation between the 3rd width L in one direction:K-L≥2μm.It can so ensure that light-shielding structure covers substrate base completely
To avoid, light incidence enters the light that plate side passes through or scattering enters in channel region and lightly doped district.
In the present embodiment, can be by the way that light-shielding structure be arranged into two parts, the Part I 321 of light-shielding structure is along
The width P in one direction is more than the width K of the Part II 322 of light-shielding structure in the first direction.Shading can preferably played
Effect, and can make same due to lightly doped district of the transition region that light-shielding structure is formed in active layer away from active layer and channel region
When, it can also be ensured that there is larger aperture opening ratio using the display panel of the array base palte.
Please continue to refer to Fig. 6, a kind of structural representation of the display panel provided it illustrates the embodiment of the present application.
As shown in fig. 6, display panel 400 includes array base palte 41, the color membrane substrates 42 being oppositely arranged with array base palte 41
And it is arranged on the liquid crystal layer 43 between array base palte and color membrane substrates.Wherein array base palte 41 can be Fig. 4 A and Fig. 4 B institutes
The array base palte that shows or the array base palte for including thin film transistor (TFT) shown in Fig. 5.Such display panel when powering up work, by
Thin film transistor (TFT) thereon in off position under light leakage current it is smaller, be advantageous to improve the display panel 400 due to film
The light leakage current of transistor and caused by the dimmed phenomenon of display brightness.
Please continue to refer to Fig. 7, a kind of structural representation of the display device provided it illustrates the embodiment of the present application.
As shown in fig. 7, display device 500 is mobile phone, the display device 500 can include the LCD shown in Fig. 6
Plate.When display device 500 includes the liquid crystal display panel shown in Fig. 6, the display device can also include backlight, wherein carrying on the back
Light source is arranged on side of the array base palte 41 of display panel shown in Fig. 6 away from color membrane substrates 42.
In addition, it will be understood by those skilled in the art that the display device of the application is except including the display surface shown in Fig. 6
Outside plate, some other known structures can also be included, such as driving the drive circuit of display panel.For not mould
The emphasis of the application is pasted, no longer these known structures will be further described.It should be noted that the application is shown
Device is not limited to the mobile phone shown in Fig. 7, can also be the devices such as computer, television set, Intelligent worn device.
Above description is only the preferred embodiment of the application and the explanation to institute's application technology principle.People in the art
Member should be appreciated that utility model scope involved in the application, however it is not limited to what the particular combination of above-mentioned technical characteristic formed
Technical scheme, while should also cover in the case where not departing from utility model design, by above-mentioned technical characteristic or its be equal
Other technical schemes that feature is combined and formed.Such as features described above has with (but not limited to) disclosed herein
The technical scheme that the technical characteristic for having similar functions is replaced mutually and formed.
Claims (10)
1. a kind of array base palte, it is characterised in that the array base palte includes underlay substrate, is arranged on the underlay substrate side
Multiple thin film transistor (TFT)s, and the light-shielding structure being arranged between the thin film transistor (TFT) and the underlay substrate；
The thin film transistor (TFT) includes active layer, and the active layer includes heavily doped region, lightly doped district and channel region；
Orthographic projection of the light-shielding structure to the active layer at least cover the lightly doped district of the thin film transistor (TFT), channel region,
Part heavily doped region；
The edge of the light-shielding structure includes inclination angle area, and the active layer includes the transition region formed above the inclination angle area；
The transition region is located at the heavily doped region.
2. array base palte according to claim 1, it is characterised in that the array base palte also includes the first conductor layer and the
Two conductor layers, the thin film transistor (TFT) also includes grid, source/drain, wherein the grid extends in a first direction；
The grid is arranged at first conductor layer, and covers the position of the channel region；The grid and the channel region
Between be provided with gate insulator；
The source/drain is arranged at second conductor layer, and heavily doped region described in covering part；The grid and the source
Insulating barrier is provided between pole/drain electrode.
3. array base palte according to claim 2, it is characterised in that the heavily doped region includes source area and drain region,
The active layer includes multiple transition regions；
At least one transition region is located at the source area and/or at least one transition region is located at the drain region.
4. array base palte according to claim 3, it is characterised in that the heavily doped region includes the first heavily doped region and the
Two heavily doped regions, first heavily doped region and second heavily doped region are located at the opposite sides of the channel region respectively；
The light-shielding structure includes Part I and Part II,
Projection covering part first heavily doped region, part second heavily doped region and raceway groove of the Part I to the active layer
Area, projection covering part second heavily doped region of the Part II to the active layer；
The Part I has the first width along the first direction, and the Part II has along the first direction
Second width；
Wherein, second width is less than first width.
5. array base palte according to claim 4, it is characterised in that
Second width is K, and the channel region has the 3rd width L in the first direction；Wherein
K-L≥2μm。
6. according to the array base palte described in claim 1-5 any one, it is characterised in that light-shielding structure inclination angle area inclines
Angle θ meets：16 ° of 26 ° of ＜ θ ＜.
7. array base palte according to claim 6, it is characterised in that the size of the crystal grain of the transition region is less than described heavy
The size of the crystal grain in region in doped region, outside the transition region.
8. array base palte according to claim 6, it is characterised in that the thickness T of the light-shielding structure meets：300nm ＜ T
＜ 1500nm.
9. a kind of display panel, it is characterised in that the display panel includes the array base described in claim 1-8 any one
Plate；
The display panel also includes the color membrane substrates being oppositely arranged with the array base palte, and is arranged on the array base palte
With the liquid crystal layer between the color membrane substrates.
10. a kind of display device, it is characterised in that the display device includes the display panel and the back of the body described in claim 9
Light source, wherein the backlight is arranged on side of the array base palte of the display panel away from the color membrane substrates.
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| CN201720236870.8U CN206773360U (en) | 2017-03-13 | 2017-03-13 | Array base palte, display panel and display device |
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| CN201720236870.8U CN206773360U (en) | 2017-03-13 | 2017-03-13 | Array base palte, display panel and display device |
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| CN112071868A (en) * | 2020-09-18 | 2020-12-11 | 京东方科技集团股份有限公司 | LTPS TFT array substrate and display device |
| CN112397579A (en) * | 2020-10-22 | 2021-02-23 | 云谷（固安）科技有限公司 | Display panel |
| CN112928127A (en) * | 2021-01-12 | 2021-06-08 | 武汉华星光电技术有限公司 | Array substrate |
| CN114002887A (en) * | 2021-11-01 | 2022-02-01 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN114005881A (en) * | 2021-10-27 | 2022-02-01 | 云谷（固安）科技有限公司 | Thin film transistor, preparation method thereof and pixel circuit |
| WO2022193063A1 (en) * | 2021-03-15 | 2022-09-22 | 京东方科技集团股份有限公司 | Thin film transistor, display substrate, manufacturing method therefor, and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112071868A (en) * | 2020-09-18 | 2020-12-11 | 京东方科技集团股份有限公司 | LTPS TFT array substrate and display device |
| CN112397579A (en) * | 2020-10-22 | 2021-02-23 | 云谷（固安）科技有限公司 | Display panel |
| CN112397579B (en) * | 2020-10-22 | 2022-12-06 | 云谷（固安）科技有限公司 | Display panel |
| CN112928127A (en) * | 2021-01-12 | 2021-06-08 | 武汉华星光电技术有限公司 | Array substrate |
| WO2022193063A1 (en) * | 2021-03-15 | 2022-09-22 | 京东方科技集团股份有限公司 | Thin film transistor, display substrate, manufacturing method therefor, and display device |
| CN114005881A (en) * | 2021-10-27 | 2022-02-01 | 云谷（固安）科技有限公司 | Thin film transistor, preparation method thereof and pixel circuit |
| CN114002887A (en) * | 2021-11-01 | 2022-02-01 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN114002887B (en) * | 2021-11-01 | 2022-10-04 | 武汉华星光电技术有限公司 | Array substrate and display panel |
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