CN206712805U - Key chip system and internet of things equipment - Google Patents
Key chip system and internet of things equipment Download PDFInfo
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- CN206712805U CN206712805U CN201720451596.6U CN201720451596U CN206712805U CN 206712805 U CN206712805 U CN 206712805U CN 201720451596 U CN201720451596 U CN 201720451596U CN 206712805 U CN206712805 U CN 206712805U
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- key chip
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Abstract
The utility model proposes a kind of key chip system and internet of things equipment, in the key chip system, key chip includes：System bus unit, multiple AES hardware accelerators, the true random number generation unit being connected respectively with system bus unit；Piece external equipment includes：Security control unit and Serial Peripheral Interface (SPI)；Multiple AES hardware accelerators include：National secret algorithm SM9 hardware accelerators, public key encryption algorithm RSA hardware accelerators, national secret algorithm SSF33 hardware accelerators.There is hardware security protection by the utility model key chip, lift the data confidentiality performance of key chip, and, by configuring system bus unit, the data-handling efficiency of effective lifting system.
Description
Technical field
It the utility model is related to communication technical field, more particularly to a kind of key chip system and internet of things equipment.
Background technology
At present, it is a applied to having on the low-power consumption of Internet of Things, low cost, high security, multi-functional key chip
Key management (including password generation, storage, renewal etc.) unit on piece.Data are sent out again after carrying out safe encryption by key chip
See off.Receiving terminal also has corresponding key chip to be decrypted, and ensures the security of data transfer.
In the prior art, the key chip is protected without hardware security, may be intercepted when data are propagated in atmosphere, and
It is easy to crack, data confidentiality performance is bad.
Utility model content
The utility model is intended to one of technical problem at least solving in correlation technique to a certain extent.
Therefore, a purpose of the present utility model is to propose a kind of key chip system so that key chip has hard
Part safeguard protection, the data confidentiality performance of key chip is lifted, and, by configuring system bus unit, effective lifting system
Data-handling efficiency.
Another purpose of the present utility model is to propose a kind of internet of things equipment.
To reach above-mentioned purpose, key chip system that the utility model first aspect embodiment proposes, including：Key core
Piece and the piece external equipment being connected with the key chip, wherein, the key chip includes：System bus unit, respectively with institute
State the connected multiple AES hardware accelerators of system bus unit；The true random number production being connected with the system bus unit
Raw unit；Described external equipment includes：Security control unit and Serial Peripheral Interface (SPI)；The Serial Peripheral Interface (SPI) and the system
Bus unit is connected；The security control unit is connected with the key chip；Wherein, the multiple AES is hardware-accelerated
Device includes：National secret algorithm SM9 hardware accelerators, public key encryption algorithm RSA hardware accelerators, national secret algorithm SSF33 are hardware-accelerated
Device.
The key chip system that the utility model first aspect embodiment proposes, by setting piece peripheral hardware in key chip
It is standby, and multiple AES hardware accelerators are configured, and the built-in system bus unit in key chip so that key chip has
There is hardware security protection, lift the data confidentiality performance of key chip, and, by configuring system bus unit, effectively lifting is
The data-handling efficiency of system.
To reach above-mentioned purpose, internet of things equipment that the utility model second aspect embodiment proposes, including：Equipment sheet
Body, and the key chip system that first aspect embodiment proposes.
The internet of things equipment that the utility model second aspect embodiment proposes, by setting piece external equipment in key chip,
And multiple AES hardware accelerators are configured, and the built-in system bus unit in key chip so that key chip has
Hardware security is protected, and lifts the data confidentiality performance of key chip, and, by configuring system bus unit, effective lifting system
Data-handling efficiency.
The additional aspect of the utility model and advantage will be set forth in part in the description, partly by from following description
In become obvious, or by it is of the present utility model practice recognize.
Brief description of the drawings
The above-mentioned and/or additional aspect of the utility model and advantage from the following description of the accompanying drawings of embodiments will
Become obvious and be readily appreciated that, wherein：
Fig. 1 is the structural representation for the key chip system that the embodiment of the utility model one proposes；
Fig. 2 is the structural representation for the key chip system that another embodiment of the utility model proposes.
Embodiment
Embodiment of the present utility model is described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning
Same or similar element is represented to same or similar label eventually or there is the element of same or like function.Below by ginseng
The embodiment for examining accompanying drawing description is exemplary, is only used for explaining the utility model, and it is not intended that to of the present utility model
Limitation.On the contrary, embodiment of the present utility model includes falling into owning in the range of the spirit and intension of attached claims
Change, modification and equivalent.
Fig. 1 is the structural representation for the key chip system that the embodiment of the utility model one proposes.
Referring to Fig. 1, the key chip system 10 includes：Key chip 11 and the piece external equipment being connected with key chip 11
12, wherein, key chip 11 includes：System bus unit 1101, the multiple encryptions being connected respectively with system bus unit 1101
Hardware algorithm accelerator；The true random number generation unit 1105 being connected with system bus unit 1101；Piece external equipment 12 includes：Peace
Full control unit 121 and Serial Peripheral Interface (SPI) 122；Serial Peripheral Interface (SPI) 122 is connected with system bus unit 1101；Security control
Unit 121 is connected with key chip 11.
In one embodiment of the present utility model, the key chip system 10 can be that wireless fidelity systems level encapsulates
The key chip system of (System In Package, SiP).
Therefore, the key chip system 10 in the utility model has more preferable resistance to mechanical and chemical attack ability, can
Significantly shorten product development and the cycle launched, less radio-frequency performance is more stable, and reliability is higher.
In one embodiment of the present utility model, the key chip system 10 includes：Key chip 11 and with key core
The connected piece external equipment 12 of piece 11, wherein,
Key chip 11 includes：
System bus unit 1101, the multiple AES hardware accelerators being connected respectively with system bus unit 1101.
Wherein, the system bus unit 1101 can be, for example, Advanced High-Performance Bus (Advanced High
Performance Bus, AHB) unit.
The system bus unit 1101 only relies only on the assistance of flash memory access memory 126, without any bridger
(bridge) and/or I/O interface assistance so that data, address and control signal during data processing operation can be via
The high-speed transfer of system bus unit 1101 is to other units, therefore, the data-handling efficiency of effective lifting system.
In embodiment of the present utility model, by configuring system bus unit 1101, due to the high data of system bus
Handling capacity, its data processing amount within the unit interval are far above SDIO/SPI data processing amount.And key core can be simplified
The hardware design of piece system 10.It is easy to use modular construction design method, access system bus unit in hardware design
1101 flash memory access memory 126, multiple AES hardware accelerators etc., it is connected with system bus unit 1101
Connect, without considering the handling process inside system bus unit 1101.By configuring system bus unit 1101, system is simplified
Structure so that whole system is clear in structure, and line is few, realizes the printing of bottom plate line.
Further, by configuring system bus unit 1101 so that system expansibility can be good.On the one hand it is that scale expands
Fill, scale expands needs only to insert the plug-in units of some same types more, is on the other hand that function expands, function expand need only to by
The standard of lighting system bus unit 1101 designs new plug-in unit.System bus unit 1101 make it that system update performance is good.Due to multiple
AES hardware accelerator, flash memory access memory 126 etc. are suspended to always by the design code of system bus unit 1101
On line, therefore, it is possible to as the chip of processor and other progress about chip design new plug-in unit, new plug-in unit is inserted
System is updated on to bottom plate, without changing other plug-in units and bottom plate line.
Wherein, multiple AES hardware accelerators include：
National secret algorithm SM9 hardware accelerators 1102, public key encryption algorithm RSA hardware accelerators 1103, national secret algorithm SSF33
Hardware accelerator 1104.
In one embodiment of the present utility model, the key chip 11 is built-in with security algorithm engine, and security algorithm draws
Not only support SM9 id password algorithms are held up, also support RSA public key encryption algorithms, and built-in true random number module.
The AES that multiple AES hardware accelerators are supported respectively is as follows：
1st, SM9 id passwords algorithm, it is a kind of cryptographic algorithm based on mark.SM9 id passwords algorithm has with entity
Criterion knows (such as addresses of items of mail, phone number, QQ number, identity card code) and is used as public key, and user is without application and exchanges certificate, from
And substantially reduce the complexity of key chip system 10.
2nd, it public key encryption algorithm RSA, can be not only used for encrypting, can be used for digital signature again.
3rd, SSF33 cryptographic algorithms, it is to carry out computing in units of 128 packets, key length is 16 bytes.
SSF33 algorithms and symmetric encipherment algorithm based on 3-DES use the key of equal length, can be based on original
The key management of 3-DES symmetric encipherment algorithms is compatible.
The true random number generation unit 1105 being connected with system bus unit 1101.
Piece external equipment 12 includes：Security control unit 121 and Serial Peripheral Interface (SPI) 122.
Serial Peripheral Interface (SPI) 122 is connected with system bus unit 1101.
Security control unit 121 is connected with key chip 11.
In embodiment of the present utility model, security control unit 121 can be used for detecting power supply monitoring/administrative unit
125 power supply and frequency, thus, it is possible to effectively prevent that outside from being attacked by measuring power supply wave shape and frequency.
In one embodiment of the present utility model, referring to Fig. 2, piece external equipment 12 also includes：
The external piloting control processor 123 being connected with Serial Peripheral Interface (SPI) 122, external piloting control processor 123 pass through serial outer
If carry out data transmission between interface 122, system bus unit 1101 and multiple AES hardware accelerators.
Piece external equipment 12 also includes：The clock unit 124 being connected with system bus unit 1101.
In embodiment of the present utility model, clock unit 124 can provide required when key chip system 10 works
Clock.
Piece external equipment 12 also includes：Power supply monitoring/the administrative unit 125 being connected with key chip 11.
Piece external equipment 12 also includes：The flash memory access memory 126 being connected with system bus unit 1101.
In embodiment of the present utility model, flash memory access memory 126 can be used for part caused by caching encryption
Data.
In the present embodiment, by setting piece external equipment in key chip, and multiple AES hardware accelerators are configured, and
The built-in system bus unit in key chip so that key chip has hardware security protection, lifts the data of key chip
Security performance, and, by configuring system bus unit, the data-handling efficiency of effective lifting system.
It should be noted that in description of the present utility model, term " first ", " second " etc. are only used for describing purpose,
And it is not intended that instruction or hint relative importance.In addition, in description of the present utility model, it is unless otherwise indicated, " more
It is individual " it is meant that two or more.
Any process or method described otherwise above description in flow chart or herein is construed as, and represents to include
Module, fragment or the portion of the code of the executable instruction of one or more the step of being used to realize specific logical function or process
Point, and the scope of preferred embodiment of the present utility model includes other realization, wherein can not press shown or discuss
Order, including according to involved function by it is basic simultaneously in the way of or in the opposite order, carry out perform function, this should be by this
The embodiment person of ordinary skill in the field of utility model is understood.
It should be appreciated that each several part of the present utility model can be realized with hardware, software, firmware or combinations thereof.
In above-mentioned embodiment, what multiple steps or method can be performed in memory and by suitable instruction execution system with storage
Software or firmware are realized.If, and in another embodiment, can be with known in this field for example, realized with hardware
Any one of following technology or their combination realize：With the gate for realizing logic function to data-signal
The discrete logic of circuit, the application specific integrated circuit with suitable combinational logic gate circuit, programmable gate array (PGA),
Field programmable gate array (FPGA) etc..
Those skilled in the art are appreciated that to realize all or part of step that above-described embodiment method carries
Suddenly it is that by program the hardware of correlation can be instructed to complete, described program can be stored in a kind of computer-readable storage medium
In matter, the program upon execution, including one or a combination set of the step of embodiment of the method.
In addition, each functional unit in each embodiment of the utility model can be integrated in a processing module,
Can be that unit is individually physically present, can also two or more units be integrated in a module.It is above-mentioned integrated
Module can both be realized in the form of hardware, can also be realized in the form of software function module.The integrated mould
If block is realized in the form of software function module and counted as independent production marketing or in use, one can also be stored in
In calculation machine read/write memory medium.
Storage medium mentioned above can be read-only storage, disk or CD etc..
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description
Point is contained at least one embodiment or example of the present utility model.In this manual, to the schematic table of above-mentioned term
State and be not necessarily referring to identical embodiment or example.Moreover, specific features, structure, material or the feature of description can be
Combined in an appropriate manner in any one or more embodiments or example.
Although embodiment of the present utility model has been shown and described above, it is to be understood that above-described embodiment is
Exemplary, it is impossible to it is interpreted as to limitation of the present utility model, one of ordinary skill in the art is in the scope of the utility model
It is interior above-described embodiment to be changed, changed, replaced and modification.
Claims (7)
1. a kind of key chip system, it is characterised in that the key chip system includes：Key chip and with the key core
The connected piece external equipment of piece, wherein,
The key chip includes：
System bus unit, the multiple AES hardware accelerators being connected respectively with the system bus unit；
The true random number generation unit being connected with the system bus unit；
Described external equipment includes：Security control unit and Serial Peripheral Interface (SPI)；
The Serial Peripheral Interface (SPI) is connected with the system bus unit；
The security control unit is connected with the key chip；
Wherein, the multiple AES hardware accelerator includes：
National secret algorithm SM9 hardware accelerators, public key encryption algorithm RSA hardware accelerators, national secret algorithm SSF33 hardware accelerators.
2. key chip system as claimed in claim 1, it is characterised in that described external equipment also includes：
The external piloting control processor being connected with the Serial Peripheral Interface (SPI), the external piloting control processor pass through the serial peripheral
Carry out data transmission between interface, the system bus unit and the multiple AES hardware accelerator.
3. key chip system as claimed in claim 1, it is characterised in that described external equipment also includes：
The clock unit being connected with the system bus unit.
4. key chip system as claimed in claim 1, it is characterised in that described external equipment also includes：
Power supply monitoring/the administrative unit being connected with the key chip.
5. key chip system as claimed in claim 1, it is characterised in that described external equipment also includes：
The flash memory access memory being connected with the system bus unit.
A kind of 6. internet of things equipment, it is characterised in that including：Apparatus body, and
Key chip system as described in claim any one of 1-5.
7. internet of things equipment as claimed in claim 6, it is characterised in that the internet of things equipment includes：
Home appliance, sensor device or control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720451596.6U CN206712805U (en) | 2017-04-26 | 2017-04-26 | Key chip system and internet of things equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720451596.6U CN206712805U (en) | 2017-04-26 | 2017-04-26 | Key chip system and internet of things equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206712805U true CN206712805U (en) | 2017-12-05 |
Family
ID=60459350
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720451596.6U Expired - Fee Related CN206712805U (en) | 2017-04-26 | 2017-04-26 | Key chip system and internet of things equipment |
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| Country | Link |
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| CN (1) | CN206712805U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113660087A (en) * | 2021-07-06 | 2021-11-16 | 浙江传媒学院 | SM9 identification cryptographic algorithm hardware implementation system based on finite field |
-
2017
- 2017-04-26 CN CN201720451596.6U patent/CN206712805U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113660087A (en) * | 2021-07-06 | 2021-11-16 | 浙江传媒学院 | SM9 identification cryptographic algorithm hardware implementation system based on finite field |
| CN113660087B (en) * | 2021-07-06 | 2023-09-26 | 浙江传媒学院 | SM9 identification cipher algorithm hardware realization system based on finite field |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171205 Termination date: 20210426 |
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| CF01 | Termination of patent right due to non-payment of annual fee |