CN206674233U - Crest detects circuit and peak detector - Google Patents

Abstract

The utility model provides a kind of crest detection circuit and peak detector, belongs to LED drive circuit technical field.Crest detection circuit includes：Difference amplifier, FET is preset, predetermined capacitive and bleeder circuit, the first end of difference amplifier are connected with the first end of default FET, and the second end of difference amplifier is connected with the second end of default FET and the first end of predetermined capacitive respectively；One end of bleeder circuit and the first end of predetermined capacitive connect；Wherein, difference amplifier is used to receive input signal, and input signal is inputted to default FET, and default FET is used to export primary peak signal, bleeder circuit is used to carry out voltage division processing to primary peak signal by predetermined capacitive, generates secondary peak signal.Crest detection circuit and peak detector provided by the utility model, realize the function of PFC sine wave harmonics.

Description

Crest detects circuit and peak detector

Technical field

It the utility model is related to LED drive circuit technical field, more particularly to a kind of crest detection circuit and crest detection Device.

Background technology

Light emitting diode (Light Emitting Diode, abbreviation LED) is a kind of efficient light fixture, is widely used to The field such as various instructions, display, decoration, backlight, general lighting and urban landscape.LED lamp is typically required with power Factor correcting (Power Factor Correction, abbreviation PFC) function, particularly high-power LED driver, is LED Important part.

First module in PFC units is peak time detector, and shown in Figure 1, Fig. 1 provides for prior art A kind of peak time detector structural representation, the peak time detector 10 by preset peak detector 101, biased electrical Potential source 102, comparator 103 and pulse generator 104 form.Wherein, it is by difference amplifier, N to preset peak detector 101 Type FET and electric capacity are formed.Under conditions of input signal crest is stable, the default peak detector 101 is detectable Each wave crest point.But when the crest of input signal is interfered or during power network shakiness, shown in Figure 2, Fig. 2 is prior art A kind of generation schematic diagram of the crest signal provided, the crest of input signal will fluctuate up and down.Now, some wave crest points will It is missed, can thus produces the PFC reference voltages of mistake, so as to which the function of PFC sine wave harmonics can not be realized.

Therefore, can be because wave crest point be missed, so as to which PFC can not be being realized just using existing default peak detector 101 The function of string ripple harmonic.

Utility model content

The utility model provides a kind of crest detection circuit and peak detector, to avoid wave crest point from being missed, so as to real The function of existing PFC sine wave harmonics.

The utility model embodiment provides a kind of crest detection circuit, including：

Difference amplifier, preset FET, predetermined capacitive and bleeder circuit, the first end of the difference amplifier and institute State the first end connection of default FET, the second end of the difference amplifier respectively with the default FET second End connects with the first end of the predetermined capacitive；One end of the bleeder circuit is connected with the first end of the predetermined capacitive；

Wherein, the difference amplifier is used to receive input signal, and the input signal is inputted to the default field Effect pipe, the default FET are used to export primary peak signal, and the bleeder circuit is used to pass through the predetermined capacitive Voltage division processing is carried out to primary peak signal, generates secondary peak signal.

In the embodiment of the utility model one, the bleeder circuit includes：

Gate generator, buffer, power supply sub-circuit and partial pressure sub-circuit；The first end of the buffer with it is described Gate generator is connected, and the second end of the buffer is connected with the power supply sub-circuit, the 3rd end of the buffer It is connected with the first end of the partial pressure sub-circuit, the second end of the partial pressure sub-circuit is connected with the predetermined capacitive.

In the embodiment of the utility model one, the partial pressure sub-circuit includes：

First power supply, the first FET, the second FET and the 3rd FET, one end point of first power supply The grid of drain electrode, the first FET not with first FET and the grid of second FET are connected, institute The source electrode for stating the first FET is connected with the source electrode of second FET, the drain electrode of second FET with it is described The source electrode connection of 3rd FET, the grid of the 3rd FET are connected with the buffer, the 3rd effect pipe Drain electrode be connected with the predetermined capacitive.

In the embodiment of the utility model one, the power supply sub-circuit includes：

Second source, the first electric capacity, the 4th FET and the 5th FET, one end of the second source respectively with The drain electrode connection of the buffer, the grid of the 5th FET and the 5th FET, the 5th field-effect Drain electrode of the source electrode of pipe respectively with the grid and the 4th FET of the 4th FET is connected, the 4th effect Should the source electrode of pipe be connected with the first end of first electric capacity, the second end of first electric capacity and the 5th FET Drain electrode connection.

In the embodiment of the utility model one, the default FET, first FET, second effect Ying Guan, the 3rd FET, the 4th FET and the 5th FET are N-type FET.

In the embodiment of the utility model one, the current value of first power supply and the second source is 0.1 microampere；

Or the current value of first power supply and the second source is 2 microamperes.

The utility model embodiment also provides a kind of peak detector, including：

Crest detection circuit described in any of the above-described embodiment.

The crest detection circuit and peak detector that the utility model embodiment provides, crest detection circuit include difference Amplifier, preset FET, predetermined capacitive and bleeder circuit.Wherein, the first end of difference amplifier and default FET First end connection, the second end of difference amplifier connects with the second end of default FET and the first end of predetermined capacitive respectively Connect；One end of bleeder circuit and the first end of predetermined capacitive connect.As can be seen here, the crest inspection that the utility model embodiment provides Slowdown monitoring circuit, by setting bleeder circuit so that crest detects circuit before primary peak signal is exported, and can pass through the partial pressure Circuit carries out voltage division processing to the primary peak signal so that primary peak signal voltage declines in staged step by step, directly It is consistent with the voltage for inputting defeated signal to the primary peak signal voltage, rise again with the input of input signal afterwards, from And secondary peak signal is generated, afterwards, it is possible to by the peak point of the secondary peak signal capture to input signal, to avoid Wave crest point is missed, so as to realize the function of PFC sine wave harmonics.

Brief description of the drawings

, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art Or the required accompanying drawing used does one and simply introduced in description of the prior art, it should be apparent that, drawings in the following description are Some embodiments of the utility model, for those of ordinary skill in the art, do not paying the premise of creative labor Under, other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 is a kind of structural representation for peak time detector that prior art provides；

Fig. 2 is a kind of generation schematic diagram for crest signal that prior art provides；

Fig. 3 is the structural representation that a kind of crest that the utility model embodiment provides detects circuit；

Fig. 4 is the structural representation that another crest that the utility model embodiment provides detects circuit；

Fig. 5 is a kind of generation schematic diagram for crest signal that the utility model embodiment provides；

Fig. 6 is a kind of structural representation for peak detector that the utility model embodiment provides.

Embodiment

It is new below in conjunction with this practicality to make the purpose, technical scheme and advantage of the utility model embodiment clearer Accompanying drawing in type embodiment, the technical scheme in the embodiment of the utility model is clearly and completely described, it is clear that is retouched The embodiment stated is the utility model part of the embodiment, rather than whole embodiments.Based on the implementation in the utility model Example, the every other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made, is belonged to The scope of the utility model protection.

Term " first ", " second ", " the 3rd " in specification and claims of the present utility model and above-mentioned accompanying drawing, (if present)s such as " the 4 " is for distinguishing similar object, without for describing specific order or precedence.Should The data that the understanding so uses can exchange in the appropriate case, so as to embodiment of the present utility model described herein, example If implemented with the order in addition to those for illustrating or describing herein.In addition, term " comprising " and " having " and Their any deformation, it is intended that cover it is non-exclusive include, for example, containing the process of series of steps or unit, side Method, system, product or equipment are not necessarily limited to those steps clearly listed or unit, but may include not list clearly Or for the intrinsic other steps of these processes, method, product or equipment or unit.

It should be noted that these specific embodiments can be combined with each other below, for same or analogous concept Or process may repeat no more in certain embodiments.

Fig. 3 is that a kind of crest of the utility model embodiment offer detects the structural representation of circuit 30, the utility model Embodiment simply illustrates by taking Fig. 3 as an example, but does not represent the utility model and be limited only to this.It is shown in Figure 3, the ripple Blob detection circuit 30 can include：

Difference amplifier 301, preset FET 302, predetermined capacitive 303 and bleeder circuit 304, difference amplifier 301 First end be connected with the first end of default FET 302, the second end of difference amplifier 301 respectively with default FET 302 the second end connects with the first end of predetermined capacitive 303；One end of bleeder circuit 304 connects with the first end of predetermined capacitive 303 Connect.

Wherein, difference amplifier 301 is used to receive input signal, and input signal is inputted to default FET 302, Default FET 302 is used to export primary peak signal, and bleeder circuit 304 is used for by predetermined capacitive 303 to primary peak Signal carries out voltage division processing, generates secondary peak signal.

Wherein, input signal can be sine wave signal, or cosine wave signal, here, for input signal Type, the utility model are not particularly limited.

In the utility model embodiment, by setting bleeder circuit 304, its object is to：When the voltage of input signal When fluctuation is fluctuated up and down, pass through bleeder circuit 304 so that crest detects circuit 30 before primary peak signal is exported, can be with Voltage division processing is carried out to the primary peak signal by the bleeder circuit 304 so that primary peak signal voltage is in step by step Staged declines, until the primary peak signal voltage is consistent with the voltage of the defeated signal of input, afterwards again with input signal Input and rise, so as to generate secondary peak signal, afterwards, it is possible to which input signal is arrived by the secondary peak signal capture Peak point, to avoid wave crest point from being missed, so as to realize the function of PFC sine wave harmonics.

The crest detection circuit 30 that the utility model embodiment provides, crest detection circuit 30 include difference amplifier 301, preset FET 302, predetermined capacitive 303 and bleeder circuit 304.Wherein, the first end of difference amplifier 301 is with presetting The first end connection of FET 302, the second end of difference amplifier 301 respectively with the second end of default FET 302 and The first end connection of predetermined capacitive 303；One end of bleeder circuit 304 is connected with the first end of predetermined capacitive 303.As can be seen here, The crest detection circuit 30 that the utility model embodiment provides, by setting bleeder circuit 304 so that crest detection circuit 30 exists Before exporting primary peak signal, voltage division processing can be carried out to the primary peak signal by the bleeder circuit 304 so that the One crest signal voltage declines in staged step by step, until the primary peak signal voltage and the voltage one for inputting defeated signal Cause, rise again with the input of input signal afterwards, so as to generate secondary peak signal, afterwards, it is possible to by this second Crest signal capture to input signal peak point, to avoid wave crest point from being missed, so as to realize the work(of PFC sine wave harmonics Energy.

It is further, shown in Figure 4 on the basis of embodiment corresponding to Fig. 3 based on embodiment corresponding to Fig. 3, Fig. 4 is the structural representation that another crest that the utility model embodiment provides detects circuit 30, and the crest detects circuit 30 In bleeder circuit 304 can include：

Gate generator 3041, buffer 3042, power supply sub-circuit 3043 and partial pressure sub-circuit 3044；Buffer 3042 first end is connected with gate generator 3041, and the second end of buffer 3042 is connected with power supply sub-circuit 3043, 3rd end of buffer 3042 is connected with the first end of partial pressure sub-circuit 3044, the second end of partial pressure sub-circuit 3044 and default electricity Hold 303 connections.

Further, partial pressure sub-circuit 3044 includes：

First power supply 30441, the first FET 30442, the second FET 30443 and the 3rd FET 30444, One end of first power supply 30441 drain electrode with the first FET 30442, the grid of the first FET 30442 and respectively The source electrode of the grid connection of two FETs 30443, the source electrode of the first FET 30442 and the second FET 30443 connects Connect, the drain electrode of the second FET 30443 is connected with the source electrode of the 3rd FET 30444, the grid of the 3rd FET 30444 Pole is connected with buffer 3042, and the drain electrode of the 3rd FET 30444 is connected with predetermined capacitive 303.

Optionally, power supply sub-circuit 3043 includes：

Second source 30431, the first electric capacity 30432, the 4th FET 30433 and the 5th FET 30434, second One end of power supply 30431 respectively with buffer 3042, the grid of the 5th FET 30434 and the 5th FET 30434 Drain electrode connection, the source electrode of the 5th FET 30434 grid and the 4th FET with the 4th FET 30433 respectively 30433 drain electrode connection, the source electrode of the 4th FET 30433 are connected with the first end of the first electric capacity 30432, the first electric capacity 30432 the second end is connected with the drain electrode of the 5th FET 30434.

Optionally, FET 302, the first FET 30442, the second FET 30443, the 3rd field-effect are preset Pipe 30444, the 4th FET 30433 and the 5th FET 30434 are N-type FET.Certainly, the utility model is real Example is applied simply with default FET 302, the first FET 30442, the second FET 30443, the 3rd FET 30444th, the 4th FET 30433 and the 5th FET 30434 are and illustrated exemplified by N-type FET, but not Represent the utility model and be limited only to this.

Optionally, the current value of the first power supply 30441 and second source 30431 is 0.1 microampere；Or first power supply 30441 and the current value of second source 30431 be 2 microamperes.

Example, the utility model embodiment is simply with the current value of the first power supply 30441 and second source 30431 0.1 microampere；Or first the current value of power supply 30441 and second source 30431 be to illustrate exemplified by 2 microamperes, specifically may be used It is actually needed and is configured with basis, here, new for the first power supply 30441 and the current value of second source 30431, this practicality Type does not do and further limited.

In actual application, illustrated by taking sine wave as an example, the operation principle of crest detection circuit 30 is：Clock Pulse generator 3041 is according to the sine wave period of input signal, and according to the discharge time of sine wave period and to decline ladder true Timing clock pulses cycle and clock-pulse width.Incorporated by reference to shown in Fig. 4, gate generator 3041 produces clock pulse signal Afterwards, input signal of the clock pulse signal as buffer 3042, when being discharged to reduce gate generator 3041 Switch-charge is injected and extracted from the influence to crest signal, can reduce gate generator by sub-circuit 3043 of powering Switch-charge is injected and extracted from the influence to crest signal during 3041 electric discharge.The voltage of the power supply sub-circuit 3043 is by the 4th effect Should the FET 30434 of pipe 30433 and the 5th composition two series winding diodes determine, and the first electric capacity 30432 be used for keep Voltage, therefore, the supply voltage of buffer 3042 can be reduced by the power supply sub-circuit 3043 so that buffer 3042 is driving During three FET 30444 of dynamic switch, reduce switch spike value, so as to reduce the influence to crest signal.At the 3rd After effect pipe 30444 turns on, the electric current of its partial pressure is by the first FET 30442, the second FET the 30443, the 3rd The power supply 30441 of FET 30444 and first determines that the electric current of the first power supply 30441 passes through first FET 30442 The electric current of the first power supply of identical 30441 is mapped to the second FET 30443.

Shown in Figure 5, Fig. 5 is a kind of generation schematic diagram for crest signal that the utility model embodiment provides, when The sine wave signal of input from it is low to crest when, default FET 302 has stronger power supply capacity, and through the second FET 30443 and the 3rd FET 30444 extract electric current it is relatively weak so that crest signal with input signal rise and on Rise, to reach crest value.Meanwhile by the default FET 302 and predetermined capacitive 303 of one-way conduction, ripple can make it that The voltage of peak-to-peak signal is maintained on the crest value of input signal.Afterwards, input sine wave signal is begun to decline from crest, and crest Signal voltage is maintained on input signal crest value, in order to detect the sine wave signal of next all low peaks, it is necessary to drop The voltage of the low crest signal.After input sine wave signal declines from crest, default FET 302 may turn off, from when Clock pulse signal caused by clock generator 3041 passes through buffer 3042, makes the amplitude of clock pulse signal electric from first Pressure is reduced to second voltage, to drive the 3rd FET 30444, so as to reduce the switch spike pair of the 3rd FET 30444 The influence of crest signal so that primary peak signal voltage declines in staged step by step, until primary peak signal electricity Pressure is consistent with the voltage of input signal, then rises with the input of input signal, so as to generate secondary peak signal, it is possible to By the peak point of the secondary peak signal capture to input signal, to avoid wave crest point from being missed, so as to realize PFC sine waves The function of harmonic.It should be noted that in the utility model embodiment, in a cycle the reduction of crest signal voltage pass through The electric current of first power supply 30441 and the clock widths of clock pulse signal determine.

Fig. 6 is a kind of structural representation for peak detector 60 that the utility model embodiment provides, and refers to Fig. 6 institutes Show, the peak detector 60 can include：

Crest detection circuit 30 shown in any of the above-described embodiment.

Peak detector 60 shown in the utility model embodiment, can perform the technical side shown in above method embodiment Case, its realization principle and beneficial effect are similar, are no longer repeated herein.

Finally it should be noted that：Various embodiments above is only to illustrate the technical solution of the utility model, rather than it is limited System；Although the utility model is described in detail with reference to foregoing embodiments, one of ordinary skill in the art should Understand：It can still modify to the technical scheme described in foregoing embodiments, either to which part or whole Technical characteristic carries out equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from this practicality newly The scope of each embodiment technical scheme of type.

Claims (7)

1. a kind of crest detects circuit, it is characterised in that including：

Difference amplifier, presets FET, predetermined capacitive and bleeder circuit, the first end of the difference amplifier with it is described pre- If the first end connection of FET, the second end of the difference amplifier respectively with the second end of the default FET and The first end connection of the predetermined capacitive；One end of the bleeder circuit is connected with the first end of the predetermined capacitive；

Wherein, the difference amplifier is used to receive input signal, and the input signal is inputted to the default field-effect Pipe, the default FET are used to export primary peak signal, and the bleeder circuit is used for by the predetermined capacitive to the One crest signal carries out voltage division processing, generates secondary peak signal.

2. circuit according to claim 1, it is characterised in that the bleeder circuit includes：

Gate generator, buffer, power supply sub-circuit and partial pressure sub-circuit；The first end of the buffer and the clock Pulse generator is connected, and the second end of the buffer is connected with the power supply sub-circuit, the 3rd end of the buffer and institute The first end connection of partial pressure sub-circuit is stated, the second end of the partial pressure sub-circuit is connected with the predetermined capacitive.

3. circuit according to claim 2, it is characterised in that the partial pressure sub-circuit includes：

First power supply, the first FET, the second FET and the 3rd FET, one end of first power supply respectively with The grid connection of the drain electrode of first FET, the grid of the first FET and second FET, described the The source electrode of one FET is connected with the source electrode of second FET, the drain electrode of second FET and the described 3rd The source electrode connection of FET, the grid of the 3rd FET are connected with the buffer, the 3rd FET Drain electrode is connected with the predetermined capacitive.

4. circuit according to claim 3, it is characterised in that the power supply sub-circuit includes：

Second source, the first electric capacity, the 4th FET and the 5th FET, one end of the second source respectively with it is described The drain electrode connection of buffer, the grid of the 5th FET and the 5th FET, the 5th FET Drain electrode of the source electrode respectively with the grid and the 4th FET of the 4th FET is connected, the 4th FET Source electrode be connected with the first end of first electric capacity, the drain electrode of the second end of first electric capacity and the 5th FET Connection.

5. circuit according to claim 4, it is characterised in that

It is the default FET, first FET, second FET, the 3rd FET, described 4th FET and the 5th FET are N-type FET.

6. circuit according to claim 4, it is characterised in that

The current value of first power supply and the second source is 0.1 microampere；

Or the current value of first power supply and the second source is 2 microamperes.

A kind of 7. peak detector, it is characterised in that including：

Crest detection circuit described in the claims any one of 1-6.