CN206575509U - A kind of many video source access splicers - Google Patents
A kind of many video source access splicers Download PDFInfo
- Publication number
- CN206575509U CN206575509U CN201720324208.8U CN201720324208U CN206575509U CN 206575509 U CN206575509 U CN 206575509U CN 201720324208 U CN201720324208 U CN 201720324208U CN 206575509 U CN206575509 U CN 206575509U
- Authority
- CN
- China
- Prior art keywords
- video
- interface
- input
- output
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Controls And Circuits For Display Device (AREA)
Abstract
The utility model provides a kind of many video source access splicers, including main control unit and the video exchange unit being sequentially connected, video input unit and video output unit, the main control unit includes the CPU and control panel being connected with each other, the video exchange unit includes the video input apparatus being sequentially connected, input interface and exchange chip, the video input unit includes the interface conversion circuit being sequentially connected, first FPGA and MCU, the exchange chip connects the interface conversion circuit, the video output unit includes the output interface and display end being sequentially connected, the MCU connections output interface, the CPU connects the interface conversion circuit respectively, first FPGA, the MCU and the output interface.The utility model realizes many video source flexible access processing, can be used widely in large scale LED/LCD splice displaying systems.
Description
Technical field
The utility model belongs to splicer technical field, and in particular to a kind of many video source access splicers.
Background technology
With the development of science and technology, dot spacing LED and large-scale LCD splice displaying system are used more and more
In many industries, such as outdoor advertising, exhibition exhibition booth, traffic scheduling, public security fire-fighting.Over the years, as display terminal is manufactured
The decline of cost, price is also more and more cheaper so that increasing user can use greater area of display terminal, and this is right
The function of display system proposes higher requirement：The diversity of access interface, across the synchronism of screen display, high-resolution image quality
The access of video data, the access of network video signal.It is increasingly increased under the application environment that becomes increasingly complex in order to meet
Functional requirement, it is necessary to which multi-screen splicing device meets these functional requirements in Multi-screen display system, and is the expansion of later system
Open up leaving space.
The video source of existing video montaging device majority access is all single, it is impossible to meet the access splicing of various video source
The requirement of processing, a kind of Split type structure of liquid crystal-spliced device and liquid crystal display of patent（Publication number：CN203930266U）Disclose one
Planting includes splicer casing, splicer fixed plate and output port, and the two ends of splicer casing are respectively fixed with a splicer
Fixed plate, the side of splicer casing is provided with output port；The liquid crystal display includes screen body, screen body bonnet and input port,
Screen body bonnet is fixed on screen body, is covered after screen body and is provided with input port, output port and liquid on the liquid crystal-spliced device
Electrically connected between input port on crystalline substance screen by signal connecting line, this patent makes liquid crystal display separate with liquid crystal-spliced device to set
Put, expand the application of combination, but not from radical change application on access source, it is impossible to realize many video accesses
Splicing.
Utility model content
The purpose of this utility model is to provide a kind of many video source access splicers, realizes at many video source flexible access
Reason, can be used widely in large scale LED/LCD splice displaying systems.
The utility model provides following technical scheme：
A kind of many video source access splicers, including main control unit and video exchange unit, the video input being sequentially connected
Unit and video output unit, the main control unit include the CPU and control panel being connected with each other, the video exchange unit bag
The video input apparatus being sequentially connected, input interface and exchange chip are included, the video input unit includes connecing for being sequentially connected
Mouth change-over circuit, the first FPGA and MCU, the exchange chip connect the interface conversion circuit, the video output unit bag
The output interface and display end being sequentially connected are included, the MCU connections output interface, the CPU connects the interface respectively
Change-over circuit, the first FPGA, the MCU and the output interface.
It is preferred that, the main control unit also include respectively with CPU power supplys be connected and clock apparatus, the power supply is logical
Cross the CPU and provide power supply for whole splicer system, the clock apparatus provides clock by the CPU for whole splicer
Signal, makes video frequency output keep synchronous.
It is preferred that, the input interface include respectively the DVI input interfaces of connection corresponding with the video input apparatus and
Networking input interface, realizes that splicer is accessed in various video source.
It is preferred that, the exchange chip includes video exchange chip and Ethernet switching chip, the video exchange chip
Input connect the DVI input interfaces, the output end of the video exchange chip connects the interface conversion circuit, described
The input of Ethernet switching chip connects the networking input interface, and the output end connection of the Ethernet switching chip is described
Interface conversion circuit, completes the exchange of various video datas.
It is preferred that, the output interface include respectively with the MCU networking output interfaces being connected and DVI output interfaces,
The output end of the networking output interface and the DVI output interfaces connects the corresponding display end respectively, completes video and spells
Connect processing.
It is preferred that, the networking output interface includes the 2nd FPGA and video compress chip being sequentially connected, described second
FPGA input connects the MCU, and the output end of the video compress chip connects the display end, carries out Internet video spelling
Connect compression processing display.
The beneficial effects of the utility model are：Set using crosspoint, realize that many video source access video datas are exchanged；
Input block is set using FPGA and MCU interactions, realizes that input video exchanges splicing, arithmetic speed is fast；Output unit is adopted
With FPGA and general format Duplex treatment, fast video display function is realized, and by video compress chip, realize network video
Pin Hui counties function；Main control unit is controlled comprehensively, simple to operate easy to spread.
Brief description of the drawings
Accompanying drawing is used for providing further understanding to of the present utility model, and constitutes a part for specification, with this practicality
New embodiment is used to explain the utility model together, does not constitute to limitation of the present utility model.In the accompanying drawings：
Fig. 1 is the utility model structural representation；
Marked in figure：1. video exchange unit；2. video input unit；3. video output unit；4. main control unit.
Embodiment
As shown in figure 1, a kind of many video source access splicers, including main control unit 4 and the video exchange list being sequentially connected
Member 1, video input unit 2 and video output unit 3, main control unit 4 include the CPU and control panel being connected with each other, CPU difference
Connect video input unit 2 and video output unit 4.Video input unit 2, is responsible for access and the effect process of vision signal；
Video output unit 3, main responsible vision signal is output to the effect process of corresponding display unit and output vision signal；Depending on
Frequency crosspoint 1, main responsible vision signal carries out the exchange from input port to output port on request, and director data is each
Intercoursing between individual plate；Main control unit 4, is responsible for the communication with host computer, and the instruction of host computer is handed down into corresponding work(
Energy unit is specifically operated, while the working condition of monitoring system, prompting is sent when noting abnormalities to client.
As shown in figure 1, video exchange unit 1 includes video input apparatus, input interface and the exchange chip being sequentially connected,
Input interface includes the DVI input interfaces and networking input interface of connection corresponding with video input apparatus respectively, realizes a variety of regard
Splicer is accessed in frequency source；Exchange chip includes video exchange chip and Ethernet switching chip, the input of video exchange chip
DVI input interfaces are connected, the output end connecting interface change-over circuit of video exchange chip, the input of Ethernet switching chip connects
Networking input interface is connect, the output end connecting interface change-over circuit of Ethernet switching chip completes the exchange of various video datas.
As shown in figure 1, video input unit 2 includes interface conversion circuit, the first FPGA and MCU being sequentially connected, exchange
Chip connecting interface change-over circuit, video input unit 2 needs a variety of different video interfaces of adaptation, such as DVI/HDMI/VGA/
SDI/IP etc., so the interface different to each, is required for different interface conversion circuits, changes the vision signal of input
For rgb signal or YCbCr signals, it is input in FPGA and is handled, wherein, IP tablets are more special, and what it was accessed is
Network video signal after compression is condensed to after original vision signal, it is necessary to decompress, and is reconverted into the video that FPGA can be received
Form；FPGA plays GPU in input block, and storage, processing, form completely for doing vision signal are changed and turned
Hair, one group of control register is defined inside FPGA, for being communicated with onboard single-chip microcomputer, receives and completes main control unit 4
The instruction issued.In video input unit 2, FPGA needs to carry out the amplification of incoming video signal, reduction, brightness, contrast
Handled with the regulation of color saturation etc.；Video input unit 2 is less demanding to onboard single-chip microcomputer, mainly realizes the friendship of instruction
Mutually.
As shown in figure 1, video output unit 3 includes the output interface and display end being sequentially connected, MCU connection outputs connect
Mouthful, output interface includes the networking output interface and DVI output interfaces being connected respectively with MCU, networking output interface and DVI outputs
The output end of interface connects corresponding display end respectively, completes video-splicing processing；Networking output interface includes what is be sequentially connected
2nd FPGA and video compress chip, the 2nd FPGA input connection MCU, the output end connection display of video compress chip
End, carries out Internet video splicing compression processing display.
As shown in figure 1, main control unit 4 also includes the power supply and clock apparatus being connected respectively with CPU, power supply is by CPU
Whole splicer system provides power supply, and clock apparatus provides clock signal for whole splicer by CPU, keeps video frequency output
It is synchronous.Main control unit 4 is the brain of whole splicing equipment, is communicated by control panel, realizes that instruction issues function, realized simultaneously
Monitoring to whole splicer.
Preferred embodiment of the present utility model is the foregoing is only, the utility model is not limited to, although ginseng
The utility model is described in detail according to previous embodiment, for those skilled in the art, it still can be with
Technical scheme described in foregoing embodiments is modified, or equivalent substitution is carried out to which part technical characteristic.It is all
Within spirit of the present utility model and principle, any modification, equivalent substitution and improvements made etc. should be included in this practicality
Within new protection domain.
Claims (6)
1. a kind of many video sources access splicer, it is characterised in that including main control unit and the video exchange unit being sequentially connected,
Video input unit and video output unit, the main control unit include the CPU and control panel being connected with each other, and the video is handed over
Video input apparatus, input interface and exchange chip that unit includes being sequentially connected are changed, the video input unit is included successively
The interface conversion circuit of connection, the first FPGA and MCU, the exchange chip connect the interface conversion circuit, and the video is defeated
Go out output interface and display end that unit includes being sequentially connected, the MCU connections output interface, the CPU is connected respectively
The interface conversion circuit, the first FPGA, the MCU and the output interface.
2. a kind of many video source access splicers according to claim 1, it is characterised in that the main control unit also includes
Respectively with the CPU power supplys being connected and clock apparatus.
3. a kind of many video source access splicers according to claim 1, it is characterised in that the input interface includes dividing
The DVI input interfaces and networking input interface of connection not corresponding with the video input apparatus.
4. a kind of many video source access splicers according to claim 3, it is characterised in that the exchange chip includes regarding
Frequency exchange chip and Ethernet switching chip, the input of the video exchange chip connect the DVI input interfaces, described to regard
The output end of frequency exchange chip connects the interface conversion circuit, and the input of the Ethernet switching chip connects the network
Input interface, the output end of the Ethernet switching chip connects the interface conversion circuit.
5. a kind of many video source access splicers according to claim 1, it is characterised in that the output interface includes dividing
Not with the MCU networking output interfaces being connected and DVI output interfaces, the networking output interface and the DVI output interfaces
Output end connect the corresponding display end respectively.
6. a kind of many video source access splicers according to claim 5, it is characterised in that the networking output interface bag
The 2nd FPGA and video compress chip being sequentially connected are included, the input of the 2nd FPGA connects the MCU, the video pressure
The output end of shrinking chip connects the display end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720324208.8U CN206575509U (en) | 2017-03-30 | 2017-03-30 | A kind of many video source access splicers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720324208.8U CN206575509U (en) | 2017-03-30 | 2017-03-30 | A kind of many video source access splicers |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206575509U true CN206575509U (en) | 2017-10-20 |
Family
ID=60053297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720324208.8U Active CN206575509U (en) | 2017-03-30 | 2017-03-30 | A kind of many video source access splicers |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206575509U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107888862A (en) * | 2017-11-24 | 2018-04-06 | 威创集团股份有限公司 | A kind of signal shunt method and system applied to video-splicing |
| CN109803099A (en) * | 2018-12-24 | 2019-05-24 | 南京巨鲨显示科技有限公司 | A kind of dynamic management approach of video montaging device and its show layers |
-
2017
- 2017-03-30 CN CN201720324208.8U patent/CN206575509U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107888862A (en) * | 2017-11-24 | 2018-04-06 | 威创集团股份有限公司 | A kind of signal shunt method and system applied to video-splicing |
| CN107888862B (en) * | 2017-11-24 | 2020-12-11 | 威创集团股份有限公司 | Signal distribution method and system applied to video splicing |
| CN109803099A (en) * | 2018-12-24 | 2019-05-24 | 南京巨鲨显示科技有限公司 | A kind of dynamic management approach of video montaging device and its show layers |
| CN109803099B (en) * | 2018-12-24 | 2021-10-22 | 南京巨鲨显示科技有限公司 | Dynamic management method for display layers of video splicer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN206698331U (en) | Multi-screen image processing unit | |
| CN101277395B (en) | Method and apparatus for partitioning HDMI and Display Port image signal | |
| CN101819755A (en) | Monitor joined screen with function of displaying multi-channel video signals and realization method thereof | |
| CN206807643U (en) | 4K image mosaics display device and display system based on ARM frameworks | |
| CN106648408A (en) | Touch data processing method, device, touch screen and splicing display system | |
| CN103197801A (en) | Integrated machine and method for realizing simultaneous touch of external equipment and built-in system | |
| CN206575509U (en) | A kind of many video source access splicers | |
| CN113377313B (en) | Multi-screen multiplexing display device and method | |
| CN104571991A (en) | Control panel, illumination equipment and illumination method | |
| CN201044165Y (en) | High resolution split joint television curtain wall | |
| CN107529024A (en) | Multifunctional image video switch boards | |
| CN105553835A (en) | Method and system of ultrahigh definition large screen for synchronously displaying client data interfaces | |
| CN204681493U (en) | A kind of 4K multi-screen splicing processor | |
| CN106791649A (en) | A kind of display system and display methods of achievable shuangping san | |
| CN102497526B (en) | Method and system for displaying multiple channels of video by same link | |
| CN201655249U (en) | Integrated audio/video controller for LED display | |
| CN203299695U (en) | E-book and tablet computer two-in-one application device | |
| CN206100251U (en) | Demonstration controlling means of concatenation screen | |
| CN201255933Y (en) | Digital network interactive teaching system | |
| CN204272298U (en) | Multichannel expanded type multi-screen splicer | |
| CN203300153U (en) | Ultrahigh-resolution-ratio LED splicing displaying system | |
| CN104202539A (en) | Tiled screen meeting display method | |
| CN205263790U (en) | Display control board | |
| WO2016169513A1 (en) | Bicycle wheel light system transmitting data via wifi | |
| CN100461087C (en) | Computer system possessing analog digital video output, host and video transmission device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Splicing device is inserted in many videos source Effective date of registration: 20180904 Granted publication date: 20171020 Pledgee: Bank of Nanjing Jiangbei District branch of Limited by Share Ltd Pledgor: NANJING LOFTY DIGITAL TECHNOLOGY CO., LTD. Registration number: 2018320000159 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |