CN206506514U - A kind of multiplex interface circuit and gateway - Google Patents
A kind of multiplex interface circuit and gateway Download PDFInfo
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- CN206506514U CN206506514U CN201720195819.7U CN201720195819U CN206506514U CN 206506514 U CN206506514 U CN 206506514U CN 201720195819 U CN201720195819 U CN 201720195819U CN 206506514 U CN206506514 U CN 206506514U
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Abstract
The utility model provides a kind of multiplex interface circuit and gateway, and the multiplex interface circuit includes the first binding post, the second binding post, the 3rd binding post and multiplex circuit.First binding post is multiple, and each first binding post is connected with each sensor respectively.Each first binding post includes multiple pins respectively, and the multiple pin includes power pins, grounding pin and input/output pin.One end of second binding post is connected with the sensor, the other end is connected with the multiplex circuit.3rd binding post is connected with the sensor.The multiplex interface circuit can be adapted to different interface types, different installation environments and use environment, and with high-protection level.
Description
Technical field
The utility model is related to electronic measuring technology field, in particular to a kind of multiplex interface circuit and gateway.
Background technology
Smart city is exactly with information and means of communication sensing, analysis, the every pass for integrating city operations core system
Key information, so as to make intelligence to the various demands including the people's livelihood, environmental protection, public safety, urban service, industry and commerce activity
Response.Its essence is advanced information technology is utilized, realize the management of city intelligent formula and run, and then created for the people in city
More good days, promotes harmony, the Sustainable Growth in city.Smart city has substantial amounts of nerve endings, extends to city
Every aspect, and these nerve endings are typically difference in functionality or the sensor of model.Sensor is adopted to Various types of data
Collection, then by the management platform of wired or wireless link transmission to smart city, with the value of further mining data.
In the big data epoch, as people recognize and studied for promiscuity between things, sensor reads and stored
The value of mass data be even more to estimate.For the construction of smart city, how quickly, efficient, substantial amounts of each pass is read
Data in sensor become particularly significant.
Inventor it has been investigated that, in the prior art, the sensing of multiple interfaces type is adapted to using unified interface
Device, improves the versatility of equipment.But, because gateway as neuron in smart city is widespread deployment, and its portion
Affix one's name to environment relative complex.Interface circuit barrier propterty of the prior art is poor, it is impossible to adapt to the data access under a variety of environment.Cause
How this, realize that a kind of barrier propterty height, convenient disassembly, adaptation number of sensors, the interface circuit more than type are particularly significant.
Utility model content
In view of this, the purpose of this utility model is to provide a kind of multiplex interface circuit and gateway, to solve above-mentioned ask
Topic.
The utility model preferred embodiment provides a kind of multiplex interface circuit, described multiple for being connected with multiple sensors
Include the first binding post, the second binding post, the 3rd binding post and multiplex circuit with interface circuit；
First binding post is multiple, and each first binding post is connected with each sensor respectively, each institute
State the first binding post includes multiple pins respectively, and the multiple pin includes power pins, grounding pin and input/output
Pin；
One end of second binding post is connected with the sensor, the other end is connected with the multiplex circuit；
3rd binding post is connected with the sensor.
In the utility model embodiment is preferably selected, in above-mentioned multiplex interface circuit, multiple first wiring
The input/output pin of any one the first binding post in terminal is multiple, and the input/output pin at least includes electricity
Press analogue type pin, current analog type pin, data signal pin, IIC pins, SPI pins, TTL pins, RS232 pins with
And one kind in RS485 pins.
In the utility model embodiment is preferably selected, in above-mentioned multiplex interface circuit, multiple first wiring
The power pins of any one the first binding post in terminal are multiple, each power pins of same first binding post
Voltage magnitude it is different.
In the utility model embodiment is preferably selected, in above-mentioned multiplex interface circuit, multiple first wiring
The power pins of any one the first binding post in terminal are 3 and voltage magnitude is respectively 3.3V, 5V and 12V.
In the utility model embodiment is preferably selected, in above-mentioned multiplex interface circuit, multiple first wiring
The grounding pin of any one the first binding post in terminal with least including power supply pin, simulation ground pin and digitally
One kind in pin.
In the utility model embodiment is preferably selected, in above-mentioned multiplex interface circuit, first binding post
For 6, respectively No. one binding post, No. two binding posts, No. three binding posts, No. four binding posts, No. five binding posts
And No. six binding posts.
In the utility model embodiment is preferably selected, in above-mentioned multiplex interface circuit, a binding post
Draw with the input/output pin of No. two binding posts including voltage analog type pin, current analog type pin and data signal
Pin, the input/output pin of No. three binding posts draws including voltage analog type pin, current analog type pin and IIC
Pin, the input/output pin of No. four binding posts includes SPI pins, the input/output pin of No. five binding posts
Including TTL pins and RS232 pins, the input/output pin of No. six binding posts includes RS232 pins and RS485 draws
Pin.
In the utility model embodiment is preferably selected, in above-mentioned multiplex interface circuit, a binding post
Include simulation ground, digitally and power supply, the grounding lead of No. three binding posts with the grounding pins of No. two binding posts
Pin is included digitally with power supply, the grounding pin of No. four binding posts, No. five binding posts and No. six binding posts
Including power supply.
In the utility model embodiment is preferably selected, in above-mentioned multiplex interface circuit, the multiplex circuit includes
Simulation multiplexer and amplifying circuit, the input of the simulation multiplexer is connected with second binding post, output end with
The input connection of the amplifying circuit.
On the basis of the above, the utility model embodiment additionally provides a kind of gateway, and the gateway includes sensor, processing
Device and multiplex interface circuit described above；
The multiplex interface circuit includes the first binding post, the second binding post, the 3rd binding post and multiplexing electricity
Road；
One end of first binding post is connected with the sensor, the other end is connected with the processor, and described
One end of two binding posts is connected with the sensor, the other end is connected after connecting the multiplex circuit with the processor, institute
The one end for stating the 3rd binding post is connected with the sensor, the other end is connected with the processor.
Multiplex interface circuit and gateway that the utility model is provided, including different types of first binding post, second connect
Line terminals and the 3rd binding post.Wherein, the first binding post is multiple, multiple first binding posts any one the
One binding post includes multiple different types of input/output pins.The multiplex interface circuit can be adapted to different interface classes
Type, different installation environments and use environment, and with high-protection level.
To enable above-mentioned purpose of the present utility model, feature and advantage to become apparent, preferred embodiment cited below particularly, and
Coordinate appended accompanying drawing, be described in detail below.
Brief description of the drawings
The schematic block diagram for the multiplex interface circuit that Fig. 1 provides for the utility model embodiment.
The circuit theory diagrams for each first binding post that Fig. 2 provides for the utility model embodiment.
The circuit theory diagrams for the voltage analog process circuit that Fig. 3 provides for the utility model embodiment.
The circuit theory diagrams for the current analog process circuit that Fig. 4 provides for the utility model embodiment.
The circuit theory diagrams for the RS485 converters that Fig. 5 provides for the utility model embodiment.
The circuit theory diagrams for the RS232 converters that Fig. 6 provides for the utility model embodiment.
The pinouts for the processor that Fig. 7 provides for the utility model embodiment.
Icon：100- multiplex interface circuits；The binding posts of 110- first；The binding posts of 120- second；121- multiplex circuits；
The binding posts of 130- the 3rd；140- voltage analog process circuits；The two-way suppression diodes of T1- first；The pull down resistors of R1- first；
The pull down resistors of R2- second；The current-limiting resistances of R3- first；The current-limiting resistances of R4- second；The electric capacity of C1- first；The electric capacity of C2- second；C3-
Three electric capacity；The operational amplifiers of U1- first；150- current analog process circuits；The two-way suppression diodes of T2- second；Under R5- the 3rd
Pull-up resistor；The pull down resistors of R6- the 4th；The current-limiting resistances of R7- the 3rd；The current-limiting resistances of R8- the 4th；The electric capacity of C4- the 4th；The electricity of C5- the 5th
Hold；The electric capacity of C6- the 6th；The operational amplifiers of U2- second；160-RS485 interface circuits；170-RS232 interface circuits.
Embodiment
It is new below in conjunction with this practicality to make the purpose, technical scheme and advantage of the utility model embodiment clearer
Accompanying drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that retouched
The embodiment stated is a part of embodiment of the utility model, rather than whole embodiments.Generally here described in accompanying drawing and
The component of the utility model embodiment shown can be arranged and designed with a variety of configurations.
Therefore, the detailed description of embodiment of the present utility model below to providing in the accompanying drawings is not intended to limit requirement
The scope of the present utility model of protection, but it is merely representative of selected embodiment of the present utility model.Based in the utility model
Embodiment, the every other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made, all
Belong to the scope of the utility model protection.
It should be noted that：Similar label and letter represents similar terms in following accompanying drawing, therefore, once a certain Xiang Yi
It is defined in individual accompanying drawing, then it further need not be defined and explained in subsequent accompanying drawing.
, it is necessary to explanation, the orientation of the instruction such as term " one end ", " other end " in foregoing description of the present utility model
Or position relationship is that, based on orientation shown in the drawings or position relationship, or the utility model product is usually put when using
Orientation or position relationship, are for only for ease of description the utility model and simplify description, rather than indicate or imply signified dress
Put or element there must be specific orientation, with specific azimuth configuration and operation, therefore it is not intended that to the utility model
Limitation.In addition, term " first ", " second ", " the 3rd ", " the 4th " etc. are only used for distinguishing description, and it is not intended that indicating
Or imply relative importance.
Referring to Fig. 1, a kind of schematic structure frame of the multiplex interface circuit 100 provided for the utility model embodiment
Figure.The multiplex interface circuit 100 is used to be connected with multiple sensors, as shown in figure 1, the multiplex interface circuit 100 includes
First binding post 110, the second binding post 120, the 3rd binding post 130 and multiplex circuit 121.First terminals
Son 110 is multiple, and one end of each first binding post 110 can be connected, separately with each different types of sensor respectively
One end can be connected with processor.
One end of second binding post 120 is connected with the sensor, the other end connect the multiplex circuit 121 it
It is connected afterwards with the processor.One end of 3rd binding post 130 is connected with the sensor, the other end and the processing
Device is connected.
Alternatively, each different types of sensor can gather different types of signal to generate different induced signals.
And by first binding post 110, the second binding post 120 and the 3rd binding post 130 by induced signal send to
Processor, so that processor is handled each induced signal.
Alternatively, each described first binding post 110 includes multiple pins respectively, according to first binding post 110
The type of the sensor of adaptation, the first binding post 110 can have different types of pin.Wherein, the multiple pin is at least
Including power pins, grounding pin and input/output pin, to ensure that the first binding post 110 can be normally carried out work.
Alternatively, the input/output pin of any one the first binding post 110 in first binding post 110
It can also be multiple that can be one.In the present embodiment, it is contemplated that the versatility of the first binding post 110, so as to suitable
With a variety of different types of sensors, the input/output pin of first binding post 110 is set to multiple.Also, it is same
The type of the input/output pin of first binding post 110 is different.
Alternatively, in the present embodiment, the multiplex circuit 121 includes simulation multiplexer and amplifying circuit.The simulation
The input of multiplexer is connected with second binding post 120, output end is connected with the input of the amplifying circuit.It is described
The output end of amplifying circuit is connected with the processor.Alternatively, in the present embodiment, the simulation multiplexer can be selected
CD4052.Alternatively, the external sensor being connected with second binding post 120 can be the number of following several interface types
Word sensor：Spi bus interface, iic bus interface, switching value interface or single bus interface.Signal is gathered in external sensor
Afterwards, by it by sending into the amplifying circuit after second binding post 120 and the simulation multiplexer, signal is amplified
The processor is transported to, so that the processor is handled.
Alternatively, in the present embodiment, the 3rd binding post 130 is the binding post of traditional type, i.e., each the
Three binding posts 130 can only adapt to a type of sensor.Alternatively, the number of the 3rd binding post 130 can be with
Can also be multiple for one.
As shown in Fig. 2 alternatively, in the present embodiment, the number of first binding post 110 is 6, respectively one
Number binding post P1, No. two binding post P2, No. three binding post P3, No. four binding post P4, No. five binding post P5 and
No. six binding post P6.Wherein, the power supply of any one the first binding post 110 in the multiple first binding post 110
Pin is 3, and its voltage magnitude is respectively 3.3V, 5V and 12V.Supply voltage can be according to the job requirement of sensor
To determine.
The input/output pin of any one the first binding post 110 in the multiple first binding post 110
At least include voltage analog type pin, current analog type pin, data signal pin, IIC pins, SPI pins, RS232 pins
And one kind in RS485 pins.Any one the first binding post 110 in the multiple first binding post 110 connects
Ground pin with least including power supply pin GND, simulation ground pin AGND and digitally one kind in pin DGND.
Specifically, the input/output pin of a binding post P1 includes voltage analog type pin AI1, current-mode
Plan type pin AI2 and data signal pin DI1.The grounding pin of a number binding post P1 includes simulation ground pin
AGND, digitally pin DGND and power supply ground pin GND.
The input/output pin of No. two binding post P2 includes voltage analog type pin AI3, current analog type pin
AI4 and data signal pin DI2.The grounding pin of No. two binding post P2 includes simulation ground pin AGND, digitally
Pin DGND and power supply ground pin GND.
The input/output pin of No. three binding post P3 includes voltage analog type pin AI5, current analog type pin
AI6 and IIC pins (SCL1, SAD1).The grounding pin of No. three binding post P3 includes digitally pin DGND and electricity
Source ground pin GND.
The input/output pin of No. four binding post P4 includes SPI pins (SPI2_SCK, SPI2_NSS, SPI2_
MOSI、SPI2_MISO).The grounding pin of No. four binding post P4 includes power supply ground pin GND.
The input/output pin of No. five binding post P5 includes TTL pins (RX, TX) and RS232 pins
(R232_RX1、R232_TX1).The grounding pin of No. five binding post P5 includes power supply ground pin GND.
The input/output pin of No. six binding post P6 includes RS485 pins (VDD_485, GND_485,485_
A1,485_B1) and RS232 pins (R232_RX1, R232_TX1).The grounding pin of No. six binding post P6 includes electricity
Source ground pin GND.
Alternatively, as shown in figure 3, the voltage analog type pin is integrated with voltage analog process circuit 140, the voltage
The output end of analog processing circuit 140 is connected with the processor.As shown in figure 4, the current analog type pin is integrated with electricity
Flow field simulation process circuit 150, the output end of the current analog process circuit 150 is connected with the processor.As shown in figure 5,
The RS485 pins are integrated with RS485 interface circuits 160, output end and the processor of the RS485 interface circuits 160
Connection.As shown in fig. 6, the RS232 pins are integrated with RS232 interface circuits 170, the output of the RS232 interface circuits 170
End is connected with the processor.
Fig. 3 and Fig. 7 are please referred to, the voltage analog process circuit 140 includes the first two-way suppression voltage-regulator diode
T1, the first pull down resistor R1, the second pull down resistor R2, the first current-limiting resistance R3, the second current-limiting resistance R4, the first electric capacity C1,
Two electric capacity C2, the 3rd electric capacity C3 and the first operational amplifier U1.
One end of the first two-way suppression voltage-regulator diode T1 is connected with the output end of voltage-type analog sensor, another
End ground connection.One end of the first pull down resistor R1 is connected with the output end of voltage-type analog sensor, other end ground connection.It is described
First current-limiting resistance R3 one end is connected with the output end of voltage-type analog sensor, the other end connects second pull down resistor
It is grounded after R2.The normal phase input end of the first operational amplifier U1 is connected, instead with one end of the first current-limiting resistance R3
Phase input is connected with the output end of the first operational amplifier U1.One end of the first electric capacity C1 and first current limliting
Resistance R3 one end connection, other end ground connection.One end of the second electric capacity C2 and the power supply of the first operational amplifier U1
Input connection, other end ground connection.One end of the second current-limiting resistance R4 and the output end of the first operational amplifier U1
Connection, the other end are connected with the voltage-type simulation input pin AD_IN1-AD_IN3 of the processor.The 3rd electric capacity C3's
One end is connected with one end of the second current-limiting resistance R4, other end ground connection.Alternatively, in the present embodiment, the processor
Model STM32L152VBT6.
Fig. 4 and Fig. 7 are please referred to, the current analog process circuit 150 includes the second two-way suppression voltage-regulator diode
T2, the 3rd pull down resistor R5, the 4th pull down resistor R6, the 3rd current-limiting resistance R7, the 4th current-limiting resistance R8, the 4th electric capacity C4,
Five electric capacity C5, the 6th electric capacity C6 and the second operational amplifier U2.
One end of the second two-way suppression voltage-regulator diode T2 is connected with the output end of current mode analog sensor, another
End ground connection.One end of the 3rd pull down resistor R5 is connected with the output end of current mode analog sensor, other end ground connection.It is described
3rd current-limiting resistance R7 one end is connected with the output end of current mode analog sensor, the other end connects the 4th pull down resistor
It is grounded after R6.The normal phase input end of the second operational amplifier U2 is connected, instead with one end of the 3rd current-limiting resistance R7
Phase input is connected with the output end of the second operational amplifier U2.One end of the 4th electric capacity C4 and the 3rd current limliting
Resistance R7 one end connection, other end ground connection.One end of the 5th electric capacity C5 and the power supply of the second operational amplifier U2
Input connection, other end ground connection.One end of the 4th current-limiting resistance R8 and the output end of the second operational amplifier U2
Connection, the other end are connected with the current mode simulation input pin AD_IN4-AD_IN6 of the processor.
Fig. 5 and Fig. 7 are please referred to, the RS485 interface circuits 160 include RS485 converters.Alternatively, in this reality
Apply in example, RS485 converters use MAX485.Wherein, 12 pin and 13 pin are the A and B two during RS485 communicates in MAX485
Individual pin.3 pin and 6 pin are coupled with RXD the and TXD pins of the processor, are directly carried out using the processor UART
Data receiver and transmission.4 pin and 5 pin are direction pin, and receiver is enabled wherein 4 pin are low levels, and 5 pin are that high level enable is defeated
Go out driver.The two pins connect together, when not sending data, and it is low level to keep the two pins, allow at MAX485
In reception state.When needing to send data, this pin is drawn high, to send data.Pending data is drawn again after being sent
This low pin.
The major function of the RS485 interface circuits 160 is to turn the transmission signal of the processor by " transmitter "
Change the differential signal in communication network into, the differential signal in communication network can also be converted into by " receiver " described
The signal that processor is received.Any instant, RS485 converters can only operate in one of " reception " or " transmission " both of which.
Fig. 6 and Fig. 7 are please referred to, the RS232 interface circuits 170 include RS232 converters.Alternatively, in this reality
Apply in example, RS232 converters use MAX3232.MAX3232 has two-way receiver and two-way driver.Wherein, first
Road COMS, TTL logic level output pin R1OUT is connected with the USART2_RX pins of the processor.First via COMS, TTL
Logic level input pin T1IN is connected with the USART2_TX of the processor.
The utility model additionally provides a kind of gateway, and the gateway includes sensor, processor and the multiplex interface
Circuit 100.The multiplex interface circuit 100 includes the first binding post 110, the second binding post 120, the 3rd binding post
130 and multiplex circuit 121.
One end of first binding post 110 is connected with the sensor, the other end is connected with the processor.It is described
One end of second binding post 120 is connected with the sensor, the other end connect after the multiplex circuit 121 with the processing
Device is connected.One end of 3rd binding post 130 is connected with the sensor, the other end is connected with the processor.
In summary, the utility model is provided a kind of multiplex interface circuit 100 and gateway, including interface type are different
First binding post 110, the second binding post 120 and the 3rd binding post 130.First binding post 110 to be multiple,
And any one first binding post 110 in multiple first binding posts 110 includes multiple different types of input/output
Pin.The multiplex interface circuit 100 by a variety of different types of binding posts, can realize be adapted to different interface types,
Different installation environments and use environment, and with high-protection level.
In description of the present utility model, unless otherwise clearly defined and limited, term " setting ", " connection " should be done extensively
Reason and good sense solution, for example, it may be being fixedly connected or being detachably connected, or is integrally connected；Can mechanically connect,
It can be electrical connection；Can be joined directly together, can also be indirectly connected to by intermediary, can be the company of two element internals
It is logical.For the ordinary skill in the art, it can understand that above-mentioned term is specific in the utility model with concrete condition
Implication.
Preferred embodiment of the present utility model is the foregoing is only, the utility model is not limited to, for this
For the technical staff in field, the utility model can have various modifications and variations.It is all it is of the present utility model spirit and principle
Within, any modification, equivalent substitution and improvements made etc. should be included within protection domain of the present utility model.
Claims (10)
1. a kind of multiplex interface circuit, for being connected with multiple sensors, it is characterised in that the multiplex interface circuit includes the
One binding post, the second binding post, the 3rd binding post and multiplex circuit；
First binding post is multiple, and each first binding post is connected with each sensor respectively, and each described the
One binding post includes multiple pins respectively, and the multiple pin draws including power pins, grounding pin and input/output
Pin；
One end of second binding post is connected with the sensor, the other end is connected with the multiplex circuit；
3rd binding post is connected with the sensor.
2. multiplex interface circuit according to claim 1, it is characterised in that any in multiple first binding posts
The input/output pin of one the first binding post is multiple, and the input/output pin at least draws including voltage analog type
Pin, current analog type pin, data signal pin, IIC pins, SPI pins, TTL pins, RS232 pins and RS485 pins
In one kind.
3. multiplex interface circuit according to claim 1, it is characterised in that any in multiple first binding posts
The power pins of one the first binding post are multiple, and the voltage magnitude of each power pins of same first binding post is not
Together.
4. multiplex interface circuit according to claim 3, it is characterised in that any in multiple first binding posts
The power pins of one the first binding post are 3 and voltage magnitude is respectively 3.3V, 5V and 12V.
5. multiplex interface circuit according to claim 1, it is characterised in that any in multiple first binding posts
The grounding pin of one the first binding post with least including power supply pin, simulation ground pin and digitally one in pin
Kind.
6. multiplex interface circuit according to claim 1, it is characterised in that first binding post is 6, is respectively
A number binding post, No. two binding posts, No. three binding posts, No. four binding posts, No. five binding posts and No. six wiring
Terminal.
7. multiplex interface circuit according to claim 6 a, it is characterised in that binding post and No. two terminals
The input/output pin of son includes voltage analog type pin, current analog type pin and data signal pin, and described No. three connect
The input/output pin of line terminals includes voltage analog type pin, current analog type pin and IIC pins, and described No. four connect
The input/output pin of line terminals includes SPI pins, the input/output pins of No. five binding posts include TTL pins and
RS232 pins, the input/output pin of No. six binding posts includes RS232 pins and RS485 pins.
8. multiplex interface circuit according to claim 6 a, it is characterised in that binding post and No. two terminals
The grounding pin of son includes simulation ground, digitally and power supply, and the grounding pin of No. three binding posts is included digitally
With power supply, the grounding pin of No. four binding posts, No. five binding posts and No. six binding posts is with including power supply.
9. multiplex interface circuit according to claim 1, it is characterised in that the multiplex circuit include simulation multiplexer with
And amplifying circuit, the input of the simulation multiplexer is connected with second binding post, output end and the amplifying circuit
Input connection.
10. a kind of gateway, it is characterised in that including the multiplexing described in sensor, processor and claim 1-9 any one
Interface circuit；
The multiplex interface circuit includes the first binding post, the second binding post, the 3rd binding post and multiplex circuit；
One end of first binding post is connected with the sensor, the other end is connected with the processor, and described second connects
One end of line terminals is connected with the sensor, the other end is connected after connecting the multiplex circuit with the processor, and described the
One end of three binding posts is connected with the sensor, the other end is connected with the processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720195819.7U CN206506514U (en) | 2017-03-01 | 2017-03-01 | A kind of multiplex interface circuit and gateway |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720195819.7U CN206506514U (en) | 2017-03-01 | 2017-03-01 | A kind of multiplex interface circuit and gateway |
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| CN206506514U true CN206506514U (en) | 2017-09-19 |
Family
ID=59840846
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108182160A (en) * | 2017-12-28 | 2018-06-19 | 北京守朴科技有限公司 | General-purpose interface input signal automatic identifying method, device and signal handling equipment |
| CN108874713A (en) * | 2018-05-31 | 2018-11-23 | 联想(北京)有限公司 | A kind of information processing method and device |
| CN113167822A (en) * | 2018-12-19 | 2021-07-23 | 法国大陆汽车公司 | Automatic detection device for connection between electronic devices |
-
2017
- 2017-03-01 CN CN201720195819.7U patent/CN206506514U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108182160A (en) * | 2017-12-28 | 2018-06-19 | 北京守朴科技有限公司 | General-purpose interface input signal automatic identifying method, device and signal handling equipment |
| CN108874713A (en) * | 2018-05-31 | 2018-11-23 | 联想(北京)有限公司 | A kind of information processing method and device |
| CN108874713B (en) * | 2018-05-31 | 2021-10-22 | 联想(北京)有限公司 | Information processing method and device |
| CN113167822A (en) * | 2018-12-19 | 2021-07-23 | 法国大陆汽车公司 | Automatic detection device for connection between electronic devices |
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