CN206461708U - ADC dynamic logics reverse circuit, word line voltage selection circuit and storage unit circuit - Google Patents
ADC dynamic logics reverse circuit, word line voltage selection circuit and storage unit circuit Download PDFInfo
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- CN206461708U CN206461708U CN201621479337.6U CN201621479337U CN206461708U CN 206461708 U CN206461708 U CN 206461708U CN 201621479337 U CN201621479337 U CN 201621479337U CN 206461708 U CN206461708 U CN 206461708U
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Abstract
The utility model is related to ADC dynamic logics reverse circuit, word line voltage selection circuit and storage unit circuit.ADC dynamic logic reverse circuits include：First PMOS transistor, source electrode connects the first power end, and drain electrode connection first node, grid is connected to the first control end；First nmos pass transistor, source electrode connection second source end, drain electrode connection Section Point, grid is connected to the 3rd node；The multistage reverse circuit being sequentially connected, multistage reverse circuit is parallel between first node and Section Point, and the output end of upper level reverse circuit is connected to the input of next stage reverse circuit；Input circuit, for providing input signal to first order reverse circuit；First electric capacity, is connected between first node and Section Point.In the utility model, logic reverse circuit and memory cell and power end and ground terminal are separated, and write operation and the read operation or reset operating control signal of memory cell are separated, it is to avoid circuit switching process produces influence to power end and ground terminal, improves image quality.
Description
Technical field
The utility model is related to IC design technical field, more particularly to ADC dynamic logics reverse circuit, wordline electricity
Press selection circuit and storage unit circuit.
Background technology
Existing frequently-used cmos image sensor is exported by arranging parallel logic circuit mostly, and is stored in SRAM
Memory.In existing logic circuit, cmos circuit is realized in switching process by carrying out discharge and recharge to node capacitor
Logic turn over function, and there is a situation where that nmos pass transistor and PMOS transistor are simultaneously turned in charge and discharge process, so that
The fluctuation of power end and ground terminal can be caused.In addition, have what many column logic circuitries were overturn in imaging sensor photo-process simultaneously
Situation, while energizing signal is write into SRAM, multiple row ADC CMOS logic works simultaneously also results in the fluctuation of power supply and ground,
So as to influence picture quality.
Utility model content
The purpose of this utility model is the ADC dynamic logic reverse circuits for providing a kind of imaging sensor, solves existing
In technology the problem of the influence of fluctuations image quality of power end and ground terminal.
Another object of the present utility model is also to provide a kind of word line voltage selection circuit, by the write operation of memory cell
Separated with read operation or the control signal for resetting operation, prevent read operation and reset operation control circuit to for producing write operation
The ADC dynamic logics reverse circuit of control signal produces influence.
A further object of the present utility model is to provide a kind of storage unit circuit, by memory cell and power end and ground terminal
Separate, interference of the cut-off multiple row SRAM in ablation process to power supply and ground.
In order to solve the above-mentioned technical problem, the utility model provides a kind of ADC dynamic logics reverse circuit, including：
First PMOS transistor, source electrode connects the first power end, and drain electrode connection first node, grid is connected to the first control
End；
First nmos pass transistor, source electrode connection second source end, drain electrode connection Section Point, grid is connected to Section three
Point；
The multistage reverse circuit being sequentially connected, the multistage reverse circuit is parallel to the first node and the second section
Between point, and the output end of upper level reverse circuit is connected to the input of next stage reverse circuit；
Input circuit, the input circuit is used to provide input signal to first order reverse circuit；
First electric capacity, is connected between the first node and the Section Point.
Optionally, reverse circuit described in every one-level includes：
Second PMOS transistor, source electrode connects the first node, and drain electrode connection the 3rd node, grid is connected to institute
State the first control end；
Second nmos pass transistor, source electrode connects the Section Point, and drain electrode connection the 3rd node, grid connection is described
The output end of input circuit or the output end of upper level reverse circuit；
3rd PMOS transistor, source electrode connects the first node, the input of drain electrode connection next stage reverse circuit, grid
Pole connects the 3rd node；
3rd nmos pass transistor, source electrode connects the Section Point, the input of drain electrode connection next stage reverse circuit, grid
Pole connects the second control end.
Optionally, the input circuit includes：
4th PMOS transistor, source electrode connects the 3rd power end, drain electrode connection fourth node, grid connection first control
End processed；
5th PMOS transistor, source electrode connects the fourth node, and the drain electrode connection first node, grid connection is described
3rd node；
4th nmos pass transistor, the drain electrode connection fourth node, source electrode connects the input of the first order reverse circuit
End, grid connection input signal；
5th nmos pass transistor, the input of the drain electrode connection first order reverse circuit, source electrode connection second electricity
Source, grid connects second control end；
4th electric capacity a, pole of the 4th electric capacity is connected to the fourth node, and another pole connects the Section Point；
5th electric capacity a, pole of the 5th electric capacity is connected to the input of the first order reverse circuit, and another pole connects
Connect the Section Point.
Optionally, the voltage of first power end is 1.2V ~ 1.5V, and the second source end connects ground terminal, described the
The voltage of three power ends is 1.8V ~ 2.8V.
Optionally, the capacitance of the 4th electric capacity is less than the capacitance of first electric capacity, described the 5th electric capacity
Capacitance is less than the capacitance of the 4th described electric capacity.
Optionally, first order reverse circuit also includes：6th nmos pass transistor, drain electrode connection the 3rd node, source electrode
The Section Point is connected, grid connects the 3rd control end.
Accordingly, the utility model also provides a kind of word line voltage selection circuit, including：
Word line voltage generation circuit uses above-mentioned ADC dynamic logic reverse circuits, and the output end of one-level reverse circuit is led to
The input that the first phase inverter is connected to the first nor gate is crossed, the output end of adjacent next stage reverse circuit is connected to first
Another input of nor gate, the output end of first nor gate provides word line voltage, and word line voltage passes through the first gating electricity
Road is connected to the word line control voltage of memory cell；
Read operation control signal and reset operating control signal and be respectively connecting to two inputs of the second nor gate, described the
The output end of two nor gates is connected to the word line control voltage of memory cell by the second phase inverter and the second gating circuit.
Accordingly, the utility model also provides a kind of storage unit circuit, including：
7th PMOS transistor, source electrode connects the 4th power end, the power end of drain electrode connection 6T memory cell, grid connection
4th control end；
7th nmos pass transistor, the ground terminal of the drain electrode connection 6T memory cell, source electrode connects the 5th power end, and grid connects
Connect the 5th control end.
Optionally, the word line control signal of the 6T memory cell connects the word of above-mentioned word line voltage selection circuit output
Line traffic control voltage.
It is of the present utility model at least to have the advantages that relative to prior art：
1）In ADC dynamic logic reverse circuits, multistage reverse circuit is broken by the first PMOS transistor and the first power end
Open, disconnected by the first nmos pass transistor and second source end, the 4th PMOS transistor disconnects the 3rd power end, and pass through the
One electric capacity and the 4th electric capacity carry out discharge and recharge to the energizing signal in multistage reverse circuit so that circuit will not in switching process
Influence is produced on the first power end, second source end and the 3rd power end, it is to avoid influence is produced on other circuits in chip,
Improve the image quality of imaging sensor.
）In word line voltage selection circuit, the write operation of storage unit circuit and read operation or the control for resetting operation are believed
Number separate, prevent read operation and reset operation control circuit to the ADC dynamic logics for producing write operation control signal
Reverse circuit produces influence.
3）In storage unit circuit, the power end of 6T memory cell is disconnected by the 7th PMOS transistor and power end, ground
End is disconnected by the 7th nmos pass transistor so that circuit will not be produced in switching process to the 4th power end and the 5th power end
Influence.
Brief description of the drawings
Fig. 1 is the circuit diagram of ADC dynamic logic reverse circuits in the utility model first embodiment；
Fig. 2 is the SECO figure of ADC dynamic logic reverse circuits in the utility model first embodiment；
Fig. 3 is the circuit diagram of word line voltage selection circuit in the utility model second embodiment；
Fig. 4 is the schematic diagram of storage unit circuit in the utility model 3rd embodiment；
Fig. 5 is to realize the SECO figure of SRAM write and read operation in the utility model 3rd embodiment.
Embodiment
Many details are elaborated in the following description to fully understand the utility model.But this practicality is new
Type can be implemented with being much different from other manner described here, and those skilled in the art can be new without prejudice to this practicality
Similar popularization is done in the case of type intension, therefore the utility model is not limited by following public specific implementation.
Secondly, the utility model is described in detail using schematic diagram, when the utility model embodiment is described in detail, for ease of
Illustrate, the schematic diagram is example, it should not limit the scope of the utility model protection herein.
It is understandable to enable above-mentioned purpose of the present utility model, feature and advantage to become apparent, below in conjunction with accompanying drawing to this
The ADC dynamic logic reverse circuits of utility model are described in detail.
ADC dynamic logics reverse circuit of the present utility model is described below in conjunction with the accompanying drawings.
First embodiment
With reference to shown in Fig. 1, the utility model provides a kind of ADC dynamic logics reverse circuit, ADC dynamic logics upset electricity
Road includes：
First PMOS transistor P1, source electrode connects the first power end VDD, and drain electrode connection first node S1, grid is connected to
First control end int_sramb；
First nmos pass transistor N1, source electrode connection second source end VSS, drain electrode connection Section Point S2, grid is connected to
3rd node S3；
The multistage reverse circuit being sequentially connected, the multistage reverse circuit is parallel to the first node and the second section
Between point, and the output end of upper level reverse circuit is connected in the input of next stage reverse circuit, Fig. 1 and shows the first order
Reverse circuit 11 and second level reverse circuit 12, the output end OUT1 connections second level reverse circuit 12 of first order reverse circuit 11
Input；
Input circuit 13, the input circuit 13 is provided according to its input signal cmp_out to first order reverse circuit 11
Input signal；
First electric capacity C1, is connected between the first node S1 and the Section Point S2.
Specifically, with reference to shown in Fig. 1, reverse circuit described in per one-level includes：
Second PMOS transistor P2, source electrode connects the first node S1, and drain electrode connection the 3rd node S3, grid connects
It is connected to the first control end int_sramb；
Second nmos pass transistor N2, source electrode connects the Section Point S2, and drain electrode connection the 3rd node S3, grid connects
The output end of one-level reverse circuit is connected, or is connected to the input circuit；
3rd PMOS transistor P3, source electrode connects the first node S1, the input of drain electrode connection next stage reverse circuit
End, grid connects the 3rd node S3；
3rd nmos pass transistor N3, source electrode connects the Section Point S2, the input of drain electrode connection next stage reverse circuit
End, grid connects the second control end int_sram；
Wherein, the first control end int_sramb and the second control end int_sram is two signals of opposite in phase.
In addition, reverse circuit described in per one-level also includes：Second electric capacity（Not shown in figure）, second capacitance connection in
Between the 3rd node S3 and the Section Point S2, the capacitance of the first electric capacity C1 is more than the electricity of second electric capacity
Capacitance, the second electric capacity is used for the current potential for maintaining the 3rd node S3 and adjusts the RC delays on the 3rd node S3.Turned over described in per one-level
Shifting circuit also includes：3rd electric capacity（Not shown in figure）, output end and institute of the 3rd capacitance connection in this grade of reverse circuit
State between first node S1, the capacitance of the first electric capacity C1 is more than the capacitance of the 3rd electric capacity, the 3rd electric capacity is used for
Maintain the current potential of output end and adjust the delays of the RC in output end.It should be noted that due to the second described electric capacity and the 3rd
The capacitance of electric capacity is smaller, can be obtained by the parasitic capacitance in circuit layout, so without increasing this in schematic diagram
Two electric capacity.
Shown in Fig. 1, the input circuit 13 includes：
4th PMOS transistor P4, source electrode connects the 3rd power end AVDD, drain electrode connection fourth node S4, grid connection institute
State the first control end int_sramb；
5th PMOS transistor P5, source electrode connects the fourth node S4, and the drain electrode connection first node S1, grid connects
Meet the 3rd node S3；
4th electric capacity C4, the 4th electric capacity C4 pole are connected to the fourth node S4, another pole connection described the
Two node S2, the capacitance of the 4th electric capacity is less than the capacitance of first electric capacity；
4th nmos pass transistor N4, the drain electrode connection fourth node S4, source electrode connects the 5th node（First order upset electricity
The input on road 11）, grid connection input signal cmp_out, input signal cmp_out are the comparison in upper level circuit ADC
Device output signal；
5th nmos pass transistor N5, drain electrode the 5th node of connection（The input of first order reverse circuit 11）, source electrode connection
The second source end VSS, grid connects the second control end int_sram；
5th electric capacity C5 a, pole of the 5th electric capacity C5 is connected to the 5th node S5（First order reverse circuit 11
Input）, another pole connects the Section Point S2.
In the present embodiment, the output signal cmp_out high level of previous stage comparator circuit is 2.8V, first power supply
The voltage for holding VDD is 1.2V ~ 1.5V, for example, take 1.2V, the second source end VSS connections ground terminal, the 3rd power end
AVDD voltage is 1.8V ~ 2.8V, for example, take 1.8V.In order to suppress electrical leakage problems in the utility model, all metal-oxide-semiconductors are used
Thick-oxide structure.
With reference to shown in Fig. 1 and 2, the course of work of ADC dynamic logics reverse circuit of the present utility model is as follows：
First, at the t1 moment, the first control end int_sramb is low level signal, and the second control end int_sram is height
Level signal so that the first PMOS transistor P1, the second PMOS transistor P2 and the 4th PMOS transistor P4 are opened, fourth node
S4 voltage is pulled to the 3rd power end AVDD magnitude of voltage, and first node S1 and the 3rd node S3 voltage vo1 are pulled to
One power end VDD magnitude of voltage, the first nmos pass transistor N1 and the 5th nmos pass transistor N5 are opened, Section Point S2 and the 5th section
Point S5 voltage is pulled to second source end VSS voltage, third transistor N3 conductings, and output end OUT1 voltage vo2 is
VSS.Meanwhile, the PMOS transistor P2 ' conductings of second level reverse circuit, node S3 ' voltage vo3 is VDD, nmos pass transistor
N3 ' is turned on, and output end OUT2 current potential vo4 is VSS.Now, the source of the 5th PMOS transistor is 1.8V, and leakage is disconnected and grid end connects
1.2V, the rim condition being on..
Afterwards, at the t2 moment, the first control end int_sram is low level, and the second control end int_sramb is high level,
So that the first PMOS transistor P1, the 4th PMOS transistor P4, the 5th nmos pass transistor N5 are turned off, the first electric capacity C1 keeps the
Voltage between one node S1 and Section Point S2, the 4th electric capacity C4 maintains the electricity between fourth node S4 and Section Point S2
Pressure, multistage reverse circuit 11,12 is separated with the first power end VDD's and the 3rd power end AVDD.In this period, due to
Voltage on five PMOS transistor P5 weak conducting state, fourth node S4 can slowly be reduced from 1.8V, and on first node S1
Voltage correspondingly can then have been raised from 1.2V.Meanwhile, the second PMOS transistor P2 and the 3rd nmos pass transistor N3 also enter
Cut-off state.
Then, at the t3 moment, input signal cmp_out current potential is gradually risen as 2.8V so that the 4th nmos pass transistor
N4 is opened, and the voltage of the 5th node is gradually drawn high by fourth node, so that the second nmos pass transistor N2 is opened, the 3rd node
S3 pulls into VSS by Section Point S2, and the first nmos pass transistor N1 is closed, and Section Point S2 is separated with second source end VSS's
And it is maintained at VSS voltages.
3rd node S3 voltage vo1 is changed into after low level, and the 5th PMOS transistor P5 is fully on so that first node
S1 and fourth node S4 voltage are equal, stable in 1.4V or so.The 3rd PMOS transistor P3 is opened simultaneously, output end OUT1's
Voltage vo2 voltage is gradually increasing as high level, and the output end OUT1 of first order reverse circuit 11 is output into the second level
The input of reverse circuit 12（Nmos pass transistor N2 ' grid）.The second nmos pass transistor N2 ' in second level reverse circuit 12
Open, the voltage vo3 on node S3 ' is pulled to low potential, then open PMOS transistor P3 ', by output end OUT2 electricity
Draw high position so that vo4 current potential is drawn high as high potential.
In addition, the first order reverse circuit 11 in the present embodiment also includes：6th nmos pass transistor N6, drain electrode connection is described
3rd node S3, source electrode connects the Section Point S2, and grid connects the 3rd control end set.After the write operation stage terminates,
A high level pulse signal is provided in the 3rd control end set so that not yet receive cmp_out high level in the write operation stage
The circuit row of signal complete upset, are equivalent to and fill into a bright spot in the image sensor.Write operation and set operations are fully completed
Afterwards, cmp_out is changed into low level, and circuit comes back to t1 moment states.
Second embodiment
Referring to figs. 2 and 3 shown, the utility model also provides a kind of word line voltage selection circuit, including for controlling to write
The word line voltage WL of operation and two branch of control signal rst for controlling the control signal sel of read operation or reset to operate
Road, controls the gating of two branch roads, exports corresponding word line control voltage WLO, exports to storage unit circuit, so as to control to deposit
The read-write state of storage unit.In the present embodiment, memory cell carries out the word line voltage WL of write operation and believed with carrying out the sel of read operation
Number and reset operation rst signals separate, pass through write operation control signal write_n and write_d select the first gating circuit
33 and second gating circuit 34 conducting, write operation stage, word line control voltage WLO connection write operation voltage WL, non-write operation
Stage, word line control voltage WLO connection read operation control signal sel or reset operating control signal rst, so that storage is single
The process of first progress write operation and read operation or reset operation is separated, it is to avoid the circuit that read operation and reset are operated is to write operation
ADC dynamic logics reverse circuit produces influence.
Wherein, the offer of word line voltage generation circuit 20 write operation voltage WL, write operation voltage WL pass through the first gating circuit
The word line control voltage WLO of memory cell is connected to, word line voltage generation circuit 20 is using above-mentioned ADC dynamic logics upset electricity
The output end of road one-level reverse circuit is connected to an input of the first nor gate by the first phase inverter, and adjacent next stage is turned over
The output end of shifting circuit is connected to another input of the first nor gate, and the output end of first nor gate produces write operation electricity
Press WL.Specifically, referring to figs. 2 and 3 shown, the output end vo2 of first order reverse circuit 11 in word line voltage generation circuit 20
An input of the first nor gate 22, the output end vo4 connections of second level reverse circuit 12 are connected to by the first phase inverter 21
To another input of the first nor gate 22, the output end connection write operation voltage WL of first nor gate 22.In cmp_out
It is changed into after high level, is postponed by the upset between vo2 and vo4, in output end one high electricity of formation of OR-NOT circuit 22
Flat pulse signal is used as write operation signal WL.
It should be noted that tens SRAM memory cell is connected to per word line control voltage WLO all the way, so it
Load capacitance is that than larger, when write operation signal WL is changed into high level pulse, it is connected to WLO pairs by the first gating circuit
The wordline control end of tens memory cell of connection is charged, and can cause the of described ADC dynamic logic reverse circuits
One node S1 voltage is significantly dragged down.In order to prevent this pulling so that the brownout on S1 cause logic reverse circuit without
Method normal work, so just there is the 5th PMOS transistor in described ADC dynamic logic reverse circuits fully on by the 4th
Higher voltage is passed on first node S1 on node S4, the voltage on first node S1 is improved in advance, it is ensured that described ADC is moved
State logic reverse circuit keeps correct working condition in the case of voltage pull-down.This process is with reference to shown in Fig. 2.
With continued reference to shown in Fig. 3, read operation control signal sel and reset operating control signal rst are respectively connecting to second
Two inputs of nor gate 31, the output end of second nor gate 31 is connected by the second phase inverter 32 and the second gating circuit 34
It is connected to the word line control voltage WLO of memory cell.
3rd embodiment
With reference to shown in Fig. 4 and Fig. 5, the present embodiment provides a kind of storage unit circuit, including：7th PMOS transistor
P7, its source electrode connects the 4th power end VDD ', the power end of drain electrode connection 6T memory cell 40（6th node S6）, grid connection
4th control end bitcell_intb；7th nmos pass transistor N7, the ground terminal of its connection 6T memory cell 40 that drains（7th
Node S7）, source electrode the 5th power end VSS ' of connection, the 5th control end bitcell_int of grid connection.4th control end
Bitcell_intb and the 5th control end bitcell_int are a pair of opposite control signals.
Wherein, the 6T memory cell 40 includes：
8th PMOS transistor P8, the source electrode of the 8th PMOS transistor connects the 6th node S6, drain electrode connection the 8th
Node S8, grid connects the 9th node S9；
8th nmos pass transistor, the source electrode of the 8th nmos pass transistor connects the 7th node S7, Section eight of drain electrode connection
Point S8, grid connects the 9th node S9；
9th PMOS transistor P9, the source electrode of the 9th PMOS transistor connects the 6th node S6, drain electrode connection the 9th
Node S9, grid connects the 8th node S8；
9th nmos pass transistor N9, the source electrode of the 9th nmos pass transistor connects the 7th node S7, drain electrode connection the 9th
Node S9, grid connects the 8th node S8；
Tenth nmos pass transistor N10, the tenth nmos pass transistor N10 drain electrode connect the first bit line BL, source electrode connection
8th node S8, the word line control voltage WLO of grid connection word line voltage selection circuit output；
11st nmos pass transistor N11, the 11st nmos pass transistor N11 drain electrode connect the second bit line BLb, source electrode
Connect the 9th node S9, the word line control voltage WLO of grid connection word line voltage selection circuit output.
Voltage difference between the write operation stage, the 4th power end VDD ' and the 5th power end VSS ' is not necessarily to power taking
Source voltage.In the present embodiment, the 4th power end VDD ' takes 450mV, the 5th power end VSS ' to take 150mV.With reference to Fig. 4 and Fig. 5
It is shown, the 6th node S6 and the 7th node S7 be pre-charged to 450mV and 150mV, subsequent respectively in SRAM reseting stage
Seven PMOS transistor P7 disconnect the power end of memory cell 40 and the 4th power end, and the 7th nmos pass transistor N7 is by memory cell
40 ground terminal disconnects with the 5th power end.During write operation, the value of the high-low voltage by controlling BL and BLb so that the
Eight node S8 and the 9th node S9 are also maintained at change between 150mV ~ 450mV, so after the write operation is completed, the 8th node S8
Can be respectively 450mV and 150mV with the 9th node S9.After a period of time, circuit enters the read operation stage, changes the 4th control end
Bitcell_intb and the 5th control end bitcell_int voltage so that the 7th PMOS transistor P7 and the 7th NMOS crystal
Pipe N7 is turned on, and the 4th power end VDD ' is pulled to supply voltage, and the 5th power end VSS ' is put to ground voltage, although due to switch
Effect and the influence of electric leakage, the voltage difference after a period of time between the 8th node S8 and the 9th node S9 can reduce, but as long as
Ensure this voltage difference in more than 200mV, be just pulled to supply voltage, the 5th power end VSS ' in the 4th power end VDD ' enough
Put to ground voltage, the 8th node S8 and the 9th node S9 is also pulled to supply voltage and ground by 450mV and 150mV respectively
Voltage.
In summary, in the utility model, because whole write operation process is all using dynamic logic control, with power end
Disconnect, therefore other circuits will not have been impacted with ground terminal.In addition, the write operation of memory cell is also the electricity in very little
Carried out under pressure difference, this has been greatly reduced the influence that the upset inside memory cell is caused to other modules, final reading evidence
When to memory cell internal node draw high action be also to be carried out when all write operations are fully completed, deposited so also reducing
Influencing each other between storage unit.By a series of described modes, so as to improve the picture quality of imaging sensor.
Although the utility model is disclosed as above with preferred embodiment, it is not for limiting the utility model, appointing
What those skilled in the art is not being departed from spirit and scope of the present utility model, may be by the method and skill of the disclosure above
Art content makes possible variation and modification to technical solutions of the utility model, therefore, every without departing from the utility model technology
The content of scheme, according to technical spirit of the present utility model above example is made it is any it is simple modification, equivalent variations and
Modification, belongs to the protection domain of technical solutions of the utility model.
Claims (9)
1. a kind of ADC dynamic logics reverse circuit, it is characterised in that including：
First PMOS transistor, source electrode connects the first power end, and drain electrode connection first node, grid is connected to the first control end；
First nmos pass transistor, source electrode connection second source end, drain electrode connection Section Point, grid is connected to the 3rd node；
The multistage reverse circuit being sequentially connected, the multistage reverse circuit be parallel to the first node and the Section Point it
Between, and the output end of upper level reverse circuit is connected to the input of next stage reverse circuit；
Input circuit, the input circuit is used to provide input signal to first order reverse circuit；
First electric capacity, is connected between the first node and the Section Point.
2. ADC dynamic logics reverse circuit according to claim 1, it is characterised in that reverse circuit bag described in per one-level
Include：
Second PMOS transistor, source electrode connects the first node, drain electrode connection the 3rd node, and grid is connected to described the
One control end；
Second nmos pass transistor, source electrode connects the Section Point, and drain electrode connection the 3rd node, grid connects the input
The output end of circuit or the output end of upper level reverse circuit；
3rd PMOS transistor, source electrode connects the first node, and the input of drain electrode connection next stage reverse circuit, grid connects
Connect the 3rd node；
3rd nmos pass transistor, source electrode connects the Section Point, and the input of drain electrode connection next stage reverse circuit, grid connects
Connect the second control end.
3. ADC dynamic logics reverse circuit according to claim 1 or 2, it is characterised in that the input circuit includes：
4th PMOS transistor, source electrode connects the 3rd power end, drain electrode connection fourth node, grid connection first control
End；
5th PMOS transistor, source electrode connects the fourth node, the drain electrode connection first node, grid connection the described 3rd
Node；
4th nmos pass transistor, the drain electrode connection fourth node, source electrode connects the input of the first order reverse circuit, grid
Pole connects input signal；
5th nmos pass transistor, the input of the drain electrode connection first order reverse circuit, source electrode connects the second source end,
Grid connects second control end；
4th electric capacity a, pole of the 4th electric capacity is connected to the fourth node, and another pole connects the Section Point；
5th electric capacity a, pole of the 5th electric capacity is connected to the input of the first order reverse circuit, and another pole connects institute
State Section Point.
4. ADC dynamic logics reverse circuit according to claim 3, it is characterised in that the voltage of first power end
For 1.2V ~ 1.5V, the second source end connects ground terminal, and the voltage of the 3rd power end is 1.8V ~ 2.8V.
5. ADC dynamic logics reverse circuit according to claim 3, it is characterised in that the capacitance of the 4th electric capacity
Less than the capacitance of first electric capacity, the capacitance of the 5th described electric capacity is less than the capacitance of the 4th described electric capacity.
6. ADC dynamic logics reverse circuit according to claim 2, it is characterised in that first order reverse circuit also includes：
6th nmos pass transistor, drain electrode connection the 3rd node, source electrode connects the Section Point, and grid connects the 3rd control end.
7. a kind of word line voltage selection circuit, it is characterised in that including：
Word line voltage generation circuit use ADC dynamic logics reverse circuit as claimed in claim 1, one-level reverse circuit it is defeated
Go out the input that end is connected to the first nor gate by the first phase inverter, the output end of adjacent next stage reverse circuit is connected
To another input of the first nor gate, the output end of first nor gate provides word line voltage, and word line voltage passes through first
Gating circuit is connected to the word line control voltage of memory cell；
Read operation control signal and reset operating control signal and be respectively connecting to two inputs of the second nor gate, described second or
The output end of NOT gate is connected to the word line control voltage of memory cell by the second phase inverter and the second gating circuit.
8. a kind of storage unit circuit, it is characterised in that including：
7th PMOS transistor, source electrode connects the 4th power end, the power end of drain electrode connection 6T memory cell, grid connection the 4th
Control end；
7th nmos pass transistor, the ground terminal of the drain electrode connection 6T memory cell, source electrode connects the 5th power end, grid connection the
Five control ends.
9. storage unit circuit according to claim 8, it is characterised in that the word line control signal of the 6T memory cell
Connect the word line control voltage of word line voltage selection circuit output as claimed in claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621479337.6U CN206461708U (en) | 2016-12-30 | 2016-12-30 | ADC dynamic logics reverse circuit, word line voltage selection circuit and storage unit circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621479337.6U CN206461708U (en) | 2016-12-30 | 2016-12-30 | ADC dynamic logics reverse circuit, word line voltage selection circuit and storage unit circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106657834A (en) * | 2016-12-30 | 2017-05-10 | 格科微电子（上海）有限公司 | ADC dynamic logic overturning circuit, word line voltage selection circuit and storage unit circuit |
| TWI704759B (en) * | 2019-04-11 | 2020-09-11 | 力旺電子股份有限公司 | Power switch circuit |
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2016
- 2016-12-30 CN CN201621479337.6U patent/CN206461708U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106657834A (en) * | 2016-12-30 | 2017-05-10 | 格科微电子（上海）有限公司 | ADC dynamic logic overturning circuit, word line voltage selection circuit and storage unit circuit |
| TWI704759B (en) * | 2019-04-11 | 2020-09-11 | 力旺電子股份有限公司 | Power switch circuit |
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