CN206460951U - A kind of chip-packaging structure - Google Patents
A kind of chip-packaging structure Download PDFInfo
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- CN206460951U CN206460951U CN201621111985.6U CN201621111985U CN206460951U CN 206460951 U CN206460951 U CN 206460951U CN 201621111985 U CN201621111985 U CN 201621111985U CN 206460951 U CN206460951 U CN 206460951U
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 69
- 238000001746 injection moulding Methods 0.000 claims description 8
- 239000004606 Fillers/Extenders Substances 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 239000012778 molding material Substances 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 abstract description 11
- 230000004069 differentiation Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 22
- 238000010586 diagram Methods 0.000 description 12
- 239000003365 glass fiber Substances 0.000 description 5
- 238000005498 polishing Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000007781 pre-processing Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
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- Packaging Frangible Articles (AREA)
Abstract
A kind of chip-packaging structure, including：An at least chip is included in an at least packaging body, each packaging body, and is wrapped in packaging body and the expansion body that can be cut according to package dimension demand.The utility model solves small-size chips encapsulation and the conflict of other sizes chip package, meets the demand of product differentiation.
Description
Technical Field
The utility model belongs to the technical field of the IC design, especially, relate to a chip package structure.
Background
Chip packaging is a technique for packaging integrated circuits with an insulating plastic or ceramic material. Taking a CPU as an example, the volume and appearance actually seen are not the size and appearance of a real CPU core, but are the products of packaged components such as the CPU core. Chip packaging is essential and critical to the chip. Because the chip must be isolated from the outside to prevent the electrical performance degradation caused by the corrosion of the chip circuit by impurities in the air. On the other hand, the packaged chip is more convenient to mount and transport. The quality of the packaging technology is also of great importance since it directly affects the performance of the chip itself and the design and manufacture of the PCB (printed circuit board) to which it is connected.
With the development of technology and market, small-sized Sensor (Sensor) chips are becoming mainstream because of their best balance among volume, safety, and cost. However, when designing the device, there is a specific requirement for aesthetic sense, touch feeling, etc. The sensor chip of a specific size is in conflict with the development of a small-sized sensor chip, and the increase in the size of the sensor chip causes an increase in cost. Also, the various size requirements of the Sensor (Sensor) chip lead to compatibility difficulties.
SUMMERY OF THE UTILITY MODEL
The utility model provides a chip packaging structure, it can realize the changeable chip package of size.
An embodiment of the utility model provides a chip packaging structure, include: at least one packaging body, wherein each packaging body comprises at least one chip; and an extension body which wraps the packaging body and can be cut according to the packaging size requirement.
Another embodiment of the present invention provides a chip packaging method, including:
fixing at least one packaging body on the surface of a lower die through a carrier plate, and sealing an upper die on the packaging body;
filling a cavity between the carrier plate and the upper die with an expansion body through injection molding, wherein the expansion body wraps the at least one packaging body;
and demolding to obtain the package body with the expanded size, and cutting the package body according to the package size requirement.
From the foregoing, the embodiment of the present invention provides an at least one package body is wrapped up by the extension body, the extension body can cut according to the encapsulation size demand. Therefore, the extension body can be cut according to the required packaging size to obtain the packaging chip with a specific size. The utility model provides a conflict of small-size chip package and other size chip package, satisfied the demand of product differentiation.
Drawings
In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIGS. 1A and 1B are schematic diagrams of some embodiments of the packaged chip of the present invention;
fig. 2A to 2F are flow charts of some embodiments of the packaging method for packaging chips according to the present invention;
FIG. 3 is a schematic diagram of a carrier board in the method for packaging a packaged chip according to the present invention;
FIG. 4 is a schematic diagram of a package body being fixed by a carrier plate according to the packaging method of the present invention;
FIG. 5 is a schematic view of the upper film of the packaging method for packaging chips according to the present invention;
FIG. 6 is a schematic diagram of an extender filled in the packaging method for packaging a chip according to the present invention;
FIG. 7 is a schematic diagram of a packaged chip obtained after demolding in the packaging method of the packaged chip of the present invention;
FIGS. 8A and 8B are schematic diagrams of the upper surface of the extended body and the upper surface of the IC package body, which are not flush with each other, according to the method for packaging the packaged chip of the present invention;
FIG. 9 is a schematic diagram of the upper surface of the extended body and the upper surface of the package body after the upper surface is ground in the method for packaging the chip of the present invention
FIGS. 10A and 10B are flow charts of other embodiments of the present invention for a method of packaging a packaged chip;
FIG. 11 is a schematic view of a strip-shaped glass fiber in the method for packaging a chip according to the present invention;
FIG. 12 is a schematic diagram of a local area hollow frame formed by preprocessing in the packaging method of the packaged chip according to the present invention;
FIG. 13 is a schematic diagram of the package body being placed in the hollow area of the hollow glass fiber frame according to the method for packaging a chip of the present invention;
fig. 14 is a schematic diagram of a secondary package obtained by curing in the packaging method for packaging a chip according to the present invention;
FIG. 15 is a schematic diagram of the upper surface of the extended body and the upper surface of the IC package body with uneven upper surfaces according to the method for packaging the chip of the present invention;
fig. 16 is a schematic diagram of the upper surface of the extension and the upper surface of the IC package after polishing the upper surface in the method for packaging the chip according to the present invention.
Detailed Description
The utility model discloses an at least encapsulation body is by extending the body parcel, it can cut according to encapsulation size demand to extend the body. Therefore, the extension body can be cut according to the required packaging size to obtain the packaging chip with a specific size. The utility model provides a conflict of small-size chip package and other size chip package, satisfied the demand of product differentiation.
Referring to fig. 1A and 1B, the utility model provides a chip packaging structure, include: each package body 1 comprises at least one chip 11 and an extension body 2 wrapping the package body 1 and capable of being cut according to the package size requirement.
Therefore, the utility model discloses can be as required the encapsulation size, the cutting expand the body, obtain specific size's encapsulation chip. The utility model provides a conflict of small-size chip package and other size chip package, satisfied the demand of product differentiation.
In a specific embodiment of the present invention, the extension body 2 wraps the four sides of the package body 1, so that the extension body 2 wraps the package body 1.
In another specific implementation of the present invention, the extension 2 is not lower than the upper surface of the package 1.
Specifically, the extension 2 is flush with the upper surface of the package 1.
The package body 1 and the upper surface of the extension body 2 are kept flush by grinding, so that the surface flatness is kept, and the distance from the surface of a packaged bare chip (Die) to the surface of an IC (integrated circuit) can be controlled.
In another specific implementation of the present invention, the extension body 2 is wrapped in the package body 1, and the extension body 2 is made of an injection molding material or a frame filling material.
In another specific embodiment of the present invention, the thermal expansion coefficient of the extension body 2 is consistent with the thermal expansion coefficient between the plastic package body, the lead frame, the substrate, and the chip silicon material of the package body 1, thereby preventing the package chip from being unusable due to the difference of the thermal expansion coefficients.
In another embodiment of the present invention, the surface of the packaged chip after the extension 2 is packaged has an adhesion portion for increasing the adhesion force between the chip and the circuit board. The adhesion part is specifically for planting the tin ball, does false pad (dummy pad) etc. and increases the utility model discloses the adhesion force between the encapsulation chip after the extension body 2 encapsulates and the circuit board.
The utility model discloses in another concrete realization, the colour of extension body 2 does benefit to post processing's colour for grey etc. and specific colour can be customized according to actual demand.
In yet another embodiment of the present invention, discrete components and/or conductive via modules are provided in the extender 2. The discrete component and/or the conductive via module are/is placed around the package body 1, then the extension body 2 is filled, and the package body 1 and the discrete component are wrapped by the extension body 2.
The utility model discloses in another concrete realization, utilize before extension body 2 encapsulates, surface pad pasting or water spray water solubility are glued under the encapsulation body 1 to prevent that excessive glue from polluting, influence the rear end laminating.
In yet another embodiment of the present invention, the upper surface of the package body 2 includes a cover plate. The cover plate is made of glass, ceramic, sapphire and the like, so that the cover plate and the packaging body 1 are subjected to plastic package and molding by the extension body 2.
In yet another embodiment of the present invention, the package 1 is one of a quad flat non-leaded package, a grid array package, and a wafer level package.
Referring to fig. 2A, a specific implementation of the chip packaging method of the present invention includes:
s1, fixing at least one package on the surface of the lower die through the carrier plate, and sealing the upper die for the package.
A flat plate, which can be used as a support, is prepared as the carrier plate 3, as shown in fig. 3. The package 1 is fixed by the carrier 3, as shown in fig. 4. And sealing an upper mold 4 to the package 1 on the carrier 3, as shown in fig. 5.
And S2, filling the cavity between the carrier plate and the upper die with an expansion body by injection molding, wherein the expansion body wraps the at least one packaging body.
Specifically, the extension 2 is filled around the package 1 by injection molding, and the package 1 is wrapped, as shown in fig. 6.
And S3, demolding the obtained package body with the expanded size, and cutting the package body according to the package size requirement.
And demolding to obtain the packaged chip with the expanded size, as shown in fig. 7.
In a specific implementation of the present invention, referring to fig. 2B, the method further comprises: and S4, grinding the package body after the size expansion to enable the upper surfaces of the package body and the expansion to be flush.
Fig. 8 shows the top surface of the extension 2 and the top surface of the IC package 1, which have non-flush top surfaces, and fig. 9 shows the top surface of the extension 2 and the top surface of the package 1 after polishing.
The upper surface of the extension body 2 and the upper surface of the IC package 1 are arranged on a plane by grinding, so that the surface flatness is kept, and the distance from the surface of a packaged bare chip (Die) to the surface of the IC can be controlled.
In another specific implementation of the present invention, step S2 specifically includes:
filling a cavity between the carrier plate and the upper die with an expansion body through injection molding, wherein the expansion body wraps a packaging body; or,
and filling the cavity between the carrier plate and the upper die with the expansion body through full-page injection molding, wherein the expansion body wraps a plurality of packaging bodies at one time.
The utility model discloses can pack to single packaging body 1 and expand body 2, the encapsulation size of direct forming for needs. The utility model discloses also can pack to a plurality of packaging bodies 1 and expand body 2, cut a plurality of packaging bodies 1 after expanding again, obtain the single packaging body 1 that accords with the encapsulation size.
The expansion bodies 2 are filled in the plurality of spliced packaging bodies 1 and then cut into single packaging bodies 1, so that the packaging efficiency is improved.
The expansion body 2 is made of a whole-plate injection molding material, so that a large plate used by the expansion body 2 can be prevented from warping.
In particular, the extension 2 is an injection molded material.
In another embodiment of the present invention, referring to fig. 2C, the step S1 further includes:
and S0, attaching the cover plate to the upper surface of the packaging body.
The cover plate is made of glass, ceramic, sapphire and the like, so that the cover plate and the packaging body 1 are subjected to plastic package and molding by the extension body 2.
In another embodiment of the present invention, referring to fig. 2D, the step S3 is followed by: and S5, adding an adhesion part for increasing the adhesion force between the surface of the packaged chip and the circuit main board.
The adhesion part is specifically for planting the tin ball, does false pad (dummy pad) etc. and increases the utility model discloses the adhesion force between the encapsulation chip after the extension body 2 encapsulates and the circuit board.
In another embodiment of the present invention, referring to fig. 2E, the step S2 further includes:
s22, discrete components and/or conductive through hole modules are arranged in the cavities.
In another embodiment of the present invention, referring to fig. 2F, the step S1 further includes:
and S11, pad pasting or spraying water-soluble glue on the lower surface of the packaging body.
Therefore, the glue overflow pollution is prevented, and the rear end bonding is prevented from being influenced.
Referring to fig. 10A, another specific implementation of the chip packaging method includes:
t1, preprocessing to form a hollow frame with a hollow area, and placing the hollow frame on the surface of a lower die.
Specifically, a strip-shaped glass fiber is preprocessed to form a frame 5 with a hollow part. Specifically, the strip-shaped glass fiber is preprocessed to form a frame with a hollow part in a local area as shown in fig. 11, and is preprocessed to form a frame with a hollow part in a local area as shown in fig. 12.
And T2, respectively placing at least one packaging body in each hollow area of the hollow frame, and filling the expansion body in the gap between the packaging body and the hollow frame where the packaging body is located, so that the expansion body wraps the packaging body.
Specifically, the package 1 is disposed in the hollow area of the glass fiber hollow frame 5, as shown in fig. 13. The gap between the package 1 and the hollow frame 5 where the extension 2 is filled is specifically the gap between the package 1 and the hollow frame 5 where the extension 2 is suspended.
And T3, curing the obtained package body with the expanded size, and cutting the package body according to the package size requirement.
As shown in fig. 14, the package body after being cured and expanded in size can be freely cut according to the package size requirement, so as to obtain a secondary package body with a specific size.
In another embodiment of the present invention, referring to fig. 10B, the method further comprises:
and T4, grinding the package body after the expansion size is finished, so that the upper surfaces of the expansion body and the package body are flush.
If the upper surface of the extension 2 is not flush with the upper surface of the package 1, the upper surface is polished to be flush.
Fig. 15 shows the top surface of the extension 2 and the top surface of the IC package 1, which have non-flush top surfaces, and fig. 16 shows the top surface of the extension 2 and the top surface of the IC package 1 after polishing.
The upper surface of the extension body 2 and the upper surface of the IC package 1 are arranged on a plane by grinding, so that the surface flatness is kept, and the distance from the surface of a packaged bare chip (Die) to the surface of the IC can be controlled.
It should be noted that, for the sake of simplicity, the above-mentioned embodiments of the method are described as a series of combinations of actions, but it should be understood by those skilled in the art that the present invention is not limited by the described order of actions, because some steps can be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
Above is to the description of the chip package structure that the present invention provides, to the technical personnel in the field, according to the utility model discloses the thought of embodiment all has the change part on concrete implementation and application scope, to sum up, this description content should not be understood as the restriction of the present invention.
Claims (11)
1. A chip package structure, comprising: the packaging structure comprises at least one packaging body, a chip and a chip, wherein each packaging body comprises at least one chip; and the extension body wraps the packaging body and can be cut according to the packaging size requirement, and the extension body wraps four side surfaces of the packaging body.
2. The chip package structure according to claim 1, wherein the extension is not lower than an upper surface of the package body.
3. The chip package structure according to claim 2, wherein the extension is flush with an upper surface of the package body.
4. The chip package structure according to any one of claims 1 to 3, wherein the extension body is an injection molding material or a frame filling material.
5. The chip package structure according to claim 4, wherein the thermal expansion coefficient of the extension body is consistent with the thermal expansion coefficients of the plastic package body, the lead frame, the substrate and the chip silicon material of the package body.
6. The chip package structure according to claim 1, wherein the surface of the chip package structure has an adhesion portion for increasing adhesion with a circuit board.
7. The chip package structure according to claim 1, wherein the extender is an extender requiring a customized color.
8. The chip package structure according to claim 1, wherein the extension body has discrete components and/or conductive via modules.
9. The chip package structure according to claim 1, wherein the lower surface of the package body has a pad pasting film or is sprayed with a water-soluble glue.
10. The chip package structure according to claim 1, wherein the package upper surface comprises a cover plate.
11. The chip package structure according to any one of claims 1-3 and 5-10, wherein the package body is one of a quad flat non-leaded package, a grid array package, and a wafer level package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621111985.6U CN206460951U (en) | 2016-10-10 | 2016-10-10 | A kind of chip-packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621111985.6U CN206460951U (en) | 2016-10-10 | 2016-10-10 | A kind of chip-packaging structure |
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| CN206460951U true CN206460951U (en) | 2017-09-01 |
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| CN201621111985.6U Expired - Fee Related CN206460951U (en) | 2016-10-10 | 2016-10-10 | A kind of chip-packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110517963A (en) * | 2019-09-05 | 2019-11-29 | 合肥矽迈微电子科技有限公司 | A kind of ring membrane structure Shooting Technique |
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2016
- 2016-10-10 CN CN201621111985.6U patent/CN206460951U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110517963A (en) * | 2019-09-05 | 2019-11-29 | 合肥矽迈微电子科技有限公司 | A kind of ring membrane structure Shooting Technique |
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170901 |