CN206432038U - A kind of DRAM hammers pressure circuit for detecting - Google Patents
A kind of DRAM hammers pressure circuit for detecting Download PDFInfo
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- CN206432038U CN206432038U CN201720018353.3U CN201720018353U CN206432038U CN 206432038 U CN206432038 U CN 206432038U CN 201720018353 U CN201720018353 U CN 201720018353U CN 206432038 U CN206432038 U CN 206432038U
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Abstract
A kind of DRAM of the utility model hammers pressure circuit for detecting there is provided can physics realization detecting scheme, circuit structure is simple, and the design cost of actual circuit is low, it is ensured that the reliability of DRAM data storage.It includes, serial shift registers chain, for shifting the row address A_i for latching the instruction of dram chip excited inside；OPADD latch, is connected to serial shift registers chain end, for latching the row address A_o that output is pressed onto by hammer；Match logic circuitry, input is connected with OPADD latch and per one-level shift register output respectively, and carrying out matching with the row address of OPADD latch for the output row address of serial shift registers chain is compared；Detect logic circuit, the output connection of input and match logic circuitry；Logic circuit output detection signal is detected, while output feedback signal control shift register and OPADD latch.
Description
Technical field
The utility model is related to a kind of DRAM circuit for detecting, specially a kind of DRAM hammers pressure circuit for detecting.
Background technology
DRAM (Dynamic Random Access Memory, dynamic random access memory) is most widely used
System memory element.For higher integrated level and less expensive manufacturing cost, DRAM manufacturing process characteristic sizes
(Feature Size) persistently reduces.However, the device size persistently reduced can cause in DRAM memory cell physical arrangement more
Plus close, this crosstalk (Coupling) that can increase consecutive storage unit and charge leakage (Leakage), so as to cause to store number
According to integrity problem.
Hammer pressure (Hammer Stress) is to carry out frequently multiple activation to a certain particular memory location in DRAM internal memories
(Active) operate, so as to aggravate crosstalk and the charge leakage of consecutive storage unit, the mistake of data storage can be caused when serious,
And integrity problem more serious along with process diminution this exactly DRAM.Therefore, by increasing hammer in the chips
Circuit for detecting is pressed to ensure the reliability of DRAM data storage.
Utility model content
For problems of the prior art, the utility model provides a kind of DRAM hammers pressure circuit for detecting, and there is provided can thing
The detecting scheme realized is managed, circuit structure is simple, and the design cost of actual circuit is low, it is ensured that the reliability of DRAM data storage.
The utility model is to be achieved through the following technical solutions：
A kind of DRAM hammers pressure circuit for detecting, including,
Serial shift registers chain, for shifting the row address A_i for latching the instruction of dram chip excited inside；
OPADD latch, is connected to serial shift registers chain end, for latching the row ground that output is pressed onto by hammer
Location A_o；
Match logic circuitry, input is connected with OPADD latch and per one-level shift register output respectively, is used
Matching is carried out in the output row address of serial shift registers chain with the row address of OPADD latch to be compared；
Detect logic circuit, the output connection of input and match logic circuitry；Logic circuit output detection signal is detected,
Output feedback signal controls shift register and OPADD latch simultaneously.
It is preferred that, described detecting logic circuit includes,
Detecting logic circuit input and clock signal are connected with the input of the first d type flip flop clock；First d type flip flop
The input that output end is connected as the first d type flip flop with the first phase inverter, the output end of the first d type flip flop simultaneously with multi input or
The input of NOT gate is connected；
The output end of multi input nor gate is as two inputs and an input of door, the output end of two inputs and door and the
The clock input of 2-D trigger is connected, and the output of the second d type flip flop is anti-by second as the output end for detecting logic circuit
The output freeze of phase device is connected with the reset terminal of serial shift registers chain；Detect the reset signal Reset_i of logic circuit
It is connected with the reset terminal of the second d type flip flop；
Two inputs are connected with another input of door with the output of 3d flip-flop, the input clock of 3d flip-flop
It is connected with the output end for detecting logic circuit；The output of 3d flip-flop is connected with the set end of the first d type flip flop, while
It is used as the feedback signal terminal of detecting logic circuit output.
Further, the feedback signal terminal of detecting logic circuit output is connected to the control end of a MUX, as
Control the feedback signal of shift register and OPADD latch.
It is preferred that, described match logic circuitry includes multiple XOR gates, the output end connection multi input of XOR gate with or
Door, multi input exports comparative result with the output end of OR gate；
The output of XOR gate connects the output row address of serial shift registers chain and the row of OPADD latch respectively
Corresponding address signal on address.
It is preferred that, serial shift registers chain, OPADD latch and detecting logic circuit share DRAM clock
Signal.
Compared with prior art, the utility model has following beneficial technique effect：
The utility model is stored one by one by the serial shift registers chain of setting to the row address of activation instruction, from
And can be using match logic circuitry to the row address in OPADD latch and the row in above serial shift registers chain
Address carries out matching contrast, and the row address of activation instruction is judged one by one in detecting logic circuit realization, and is patrolled using detecting
Volume circuit carries out feedback control to serial shift registers chain and OPADD latch, so as to hammer pressure is realized detecting and
Output.
Brief description of the drawings
Fig. 1 is the structural principle block diagram of circuit for detecting described in the utility model example.
Fig. 2 is the detecting scheme schematic diagram described in the utility model example.
Fig. 3 is the detection circuit structure schematic diagram described in the utility model example.
Fig. 4 is match logic circuitry schematic diagram in circuit for detecting described in the utility model example.
Fig. 5 is to detect logic circuit schematic diagram in circuit for detecting described in the utility model example.
Embodiment
The utility model is described in further detail with reference to specific embodiment, described is to the utility model
Explanation rather than restriction.
A kind of DRAM hammers pressure circuit for detecting of the present utility model, including：Serial shift registers chain, shift register last-in-chain(LIC)
Hold the OPADD latch of connection；OPADD latch and every one-level shift register output are used as match logic circuitry
Input, the output of match logic circuitry is connected with detecting logic module, while controlling serial shift registers and OPADD lock
Storage.
A kind of DRAM hammers pressure circuit for detecting of the utility model is when being judged, when the access of a row address has following spy
When levying, it is possible to judge that DRAM has hammer pressure risk：
In n+1 continuous activation instructions, some specific row address is repeatedly accessed, and access times are less than n；
The row address is ensuing 2n2 are had more than in secondary activation instructionn/ n access record above；And the row
Location is between adjacent activation instruction twice, and other address access times are no more than n-1 times.
According to specifically, as shown in figure 1, the DRAM hammer pressure circuit for detecting 100 described in the utility model embodiment includes：
It is used for shifting (the Serial of serial shift registers chain 110 for the row address A_i 10 for latching activation instruction inside dram chip
Shift Register, SSR)；(the Output of OPADD latch 120 being connected with serial shift registers 110
Address Latch, OAL) it is used for latching the row address A_o 20 that output is detected by hammer pressure；Serial shift registers 100 with
The co-used chip internal clock signal ACT_i 40 of OPADD latch 120；Match logic circuitry 130 (Match Logic, ML)
Row address is exported as serial shift registers 110 with the progress matching of the row address of OPADD latch 120 to be compared, and will be compared
As a result be output to detecting logic circuit 140 (Detect Logic, DL) be used for differentiate the address with the presence or absence of hammer pressure risk and will
Result of determination is output as detection signal Detect_o 30.When not detecting risk, detecting logic circuit 140 passes through feedback
Signal 60 controls serial shift registers 110 and OPADD latch 120 to proceed next round detecting, and passes through Reset_
I 50 resets detecting logic circuit 140；When detecting risk, detecting logic circuit 140 can be by feedback signal 60 to control
Serial shift registers 110 and OPADD latch 120 are carried out resetting operation and lock the address, and whole circuit can be held again
Beginning work.
A kind of DRAM hammers of the utility model press circuit for detecting when carrying out hammer pressure detecting, comprise the following steps,
Step 1, in n+1 continuous activation instructions, referred to by the first activation therein of OPADD latches
The row address accessed is made, the row address that nearest n activation instruction is accessed is latched by serial shift registers chain successively；
Step 2, the nearest n activation instruction latched successively to serial shift chain of latches by match logic circuitry is accessed
The row addresses of row address and OPADD latches carry out matching and compared, and export comparative result；OPADD is latched
The row address that device is latched is used as the row address that there may be hammer pressure mistake；
Step 3, detecting logic circuit carries out following Statistic analysis according to the comparative result of output；
3.1 in n+1 continuous activation instructions, are if possible repeatedly accessed in the presence of the row address of hammer pressure mistake, and
Access times are less than n, then carry out 4.2 judgement；Otherwise repeat step 1；
3.2 if possible have the row address of hammer pressure mistake ensuing 2n2 are had more than in secondary activation instructionn/ n times with
On access record；And the row address of hammer pressure mistake is there may be between adjacent activation instruction twice, and other addresses are visited
Ask that number of times is no more than n-1 times, then send detection signal Detect_o, provide a high level；Otherwise a low level is provided；
Detecting logic circuit sends detection signal Detect_o, is simultaneously emitted by a feedback signal hold, and pass through
Reset_i resets detecting logic circuit；
Step 4, OPADD latch is received after the high level that detection signal Detect_o is provided, and OPADD is latched
Device locks current row address and exported；The serial shift registers of feedback signal control simultaneously reset, and control OPADD latch
Resetted after output, repeat step 1；
OPADD latch is received after the low level that detection signal Detect_o is provided, the input of OPADD latch
End is open to shift register, the row address to store (n+1)th activation；The serial shift registers of feedback signal control simultaneously
Proceed next round detecting, repeat step 1 with OPADD latch.
In order to further illustrate the course of work of hammer pressure circuit for detecting, circuit for detecting embodiment during n=8 is selected to carry out
Illustrate.I.e. in 9 continuous activation instructions, some row address is repeatedly accessed；The row address is ensuing 256
The access record of more than 32 times is had more than in secondary activation instruction；Between two adjacent activation instructions of the row address, be up to not
More than more than 7 other addresses are accessed.It now can be determined that the row address has hammer pressure risk.The course of work of circuit for detecting can
To be illustrated with reference to detecting scheme schematic diagram 2, when Reset_i is high level, circuit is started working.Circuit for detecting can be most
Record the row address that nearest 9 activation instructions are accessed more, be compared and judged by match logic circuitry, if row
Location is repeatedly accessed in defined access times, is accessed, and is met in following 256 activation instructions and have more than for such as 4 times
More than 32 times accessed records, and the row address is be up to no more than 7 with Shangdi between two adjacent activation instructions
Location is accessed, then a high level can be provided by now detecting the detection signal Detect_o of logic circuit output, that is, warn DRAM
It is current to have hammer pressure risk, while providing the row address being detected on output A_o ends.When Detect_o is resetted by Reset_i
Afterwards, circuit can restart work again.
For the above-mentioned circuit for detecting course of work, it is possible to achieve detection circuit structure schematic diagram as shown in Figure 3.Its
In, shift register (SR0~SR7) is composed in series the serial shift registers chain that one group of long degree is 8, for shifting latch successively
The row address that nearest 8 activation instructions are accessed；The end of shift register is connected with OPADD latch (OAL), to possible
Latch output is carried out in the presence of the row address of hammer pressure risk；Match logic circuitry (ML0~ML7) is by comparing serial shift latch
The row address that nearest 8 activation instructions that chain is latched are accessed and the row that there may be hammer pressure risk of OPADD latches
Address carries out matching comparison, and comparative result is output into detecting logic circuit (DL)；Detecting logic circuit compared result is pressed
Differentiated according to above-mentioned detecting deterministic process, according to judged result serial shift can be controlled to deposit while detecting logic circuit
The working condition of device chain and OPADD latch.When detecting logic circuit does not detect the row address in the presence of hammer pressure risk
When, the feedback signal hold of detecting logic circuit is low level, and the OPADD latch inputs opening of end is posted to displacement
Storage, to store the row address that the 9th activation instruction is accessed；When detecting logic circuit detects the row address of hammer pressure risk
When, the feedback signal hold of detecting logic circuit is high level, and the OPADD latch lockout current address of end is simultaneously exported.
Here detecting logic circuit can pass through config_i<1:0>Configured to determine in n+1 continuous activation instruction, it is specific
The accessed number of times in address, the tolerance intensity of risk is pressed to distinguish the circuit for hammer.
Match logic circuitry realizes schematic diagram with reference to shown in Fig. 4 in hammer pressure circuit for detecting, and match logic circuitry is responsible for judgement
Whether the value on two address bus is similar.The logic circuit can both enter the accurate matching of row address, can also enter row address
Fuzzy matching.The utility model according to DRAM array structure, selection high address A13, B13, A12, B12, A11, B11 with it is low
Bit address A2, B2, A1, B1, A0, B0 carry out fuzzy matching.Its purpose of design is more simple Logic Circuit Design, simultaneously
Due to can be determined that partial address is similar, it has been enough to illustrate that current row address is geographically separated by not far.Wherein, it is high
Bit address A13, B13, A12, B12, A11, B11 and low order address A2, B2, A1, B1, A0, B0 combination of two are used as six XORs
The input of door, and the output of six XOR gates is connected to the nor gate of one six input, its output is exactly match logic circuitry ratio
Compared with result.
Detecting logic circuit in hammer pressure circuit for detecting realizes structural representation with reference to shown in Fig. 5, and detecting logic circuit is used
The detecting of risk is pressed to judge hammer to realize in detecting scheme：I.e. in 9 continuous activation instructions, some row address is multiple
Access, for example, access 4,5 or 6 times can be configurable by config_i；The row address has in following 256 activation instructions
Record is accessed more than more than 32 times；Between the adjacent activation instruction twice of the row address, be up to no more than more than 7 other rows
Location is accessed.When judging that the row address has hammer pressure risk, exported by detect and detecting logic electricity is resetted by Reset_i
Road, detects logic circuit and also needs to serial shift register and the progress of OPADD latch after judging the address
Reset operation and arrange next time new address input.These operations are completed by hold signals and freeze signals.
Wherein, detecting logic circuit input and clock signal Clk are connected with the input of the first d type flip flop clock；First D
The input that the output end of trigger is connected as the first d type flip flop with the first phase inverter, the output end of the first d type flip flop simultaneously with
The input of multi input nor gate is connected；The output end of multi input nor gate is as two inputs and an input of door, and two is defeated
Enter and be connected with the output end of door with the clock input of the second d type flip flop, the output of the second d type flip flop is used as detecting logic circuit
Output end detect, is connected by the output freeze of the second phase inverter with the RS ends of serial shift registers chain；Detect logic
The reset signal Reset_i inputs of circuit are connected with the R ends of the second d type flip flop；Two inputs and another input of door and the
The output of 3d flip-flop is connected, and the input clock of 3d flip-flop is connected with detecting the output end detect of logic circuit；The
The output of 3d flip-flop is connected with the S ends of the first d type flip flop, while also serving as detecting the hold signal ends of logic circuit output.
Claims (5)
1. a kind of DRAM hammers pressure circuit for detecting, it is characterised in that including,
Serial shift registers chain, for shifting the row address A_i for latching the instruction of dram chip excited inside；
OPADD latch, is connected to serial shift registers chain end, for latching the row address A_ that output is pressed onto by hammer
o；
Match logic circuitry, input is connected with OPADD latch and per one-level shift register output respectively, for going here and there
Join the output row address of shift register chain with the row address progress matching of OPADD latch to be compared；
Detect logic circuit, the output connection of input and match logic circuitry；Logic circuit output detection signal is detected, simultaneously
Output feedback signal controls shift register and OPADD latch.
2. a kind of DRAM hammers pressure circuit for detecting according to claim 1, it is characterised in that described detecting logic circuit bag
Include,
Detecting logic circuit input and clock signal are connected with the input of the first d type flip flop clock；The output of first d type flip flop
Hold the input that is connected with the first phase inverter as the first d type flip flop, the output end of the first d type flip flop and meanwhile with multi input nor gate
Input be connected；
The output end of multi input nor gate is as two inputs and an input of door, and two input the output end and the 2nd D with door
The clock input of trigger is connected, and the output of the second d type flip flop is as the output end for detecting logic circuit, by the second phase inverter
Output freeze be connected with the reset terminal of serial shift registers chain；Detect the reset signal Reset_i and the of logic circuit
The reset terminal of 2-D trigger is connected；
Two inputs are connected with another input of door with the output of 3d flip-flop, and the input clock of 3d flip-flop is with detecing
The output end for surveying logic circuit is connected；The output of 3d flip-flop is connected with the set end of the first d type flip flop, also serves as simultaneously
Detect the feedback signal terminal of logic circuit output.
3. a kind of DRAM hammers pressure circuit for detecting according to claim 2, it is characterised in that it is anti-that detecting logic circuit is exported
Feedback signal end is connected to the control end of a MUX, is used as the feedback of control shift register and OPADD latch
Signal.
4. a kind of DRAM hammers pressure circuit for detecting according to claim 1, it is characterised in that described match logic circuitry bag
Multiple XOR gates are included, the output end connection same OR gate of multi input of XOR gate, multi input exports comparative result with the output end of OR gate；
The output of XOR gate connects the output row address of serial shift registers chain and the row address of OPADD latch respectively
Upper corresponding address signal.
5. a kind of DRAM hammer pressure circuit for detecting according to claim 1, it is characterised in that serial shift registers chain, defeated
Go out address latch and detecting logic circuit shares DRAM clock signal.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106710624A (en) * | 2017-01-06 | 2017-05-24 | 西安紫光国芯半导体有限公司 | DRAM hammer pressure sensing circuit and DRAM hammer pressure sensing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106710624A (en) * | 2017-01-06 | 2017-05-24 | 西安紫光国芯半导体有限公司 | DRAM hammer pressure sensing circuit and DRAM hammer pressure sensing method |
| CN106710624B (en) * | 2017-01-06 | 2024-04-09 | 西安紫光国芯半导体有限公司 | DRAM (dynamic random Access memory) hammer pressure detection circuit and method |
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