CN206412829U - A kind of UPS exchanges Parallel Control circuit - Google Patents
A kind of UPS exchanges Parallel Control circuit Download PDFInfo
- Publication number
- CN206412829U CN206412829U CN201621312607.4U CN201621312607U CN206412829U CN 206412829 U CN206412829 U CN 206412829U CN 201621312607 U CN201621312607 U CN 201621312607U CN 206412829 U CN206412829 U CN 206412829U
- Authority
- CN
- China
- Prior art keywords
- pin
- circuit
- bus
- signal
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
It is of the present utility model it is a kind of can realize UPS exchange parallel function control circuit, its road static switch bus circuit of Shi You seven and two-way CAN bus circuit are combined, each circuit is by realizing Host Status signal, inverter voltage Phase synchronization, carrier synchronization, triggering is synchronous, the system failure is synchronous, civil power turns that battery is synchronous, battery turns synchronous civil power, data CAN communication and machine CAN communication function, realizes that UPS exchanges Parallel Control jointly.The beneficial effects of the utility model：Output synchronization and state synchronized function between each module of Modular UPS can be realized；Data communication is divided into the design of two-way CAN circuit, strengthening system stability with external data communication between UPS internal modules simultaneously；Increase circuit anti-interference design simultaneously, strong antijamming capability, data real effectiveness is high.
Description
Technical field
The utility model is related to uninterrupted power source technical field, and specifically a kind of UPS exchanges Parallel Control circuit is set
Exchange Parallel Control is electric between exchange Parallel Control circuit and complete machine between each module inside meter, more particularly to Modular UPS
Road.
Background technology
At present, Modular UPS is typically to be made up of bypass module, monitoring module and multiple power module parallels, module
Between by exchanging Parallel Control circuit, output is kept same-phase, same frequency, Modular UPS power model is typically all to adopt
Use two CSTR control, control rectification circuit and inverter circuit respectively, how rational design communication Parallel Control circuit, make each mould
Between block can real-time Communication for Power, fast synchronized response, be a key difficulties of current Modular UPS design；While modularization
UPS internal modules are more, and communication data is more, and the signal anti-interference to circuit requires high.Modular UPS requires that support heat is inserted
Technology is pulled out, when module heat is slotting, hot drawing moment produces interference, inside modules may be made to exchange the interference of Parallel Control circuit because and led
Wafer damage is caused, but also can be interfered with other modules in bus, causes mechanical disorder, stability declines.
How exchange Parallel Control circuit design avoids these from disturbing, and the design for exchanging Parallel Control circuit is had also been proposed
Higher requirement.
Utility model content
The purpose of this utility model is to provide for a kind of exchange Parallel Control circuit design applied to Modular UPS, should
Circuit not only realizes the exchange Parallel Control function of the synchronous desired signal of Modular UPS output, while increasing in circuit anti-
Disturbance-proof design, effectively eliminates and the interference of machine signal, it is to avoid the system failure, greatly promotes the stability of system.
To achieve these goals, the technical solution of the utility model is as follows：A kind of UPS exchanges Parallel Control circuit, its
It is characterised by including seven road static switch bus circuits and two-way CAN bus circuit, Modular UPS and machine control work(is realized jointly
Energy；
The static switch bus circuit, includes the data sending terminals of GPIO 1 and bi-directional voltage level conversion of dsp chip
Chip U1 21 pin are connected, and the amplitude for being sent DSP by U1 is converted to+5.0V signal for 3.3V signal, and from the 3 of U1
Pin is exported, the lifting of level, improves the anti-interference and transmission range of signal；U1 23 pin and 24 pin meet+3.3V simultaneously, give
U1 B sides supply+3.3V power supplys；C1 is connected between+3.3V and ground, plays voltage regulation filtering effect；U1 1 pin meets+5.0V, gives
U1 A sides supply+5.0V power supplys；C2 is connected between+5.0V and ground, plays voltage regulation filtering effect；U1 22 pin and GPIO 3
It is connected, as controllable reset signal；R1 is connected between U1 2 pin and ground, and 2 pin are set low, and is represented when 22 pin are set low, number
According to being from the lateral A sides transmission of U1 B；Current-limiting resistance R3 one end is connected with U1 3 pin, the input phase of the other end and diode D2
Even；Diode D2 plays one-way conduction direct current electro ultrafiltration；Filter inductance L1 and L2 connect together, one end and D2 output end phase
Even, the Signal 01 of other end bus is connected, and plays Anti-Jamming；Bus Signal 01 and the bus of other modules
Signal 01 is connected, and realizes intermodule communication；Electric capacity C3 is connected between D2 output ends and ground, and RC circuit decays are constituted with R3
High-frequency signal, plays filter action；Resistance R2 is connected between D2 output ends and ground, and bleeder circuit is constituted with R3；Diode D1
It is connected between D2 output ends and ground, plays voltage clamping；Diode D3 one end is connected with diode D2 output ends, the other end with
Resistance R4 is connected, and plays one-way conduction direct current electro ultrafiltration；Current-limiting resistance R4 one end is connected with D3 output, other end NAND gate
U2_A 2 inputs are connected；Electric capacity C4 is connected between U2_A inputs and ground, is believed with R4 composition RC circuit decays high frequencies
Number, play filter action；Resistance R5 is connected between U2_A inputs and ground, and bleeder circuit is constituted with R4；NAND gate U2_A's
Output and NAND gate U2_B input are cascaded, and play Anti-Jamming；Electric capacity C5 is connected to NAND gate U2_B output
Between end and ground, filter action is played；The GPIO2 data receivers of dsp chip are connected with NAND gate U2_B output end, connect
Receive the transmission signal in bus；
The CAN bus circuit, including the GPIO 19CANATXD of dsp chip send mouth, by NOT gate U8_A and NOT gate
U8_B series filtering circuits, are connected with CAN chips U9 1 pin, constitute the transmitting terminal of data；U9 3 pin connect+5V voltages, 2 pin
GND is met, CAN chip power supplies are given；U9 5 pin are grounded by resistance R101；8 pin are grounded by resistance R100；Resistance R102 one end
It is connected with U9 7 pin, the other end is connected with filter inductance L101；Resistance R103 one end is connected with U9 6 pin, the other end and filtering
Inductance L102 is connected；Resistance R104 one end is connected with R102 and L101 common end, the common end phase of the other end and R103 and L102
Even；The filter inductance L101 other end is connected with the CAN_H of CAN；The filter inductance L102 other end and CAN
CAN_L is connected, and CAN_H and CAN_L collectively constitute CAN signal；NOT gate U8_C and NOT gate U8_D series filtering circuits it is defeated
Enter end with U9 4 pin to be connected, the other end is connected with the receiving ports of GPIO 18 of dsp chip.
The utility model compared with prior art, the beneficial effects of the utility model：Each module of Modular UPS can be realized
Between export synchronous and state synchronized function；Data communication is divided into two-way with external data communication between UPS internal modules simultaneously
CAN circuit is designed, strengthening system stability；Increase circuit anti-interference design, strong antijamming capability, data real effectiveness simultaneously
It is high.
Brief description of the drawings
Fig. 1 is static switch bus circuit schematic diagram in the utility model.
Fig. 2 is CAN bus circuit schematic diagram in the utility model.
Fig. 3 is UPS exchange Parallel Control circuit embodiments schematic diagrames in the utility model.
Embodiment
To make to have a better understanding and awareness to architectural feature of the present utility model and the effect reached, to compared with
Good embodiment and accompanying drawing coordinate detailed description, are described as follows：
As shown in figure 1, in the present embodiment, DSP GPIO 1 sends+3.3V high level signal, through overvoltage electricity
After flat conversion chip U1, output+5.0V high level signal, will by current-limiting resistance R3, diode D2, filter inductance L1, L2
Signal 01 puts high level in bus, similarly, when GPIO 1 sends low level, and Signal 01 sets low level in bus, from
And realize to other modules and send signal；When Signal 01 receives the high level of other modules, after filtering inductance L2,
L1, diode D3, current-limiting resistance R4, NAND gate U2_A, NAND gate U2_B, reach DSP GPIO 2, DSP is received high electricity
Flat, similarly, when Signal 01 receives low level, DSP can receive low level signal, so as to realize other modules of reception
The signal of transmission, in Fig. 1, the RC filter circuits that resistance R3 and electric capacity C3 is constituted can effectively cut down the transmissions of GPIO 1
Interference in signal；Filter inductance L1 and L2, resistance R4 and electric capacity C4 compositions RC filter circuits, electric capacity C5 filtering, NAND gate
U2_A connects with NAND gate U2_B, can effectively cut down the interference in the information received.
As shown in Fig. 2 the GPIO19 data for the DSP that the present embodiment is provided are composed in series by NOT gate U8_A and NOT gate U8_B
Filter circuit after, be sent to CAN chips U9 1 pin, then export a CAN signal by U9 6 pin and 7 pin, then distinguish
By current-limiting resistance R102 and R103, filter inductance L101 and L102, reach in CAN, communicated with other modules, complete
CAN data sending functions；Other modules are sent to the data on data/address bus, after filtering inductance L1 and L2, current-limiting resistance
R102 and R103, is input to 6 pin and 7 pin of CAN chips, is then exported by U9 4 pin, by NOT gate U8_A and NOT gate U8_B
After the filter circuit being composed in series, DSP GPIO18 receiving ports are sent to, the reception of CAN data is completed.
As shown in figure 3, one embodiment of the present utility model is illustrated, the INV dsp chips (1) of power model 1
GPIO19 human hair combing wastes send data by module 1 and machine CAN bus circuit (3) reach on terminal (12), terminal (12) and terminal
(14) by bus (13) connect, module 2 and machine CAN bus circuit (15) receives bus (13) data, be output to power
The INV DSP (24) of module 2 GPIO18 pin, complete module 1 to module 2 and machine signal send；The INV of power model 2
The GPIO19 human hair combing wastes of dsp chip (24) send data by module 1 and machine CAN bus circuit (15) reach on terminal (14), number
According to by bus (13) be connected to up to terminal (12), then to module 1 and machine CAN bus circuit (3) receiving terminal, be then output to
The INV DSP (1) of power model 1 GPIO18 pin, complete the data of the receiving module 2 of module 1, realize and machine CAN communication, complete
Into module-external and machine data communication, similarly, pass through the PFC DSP (2) of power model 1, the data CAN bus circuit of module 1
(11), terminal (12), bus (13), terminal (14), the data CAN bus circuit (23) of module 2, the PFC of power model 2
DSP (25) constitutes another road CAN communication circuit, realizes data CAN communication, completes inside modules and machine data communication, power mould
The GPIO1 human hair combing wastes of the INV dsp chips (1) of block 1 send synchronizing signal, by the first via static switch bus electricity of power model 1
Road (4) is transferred to terminal (12), and the terminal (14) by bus (13) to power model 2 is transferred to the first via of power model 2
Static switch total line (16) input terminal, is then output to the receiving port GPIO2 of the INV dsp chips (24) of power model 2
Pin, completes the transmission of synchronizing signal；The GPIO1 human hair combing wastes of the INV dsp chips (24) of power model 2 send synchronizing signal, by work(
The first via static switch bus circuit (16) of rate module 2 is transferred to terminal (14), and the end of power model 1 is arrived by bus (13)
Sub (12) are transferred to first via static switch total line (4) input terminal of power model 1, are then output to power model 1
The receiving port GPIO2 pin of INV DSP chips (1), complete the reception of synchronizing signal；First via synchronizing signal telecommunication circuit is constituted,
Realize powered on moment, slave competition functionality, similarly, by the GPIO3 and GPIO4 of the INV dsp chips (1) of power model 1,
Second road static switch bus circuit (5) of power model 1, terminal (12), bus (13), terminal (14), power model 2
Second road static switch bus circuit (17), the GPIO3 and GPIO4 of the INV dsp chips (24) of power model 2 are collectively formed
The second tunnel synchronizing signal telecommunication circuit, realizes inverter voltage Phase synchronization function.By the INV dsp chips (1) of power model 1
GPIO5 and GPIO6, the 3rd road static switch bus circuit (6) of power model 1, terminal (12), bus (13), terminal
(14), the 3rd road static switch bus circuit (18) of power model 2, the GPIO5 of the INV dsp chips (24) of power model 2
The 3rd tunnel synchronizing signal telecommunication circuit is together constituted with GPIO6, host and slave processors PWM carrier phase function synchronizing functions are realized.By
The GPIO7 and GPIO8 of the INV dsp chips (1) of power model 1, the 4th road static switch bus circuit of power model 1
(7), terminal (12), bus (13), terminal (14), the 4th road static switch bus circuit (19) of power model 2, power model
The GPIO7 and GPIO8 of 2 INV dsp chips (24) together constitute the 4th tunnel synchronizing signal telecommunication circuit, realize that bypass turns inverse
Become, inversion turns bypass action handover trigger synchronizing function.By power model 1 INV DSP chips (1) GPIO9 and
GPIO10, the 5th road static switch bus circuit (8) of power model 1, terminal (12), bus (13), terminal (14), power mould
5th road static switch bus circuit (20) of block 2, the GPIO9 and GPIO10 of the INV dsp chips (24) of power model 12 are total to
With the 5th tunnel synchronizing signal telecommunication circuit is constituted, the important failed synchronization Trigger Function of system is realized.By the PFC of power model 1
The GPIO11 and GPIO12 of dsp chip (2), the 6th road static switch bus circuit (9), terminal (12), the bus of power model 1
(13), terminal (14), the 6th road static switch bus circuit (21) of power model 2, the PFC dsp chips of power model 2
(25) GPIO11 and GPIO12 together constitutes the 6th tunnel synchronizing signal telecommunication circuit, realizes that utility mode turns battery mode
Synchronous Trigger Function, the 7th road by the GPIO13 and GPIO14 of the PFC dsp chips (2) of power model 1, power model 1 is quiet
State bus switches circuit (10), terminal (12), bus (13), terminal (14), the 7th road static switch bus electricity of power model 2
Road (22), the GPIO13 and GPIO14 of the PFC dsp chips (25) of power model 2 together constitute the 7th tunnel synchronizing signal communication
Circuit, realizes that battery mode turns the synchronous Trigger Function of utility mode.
General principle of the present utility model, principal character and advantage of the present utility model has been shown and described above；One's own profession
The technical staff of industry is it should be appreciated that the utility model is not restricted to the described embodiments, described in above-described embodiment and specification
Simply principle of the present utility model, the utility model also has respectively on the premise of the utility model spirit and scope are not departed from
Changes and improvements are planted, these changes and improvements are both fallen within the range of claimed the utility model；The utility model requirement
Protection domain defined by appended claims and its equivalent.
Claims (1)
1. a kind of UPS exchanges Parallel Control circuit, it is characterised in that including seven road static switch bus circuits and two-way CAN
Circuit, realizes Modular UPS and machine control function jointly；
The static switch bus circuit, includes the data sending terminals of GPIO 1 and bi-directional voltage electrical level transferring chip of dsp chip
U1 21 pin are connected, and the amplitude for being sent DSP by U1 is converted to+5.0V signal for 3.3V signal, and defeated from U1 3 pin
Go out, the lifting of level, improve the anti-interference and transmission range of signal；U1 23 pin and 24 pin meet+3.3V simultaneously, the B to U1
Side supply+3.3V power supplys；C1 is connected between+3.3V and ground, plays voltage regulation filtering effect；U1 1 pin meets+5.0V, the A to U1
Side supply+5.0V power supplys；C2 is connected between+5.0V and ground, plays voltage regulation filtering effect；U1 22 pin are connected with GPIO 3,
As controllable reset signal；R1 is connected between U1 2 pin and ground, and 2 pin are set low, represent when 22 pin are set low, data be from
The U1 lateral A sides transmission of B；Current-limiting resistance R3 one end is connected with U1 3 pin, and the other end is connected with diode D2 input；Two
Pole pipe D2 plays one-way conduction direct current electro ultrafiltration；Filter inductance L1 and L2 connect together, and one end is connected with D2 output end, another
Hold the Signal 01 of bus to be connected, play Anti-Jamming；Bus Signal 01 and the phases of bus Signal 01 of other modules
Even, intermodule communication is realized；Electric capacity C3 is connected between D2 output ends and ground, and RC circuit decay high-frequency signals are constituted with R3, is risen
To filter action；Resistance R2 is connected between D2 output ends and ground, and bleeder circuit is constituted with R3；Diode D1 is connected to D2 outputs
Between end and ground, voltage clamping is played；Diode D3 one end is connected with diode D2 output ends, and the other end is connected with resistance R4,
Play one-way conduction direct current electro ultrafiltration；Current-limiting resistance R4 one end is connected with D3 output, other end NAND gate U2_A 2 inputs
End is connected；Electric capacity C4 is connected between U2_A inputs and ground, and RC circuit decay high-frequency signals are constituted with R4, is played filtering and is made
With；Resistance R5 is connected between U2_A inputs and ground, and bleeder circuit is constituted with R4；NAND gate U2_A output and NAND gate
U2_B input is cascaded, and plays Anti-Jamming；Electric capacity C5 is connected between NAND gate U2_B output end and ground, is risen
To filter action；The GPIO2 data receivers of dsp chip are connected with NAND gate U2_B output end, receive the transmission in bus
Signal；
The CAN bus circuit, including the GPIO 19CANA TXD of dsp chip send mouth, by NOT gate U8_A and NOT gate U8_B
Series filtering circuit, is connected with CAN chips U9 1 pin, constitutes the transmitting terminal of data；U9 3 pin connect+5V voltages, and 2 pin meet GND,
Give CAN chip power supplies；U9 5 pin are grounded by resistance R101；8 pin are grounded by resistance R100；Resistance R102 one end and the 7 of U9
Pin is connected, and the other end is connected with filter inductance L101；Resistance R103 one end is connected with U9 6 pin, the other end and filter inductance
L102 is connected；Resistance R104 one end is connected with R102 and L101 common end, and the other end is connected with R103 and L102 common end；Filter
The ripple inductance L101 other end is connected with the CAN_H of CAN；The filter inductance L102 other end and the CAN_L phases of CAN
Even, CAN_H and CAN_L collectively constitute CAN signal；NOT gate U8_C and NOT gate U8_D series filtering circuits input and U9
4 pin be connected, the other end is connected with the receiving ports of GPIO 18 of dsp chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621312607.4U CN206412829U (en) | 2016-12-02 | 2016-12-02 | A kind of UPS exchanges Parallel Control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621312607.4U CN206412829U (en) | 2016-12-02 | 2016-12-02 | A kind of UPS exchanges Parallel Control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206412829U true CN206412829U (en) | 2017-08-15 |
Family
ID=59550386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621312607.4U Active CN206412829U (en) | 2016-12-02 | 2016-12-02 | A kind of UPS exchanges Parallel Control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206412829U (en) |
-
2016
- 2016-12-02 CN CN201621312607.4U patent/CN206412829U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102739234B (en) | Multi-channel digital signal input/output isolating box and power control system | |
| CN108279601A (en) | A kind of multi-channel digital TT＆C system based on I2C+CAN buses | |
| CN206389350U (en) | A kind of light-coupled isolation communicating circuit | |
| CN205754408U (en) | A kind of switch with forward and reverse function of supplying power | |
| CN205302279U (en) | Serial interface data protocol converter | |
| CN207301680U (en) | A kind of controller and robot | |
| CN206412829U (en) | A kind of UPS exchanges Parallel Control circuit | |
| CN202548210U (en) | Phase sequence detection circuit for three-phase electricity | |
| CN201869195U (en) | Small-sized power line communication electrical equipment | |
| CN107450378A (en) | A kind of controller and robot | |
| CN206649657U (en) | A kind of power supply unit electricity charge acquisition system | |
| CN108880878A (en) | NB-IOT network switching device | |
| CN106961153A (en) | A kind of UPS exchanges Parallel Control circuit | |
| CN205232225U (en) | Medium voltage electricity live width area carrier communication module | |
| CN207896971U (en) | A kind of fiber optical transceiver of band distal end fault location function | |
| CN107273330A (en) | Three-wire system serial communication interface isolation circuit module | |
| CN107424402A (en) | The carrier module that can be communicated with external equipment | |
| CN203521836U (en) | Interface transition platelet for electrical energy acquisition terminal | |
| CN205407248U (en) | CAN -BUS protection circuit and motion control system who uses thereof | |
| CN203313216U (en) | Multi-medium internet gateway device | |
| CN205864075U (en) | A kind of active power distribution network intelligent terminal's accumulator isolation monitoring device | |
| CN207282006U (en) | Final stage device for low-voltage collecting meter reading system monitors system | |
| CN202949434U (en) | Comprehensive access terminal based on synchronous digital hierarchy (SDH) | |
| CN201122963Y (en) | Device for power supply by twisted pair line and implementing multi-machine digital communication | |
| CN202257561U (en) | Protocol converters |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |