CN206321776U - A kind of circuit that FID signal frequency-measurement accuracy is improved based on quantization delay method - Google Patents
A kind of circuit that FID signal frequency-measurement accuracy is improved based on quantization delay method Download PDFInfo
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- CN206321776U CN206321776U CN201720003276.4U CN201720003276U CN206321776U CN 206321776 U CN206321776 U CN 206321776U CN 201720003276 U CN201720003276 U CN 201720003276U CN 206321776 U CN206321776 U CN 206321776U
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Abstract
The utility model discloses a kind of circuit that FID signal frequency-measurement accuracy is improved based on quantization delay method, including dynamical nuclear polarization weak magnetic sensor, high-frequency oscillating circuits, signal conditioning circuit, hysteresis loop comparator, crystal oscillating circuit, FPGA digital Frequency Measuring modules, controller and memory cell, the input connection high-frequency oscillating circuits of the dynamical nuclear polarization weak magnetic sensor, the output end connection signal conditioning circuit of the dynamical nuclear polarization weak magnetic sensor, the signal conditioning circuit connects hysteresis loop comparator, the output end of the hysteresis loop comparator and crystal oscillating circuit is all connected with FPGA digital Frequency Measuring modules, the FPGA digital Frequency Measurings module connects controller, the controller connects memory cell, the utility model utilizes the principle of equally accurate frequency measurement, design error compensates part in FPGA digital Frequency Measuring modules, bigness scale and thin survey are combined, frequency-measurement accuracy is greatly improved.
Description
Technical field
The utility model is related to earth weak magnetic measurement technical field, more particularly to a kind of to be improved based on quantization delay method
The circuit of FID signal frequency-measurement accuracy.
Background technology
Dynamical nuclear polarization magnetometer have it is low in energy consumption, without dead band, sensitivity is high the features such as, geophysics magnetic prospecting,
Geoscience research, these fields of antisubmarine, transport by satellite have obtained commonly used.Dynamical nuclear polarization magnetometer generally includes two kinds
Resonator system：Electron spin resonance and nuclear magnetic resonance, electron spin resonance and two of the instrument using radio frequency electromagnetic field generation
The coupling relaxation of resonator system, by the energy transfer of electron spin resonance to nuclear magnetic resonance, so as to improve in sensor
The macroscopic moment of proton spin, and output FID signal (the Free Induction Decay in the presence of magnetic deflection field
Singal, free induction decay signal), dynamical nuclear polarization magnetometer is calculated by measuring FID signal frequency using gyromagnetic ratio
To current geomagnetic field intensity, therefore its frequency-measurement accuracy directly determines the measurement accuracy in magnetic field.But in actual applications, dynamic
The FID signal frequency that nuclear polarization magnetometer is directly measured is not high.
At present, generally using based on CPLD (Complex Programable Logic Device, complex programmable logic
Device) multi-period synchronizing method improve dynamical nuclear polarization magnetometer FID signal frequency-measurement accuracy, or by two kinds measurement function magnetic force
Instrument design realizes static polarization measurement and dynamic polarization using single-pole double-throw switch (SPDT), with humorous electric capacity and different polarized circuits
The unification of measurement, or using fft algorithm (Fast Fourier Transform Algorithm, fast Fourier transformation algorithm) and
The frequency measuring method that CZT algorithms (Chirp Z-transform, chirp Z-transform algorithm) are combined, is obtained using fft algorithm
Frequency coarse value, then frequency spectrum refinement is carried out by CZT algorithms, traditional time domain measurement is transformed into frequency domain measurement.
But, first method uses comparator and CPLD is measured, and does not account for nonsynchronous to clock edge
Part carries out error compensation；Second method uses traditional hard ware measure method, after being decayed to because of later stage FID signal
Phase, signal to noise ratio is too low, inevitably has counting error；3rd method uses ADC+FFT+CZT algorithm, eliminates letter
Make an uproar than too low counting error, but also can be deteriorated because of signal quality, influence frequency-measurement accuracy.
The content of the invention
In view of this, embodiment of the present utility model provides a kind of based on quantization delay method raising dynamical nuclear polarization magnetic force
The circuit of instrument FID signal frequency-measurement accuracy.
Embodiment of the present utility model provides a kind of circuit that FID signal frequency-measurement accuracy is improved based on quantization delay method, bag
Include dynamical nuclear polarization weak magnetic sensor, high-frequency oscillating circuits, signal conditioning circuit, hysteresis loop comparator, crystal oscillating circuit, FPGA numerals
Frequency measurement module (Field Programmable Gate Array, field programmable gate array), controller and memory cell, institute
State the input connection high-frequency oscillating circuits of dynamical nuclear polarization weak magnetic sensor, the output of the dynamical nuclear polarization weak magnetic sensor
End connection signal conditioning circuit, the signal conditioning circuit connects hysteresis loop comparator, the hysteresis loop comparator and crystal oscillating circuit
Output end is all connected with FPGA digital Frequency Measuring modules, and the FPGA digital Frequency Measurings module connects controller, and the controller connection is deposited
Storage unit.
Further, the FPGA digital Frequency Measurings module includes control signal part, segment count and error compensation part.
Further, the control signal part includes programmable frequency divider and two d type flip flops, the programmable frequency divider
Frequency dividing ratio can be adjusted according to actual test situation.
Further, the segment count includes the first counter and the second counter.
Further, the error compensation part includes two time-interval-units, each time-interval-unit
Constituted by some unit delay units, some d type flip flops and latch, the unit delay unit connects d type flip flop, described
D type flip flop connects latch.
Further, the memory cell is USB flash disk.
Compared with prior art, the utility model is simple in construction, is related to ingenious；Using the principle of equally accurate frequency measurement,
Design error compensates part in FPGA digital Frequency Measuring modules, and bigness scale and thin survey are combined, and frequency-measurement accuracy is greatly improved；Quantify
Time delay method is to be based on temporal interpolation delay line technique, overcomes the defect that analog interpolator hardware is complicated, be difficult to realization, measurement system
System is made up of digital circuit, can be integrated in FPGA, it is easy to accomplish and reliability is high；Can be according to actual conditions to corresponding soft
Part is overlapped and chip selection is made adjustment, and reduces improvement cost.
Brief description of the drawings
Fig. 1 is a kind of embodiment of circuit one that FID signal frequency-measurement accuracy is improved based on quantization delay method of the utility model
Circuit the general frame.
Fig. 2 is the circuit diagram of FPGA digital Frequency Measuring modules in Fig. 1.
Fig. 3 is the workflow diagram of the embodiment of the utility model one.
Fig. 4 is the principle oscillogram of the frequency measuring method used in the embodiment of the utility model one.
Embodiment
It is new to this practicality below in conjunction with accompanying drawing to make the purpose of this utility model, technical scheme and advantage clearer
Type embodiment is further described.
Fig. 1 is refer to, embodiment of the present utility model provides a kind of based on quantization delay method raising FID signal frequency measurement essence
The circuit of degree, including high-frequency oscillating circuits 1, dynamical nuclear polarization weak magnetic sensor 2, signal conditioning circuit 3, hysteresis loop comparator 4, crystalline substance
Shake circuit 5, FPGA digital Frequency Measurings module 6, controller 7 and memory cell 8, in one embodiment, the memory cell is USB flash disk,
The input connection high-frequency oscillating circuits 1 of dynamical nuclear polarization weak magnetic sensor 2, the excitation dynamical nuclear polarization of high-frequency oscillating circuits 1 is weak
Magnetic Sensor 2 produces FID signal, the output end connection signal conditioning circuit 3 of dynamical nuclear polarization weak magnetic sensor 2, signal condition
Circuit 3 connects hysteresis loop comparator 4, the FID signal of the output of the conditioning dynamical nuclear polarization of signal conditioning circuit 3 weak magnetic sensor 2, signal
The FID signal that modulate circuit 3 is exported to dynamical nuclear polarization weak magnetic sensor 2 is amplified and filtered conditioning, and by after conditioning
The output end of FID signal input hysteresis loop comparator 4, hysteresis loop comparator 4 and crystal oscillating circuit 5 is all connected with FPGA digital Frequency Measurings module 6,
Crystal oscillating circuit 5 exports time-base signal, and the FID signal after 4 pairs of conditionings of hysteresis loop comparator exports measured signal, FPGA after handling
Digital Frequency Measuring module 6 connects controller 7, and controller 7 connects memory cell 8, and FPGA digital Frequency Measurings module 6 is to time-base signal and treats
Survey signal to be handled, controller 7 reads the result of FPGA digital Frequency Measurings module 6, and calculates the frequency of FID signal, deposits
Storage unit 8 stores result of calculation.
Fig. 2 is refer to, FPGA digital Frequency Measurings module 6 includes control signal part 61, segment count 62 and error compensation portion
Divide 63, control signal part 61, segment count 62 and error compensation part 63 are connected with each other.
Control signal part 61 includes programmable frequency divider 611 and two d type flip flops 601, and programmable frequency divider 611 can
Frequency dividing ratio is adjusted according to actual test situation.
Segment count 62 includes the first counter (CNT1) 621 and the second counter (CNT2) 622.
Error compensation part 63 include two time-interval-units 631, if each time-interval-unit 631 by
Dry unit delay unit 632, some d type flip flops 601 and latch 634 are constituted, the connection d type flip flop of unit delay unit 632
601, the connection latch 634 of d type flip flop 601.
It refer to Fig. 3, the course of work：
(1) dynamical nuclear polarization weak magnetic sensor 2 produces FID signal, the higher-order of oscillation 1 by the excitation of high-frequency oscillating circuits 1
Circuit produces RF magnetic field, and RF magnetic field makes the electronic spin system in dynamical nuclear polarization weak magnetic sensor 2 resonate, dynamic kernel pole
Changing in weak magnetic sensor 2 has free radical, and electronic system energy is completed to the transfer of proton system energy by free radical, then by matter
Subsystem energy encourages to produce FID signal, FID signal input signal conditioning circuit 3, signal conditioning circuit by DC pulse
3 pairs of FID signals are amplified and filtered conditioning, and the signal after conditioning is inputted into hysteresis loop comparator 4, by hysteresis loop comparator 4
Shaping after obtain measured signal；
(2) output of crystal oscillating circuit 5 time-base signal, the measured signal that time-base signal and step (1) are obtained is inputted respectively
FPGA digital Frequency Measurings module 6, the FPGA digital Frequency Measurings module 6 is entered by equal precision measuring frequency way to time-base signal and measured signal
Row processing；
The control signal part 61 of FPGA digital Frequency Measurings module 6 is joined by time-base signal by programmable frequency divider 611
Signal strobe is examined, actual signal strobe, actual gate are obtained by the synchronous measured signal of a d type flip flop 601 with reference to signal strobe
Base signal strobe when signal is obtained by the synchronous time-base signal of another d type flip flop 601, when base signal strobe be control signal；
Afterwards, segment count 62 sends into time-base signal and actual signal strobe in the first counter 621, by actual gate
First pulse of the time-base signal after signal pulse rising edge starts the first counter 621 and counted, under actual signal strobe
The first counter 621 is closed in the pulse of time-base signal of the drop after, obtains the number of time-base signal pulse；By square-wave signal and
Actual signal strobe is sent into the second counter 622, by first of the measured signal after actual signal strobe rising edge of a pulse
Individual pulse starts the second counter 622 and counted, and the pulse of measured signal is closed second and counted after actual signal strobe trailing edge
Device 622, obtains the pulse number of measured signal；
Two time-interval-units 631 of error compensation part 63 using actual signal strobe as enabling signal,
Control signal is triggered as end signal, the d type flip flop 601 of a time-interval-unit 631 from rising edge, Ling Yishi
Between the d type flip flop 601 of interval measurement unit 631 triggered from trailing edge, calculate actual gate time, reality by quantifying time delay method
The nonsynchronous part in the edge of border signal strobe and the edge of time-base signal compensates time, institute using quantization delay method calculation error
The part for stating the edge of actual signal strobe and the edge synchronization of time-base signal directly uses the first counter 621 to time-base signal
Measure, the second counter 622 is measured to measured signal；
Quantization delay method calculating actual gate time comprises the following steps：
Determine the delay cell and amount of delay in the delay chain that starting impulse signal passes through in communication process；
Starting impulse signal carries out real-time sampling after each delay cell to stop pulse signal, when stop pulse letter
Number from low level be changed into high level when, under effective rising edge d type flip flop 601 just latched starting impulse signal arrival it is specific
Position, obtains a n+1 bit sequences code and latches；
The sequence code measured is analyzed, it is high level that measurement result, which depends on generation low transition in sequence code,
Position where lowest order, numerical value now is the number of delay unit, can calculate time-interval-unit
The error compensation time；
The time-base signal number of pulses measured by the first counter is asynchronous with the signal edge that quantization time expander method is measured
The partial error compensation time obtains actual gate time.
If equal with actual gate time t with reference to gate time T,：T=t, t=n1gT0=n2gTc, can obtain to be measured
Frequency is：
In formula：f0For measured signal, fcFor time-base signal frequency, n1, n2Respectively time-base signal and measured signal pulse
Number.
In actually measurement, f to measured signal0The beginning and ending time of counting is triggered by the rising edge of the signal,
To f in gate time t0Counting it is error free；To time-base signal fcCounting n1At most differ the error of a number, i.e. Δ n1, therefore
The relative error of measurement is：
It is only relevant with the frequency of gate time and time-base signal therefore the precision of measurement frequency is unrelated with measured signal, therefore
Gate time is accurately measured, the high time-base signal of frequency of use can improve the precision of measurement.
As shown in figure 4, in actual measurement, actual gate time is not fixed value, and because same measured signal is synchronous, its value
For the integral multiple in measured signal cycle, f to measured signal is eliminated0Counting error, still, the edge of actual signal strobe with
The edge of time-base signal is not fully synchronous in measurement process, there is corresponding error.
Sync section：G1 is the actual signal strobe synchronously obtained with measured signal with reference to gate, and G2 is actual gate letter
Control signal obtained by number synchronous time-base signal, in continuous frequency measurement, the continuous meter of the first counter 621, the second counter 622
Number, its numerical value n recorded1、n2Time-base signal pulse number and measured signal pulse number are represented respectively.
Asynchronous part：The startup of the rising edge of actual signal strobe pulse as a time-interval-unit is believed
Number, i.e. S1, when base signal strobe pulse rising edge be used as stop signal, i.e. E1；By the trailing edge of actual signal strobe pulse
As the enabling signal of another time-interval-unit, i.e. S2, when base signal strobe pulse trailing edge along as stopping letter
Number, i.e. E2, the delay unit number measured by two time-interval-units 631 is respectively n3、n4, when using quantization
The error compensation time for prolonging method to measure actual gate time.
If starting impulse signal sequentially passes through n+1 grades of delay cells, the amount of delay of delay cell is τ, time-base signal cycle
For Tc, overlapped on the rising edge edge with stop signal after n-th grade of delay cell, then time interval T to be measuredxFor：
Tx=n τ；
Therefore, in the measurements, actual gate time is：
T=n1×Tc+ΔT1-ΔT2；
ΔT1=n3G τ, Δ T2=n4gτ；
Then：T=n1×Tc+(n3-n4)τ；
(4) result of FPGA digital Frequency Measurings module 6 is read by controller 7, and to the data after step (2) processing
Frequency calculating and error compensation are carried out, the frequency of FID signal is obtained；
The frequency computing formula of FID signal is：
In formula：f0For the frequency of FID signal, n2For the pulse number of measured signal.
The utility model utilizes the principle of equally accurate frequency measurement, the method for taking " bigness scale+thin survey " accurate measurement, significantly carries
High frequency-measurement accuracy；Quantization delay method is to be based on temporal interpolation delay line technique, overcomes analog interpolator hardware complexity, is difficult to
The defect of realization, measuring system is made up of digital circuit, can be integrated in FPGA, it is easy to accomplish and reliability is high；This frequency measurement side
The resolution ratio of method depends on the amount of delay of unit delay unit, corresponding software can be overlapped according to actual conditions and chip choosing
Select and make adjustment, reduce improvement cost.
In the case where not conflicting, the feature in embodiment and embodiment herein-above set forth can be combined with each other.
Preferred embodiment of the present utility model is the foregoing is only, it is all in this practicality not to limit the utility model
Within new spirit and principle, any modifications, equivalent substitutions and improvements made etc. should be included in guarantor of the present utility model
Within the scope of shield.
Claims (6)
1. a kind of circuit that FID signal frequency-measurement accuracy is improved based on quantization delay method, it is characterised in that weak including dynamical nuclear polarization
Magnetic Sensor, high-frequency oscillating circuits, signal conditioning circuit, hysteresis loop comparator, crystal oscillating circuit, FPGA digital Frequency Measurings module, control
Device and memory cell, the input connection high-frequency oscillating circuits of the dynamical nuclear polarization weak magnetic sensor, the dynamical nuclear polarization
The output end connection signal conditioning circuit of weak magnetic sensor, the signal conditioning circuit connects hysteresis loop comparator, the hysteresis ratio
Output end compared with device and crystal oscillating circuit is all connected with FPGA digital Frequency Measuring modules, and the FPGA digital Frequency Measurings module connects controller,
The controller connects memory cell.
2. the circuit according to claim 1 that FID signal frequency-measurement accuracy is improved based on quantization delay method, it is characterised in that
The FPGA digital Frequency Measurings module includes control signal part, segment count and error compensation part.
3. the circuit according to claim 2 that FID signal frequency-measurement accuracy is improved based on quantization delay method, it is characterised in that
The control signal part includes programmable frequency divider and two d type flip flops, and the programmable frequency divider can be surveyed according to actual
Examination situation adjusts frequency dividing ratio.
4. the circuit according to claim 2 that FID signal frequency-measurement accuracy is improved based on quantization delay method, it is characterised in that
The segment count includes the first counter and the second counter.
5. the circuit according to claim 2 that FID signal frequency-measurement accuracy is improved based on quantization delay method, it is characterised in that
The error compensation part includes two time-interval-units, and each time-interval-unit is delayed by some units
Unit, some d type flip flops and latch are constituted, and the unit delay unit connects d type flip flop, and the d type flip flop connection is latched
Device.
6. the circuit according to claim 1 that FID signal frequency-measurement accuracy is improved based on quantization delay method, it is characterised in that
The memory cell is USB flash disk.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720003276.4U CN206321776U (en) | 2017-01-03 | 2017-01-03 | A kind of circuit that FID signal frequency-measurement accuracy is improved based on quantization delay method |
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| CN201720003276.4U CN206321776U (en) | 2017-01-03 | 2017-01-03 | A kind of circuit that FID signal frequency-measurement accuracy is improved based on quantization delay method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113092858A (en) * | 2021-04-12 | 2021-07-09 | 湖南师范大学 | High-precision frequency scale comparison system and comparison method based on time-frequency information measurement |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113092858A (en) * | 2021-04-12 | 2021-07-09 | 湖南师范大学 | High-precision frequency scale comparison system and comparison method based on time-frequency information measurement |
| CN113092858B (en) * | 2021-04-12 | 2022-04-12 | 湖南师范大学 | High-precision frequency scale comparison system and comparison method based on time-frequency information measurement |
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Granted publication date: 20170711 Termination date: 20180103 |