CN206301128U - A kind of array base palte and display device - Google Patents
A kind of array base palte and display device Download PDFInfo
- Publication number
- CN206301128U CN206301128U CN201720003773.4U CN201720003773U CN206301128U CN 206301128 U CN206301128 U CN 206301128U CN 201720003773 U CN201720003773 U CN 201720003773U CN 206301128 U CN206301128 U CN 206301128U
- Authority
- CN
- China
- Prior art keywords
- electrode
- array base
- columns
- pixel electrodes
- base palte
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The utility model discloses a kind of array base palte and display device, the semiconductor layer of driving transistor includes bar shaped portion, first connecting portion and the part of second connecting portion three composition, bar shaped portion is arranged at pixel electrode side in a first direction, pixel electrode side in a first direction is arranged at by the overlapping region in grid and bar shaped portion, to improve the utilization rate of pixel electrode both sides in a first direction, and pixel electrode enlarged-area in a second direction can be made, and then the aperture opening ratio of lifting pixel cell, improve the display effect of display device.
Description
Technical field
The utility model is related to display technology field, more specifically, is related to a kind of array base palte and display device.
Background technology
With the development of information technology, liquid crystal display is widely used in the various aspects of information science, example
Such as, because Thin Film Transistor-LCD has the low advantage of light, thin, power consumption, it is widely used in TV, notebook electricity
In the present information equipment such as brain, mobile phone, personal digital assistant.At present, liquid crystal display application commercially is increasingly
It is important.Array base palte is one of important composition part of liquid crystal display device, and it includes a plurality of gate line and a plurality of data lines,
And gate line and data wire intersect the multiple pixel cells of restriction.Wherein, included in each pixel cell a driving transistor and
One pixel electrode.In display picture, the conducting of gate line driving transistor, the signal transmission that then transistor sends data wire
To pixel electrode, one reaches the purpose of display picture.Because driving transistor region is lightproof area, so driving transistor
Structure design directly affects the aperture opening ratio of pixel cell, therefore is the master of technology today personnel to the structure design of driving transistor
Want one of research direction.
Utility model content
In view of this, the utility model provides a kind of array base palte and display device, the semiconductor layer of driving transistor
Including bar shaped portion, first connecting portion and the part of second connecting portion three composition, bar shaped portion is arranged at pixel electrode in a first direction
On side, the overlapping region in grid and bar shaped portion is arranged at pixel electrode side in a first direction, to improve picture
The utilization rate of plain electrode both sides in a first direction, and pixel electrode enlarged-area in a second direction can be made, and then lifted
The aperture opening ratio of pixel cell, improves the display effect of display device.
To achieve the above object, the technical scheme that the utility model is provided is as follows：
A kind of array base palte, including the multiple columns of pixel electrodes and a plurality of data lines for arranging in the first direction, it is each described
Columns of pixel electrodes described in data wire correspondence one, and the data wire extends in a second direction, the first direction and second direction
Intersect, the data wire is connected by a driving transistor with a pixel electrode in the corresponding columns of pixel electrodes, wherein, it is described
Driving transistor includes：
Semiconductor layer, the semiconductor layer include extend in a second direction bar shaped portion, in this second direction with institute
State the first connecting portion of the first end connection in bar shaped portion and in said first direction connected with second end in the bar shaped portion
Second connecting portion；
With the overlapping grid for setting of bar shaped portion insulation；
And, the first electrode for setting is contacted with the first connecting portion, and contact what is set with the second connecting portion
Second electrode, wherein, the first electrode connects the data wire, and the second electrode connects the pixel electrode.
Optionally, in this second direction, the second connecting portion is located in the columns of pixel electrodes, two neighboring picture
Region between plain electrode.
Optionally, the grid includes the first friendship that is overlapping with bar shaped portion insulation and being arranged along the second direction
Folded portion and the second overlap, with the interconnecting part for connecting first overlap and the second overlap.
Optionally, with homonymy one end of the second overlap be connected first overlap by the interconnecting part, wherein, it is described
The grid of the first overlap, the second overlap and interconnecting part composition takes the shape of the letter U.
Optionally, on the light direction of the array base palte, light shield layer is additionally provided with positioned at semiconductor layer lower section；
Wherein, the light shield layer is overlapping with the bar shaped portion.
Optionally, the data wire is located at same metal level, the data wire multiplexing described first with the first electrode
Electrode, and the data wire overlaps setting with the bar shaped portion in this second direction.
Optionally, each columns of pixel electrodes includes the first pixel electrode to N pixels electricity along the second direction
Pole, N is the integer not less than 1；
Wherein, in all driving transistors that the ith pixel electrode with all columns of pixel electrodes is connected, respectively with
Two driving transistors of ith pixel electrode connection described in adjacent two, its corresponding grid of difference is connected with each other, described to be formed
I-th gate line of array base palte, i is the no more than positive integer of N.
Optionally, when the grid takes the shape of the letter U, the two neighboring described grid of i-th gate line, its U-shaped are connected to
Opening towards opposite.
Optionally, the multiple columns of pixel electrodes is defined as the first columns of pixel electrodes to M columns of pixel electrodes, and each institute
Stating columns of pixel electrodes includes the first pixel electrode along the second direction to N pixel electrodes, and N is the integer not less than 1, M
It is the integer not less than 2；
Wherein, all pixels electrode of the columns of pixel electrodes of all even numbers is arranged in array, the pixel electrode of all odd numbers
The all pixels electrode of row is arranged in array, and the columns of pixel electrodes of the even number ith pixel electrode region, it is and described
The ith pixel electrode region of the columns of pixel electrodes of odd number Heterogeneous Permutation in this second direction, i be no more than N just
Integer.
Optionally, the two neighboring grid for being connected to i-th gate line is connected by a connecting line；
Wherein, in the two neighboring described connecting line of i-th gate line is connected to, connecting line described in is located at and it
Between the ith pixel electrode and i+1 pixel electrode of corresponding columns of pixel electrodes, another connecting line is certainly corresponding to its
Columns of pixel electrodes the ith pixel electrode region insulation cross.
Optionally, the array base palte includes：
Bearing substrate；
Positioned at the active layer of the bearing substrate side, the active layer includes the semiconductor layer；
Deviate from the gate insulation layer of the bearing substrate side positioned at the active layer；
Deviate from the first metal layer of the bearing substrate side positioned at the gate insulation layer, the first metal layer includes institute
State grid；
Deviate from the separation layer of the bearing substrate side positioned at the first metal layer；
And, the second metal layer of the bearing substrate side, the second metal layer bag are deviated from positioned at the separation layer
First electrode and second electrode are included, wherein, the first electrode and second electrode pass through via and the first connecting portion respectively
It is in contact setting with second connecting portion.
Optionally, the array base palte includes：
Bearing substrate；
Positioned at the first metal layer of the bearing substrate side, the first metal layer includes the grid；
Deviate from the gate insulation layer of the bearing substrate side positioned at the first metal layer；
Deviate from the active layer of the bearing substrate side positioned at the gate insulation layer, the active layer includes the semiconductor
Layer；
Deviate from the second metal layer of the bearing substrate side positioned at the active layer, the second metal layer includes first
Electrode and second electrode, wherein, the first electrode and second electrode respectively with the first connecting portion and second connecting portion phase
Contact is set.
Accordingly, the utility model additionally provides a kind of display device, and the display device includes above-mentioned array base palte.
Compared to prior art, the technical scheme that the utility model is provided at least has advantages below：
The utility model provides a kind of array base palte and display device, including the multiple pixels electricity for arranging in the first direction
Pole arranges and a plurality of data lines, columns of pixel electrodes described in each data wire correspondence one, and the data wire prolongs in a second direction
Stretch, the first direction and second direction are intersected, the data wire is by a driving transistor and the corresponding columns of pixel electrodes
In a pixel electrode be connected, wherein, the driving transistor includes：Semiconductor layer, the semiconductor layer is included in a second direction
The bar shaped portion of extension, the first connecting portion for being connected with the first end in the bar shaped portion in this second direction and described first
The second connecting portion connected with second end in the bar shaped portion on direction；With the overlapping grid for setting of bar shaped portion insulation；With
And, the first electrode for setting is contacted with the first connecting portion, and the second electrode for setting is contacted with the second connecting portion, its
In, the first electrode connects the data wire, and the second electrode connects the pixel electrode.
As shown in the above, the technical scheme that the utility model is provided, the semiconductor layer of driving transistor includes bar shaped
Portion, first connecting portion and the part of second connecting portion three composition, pixel electrode side in a first direction is arranged at by bar shaped portion,
Pixel electrode side in a first direction is arranged at by the overlapping region in grid and bar shaped portion, to improve pixel electrode the
The utilization rate of one both sides on direction, and pixel electrode enlarged-area in a second direction can be made, and then lift pixel cell
Aperture opening ratio, improves the display effect of display device.
Brief description of the drawings
In order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art, below will be to embodiment
Or the accompanying drawing to be used needed for description of the prior art is briefly described, it should be apparent that, drawings in the following description are only
It is embodiment of the present utility model, for those of ordinary skill in the art, on the premise of not paying creative work, also
Other accompanying drawings can be obtained according to the accompanying drawing for providing.
A kind of structural representation of array base palte that Fig. 1 a are provided for the embodiment of the present application；
Fig. 1 b are the structural representation in a driving transistor region in Fig. 1 a；
The structural representation of another array base palte that Fig. 2 a are provided for the embodiment of the present application；
Fig. 2 b are the structural representation in a driving transistor region in Fig. 2 a；
A kind of data wire and the structural representation of semiconductor layer that Fig. 3 is provided for the embodiment of the present application；
A kind of structural representation of gate line that Fig. 4 is provided for the embodiment of the present application；
The structural representation of another array base palte that Fig. 5 is provided for the embodiment of the present application；
A kind of structural representation of top gate type array base palte that Fig. 6 is provided for the embodiment of the present application；
A kind of structural representation of bottom gate type array base palte that Fig. 7 is provided for the embodiment of the present application；
A kind of structural representation of display device that Fig. 8 is provided for the embodiment of the present application.
Specific embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the utility model, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment for being obtained, belongs to the scope of the utility model protection.
As described in background, array base palte is one of important composition part of liquid crystal display device, and it includes many
Bar gate line and a plurality of data lines, and gate line and data wire intersect the multiple pixel cells of restriction.Wherein, in each pixel cell
Include a driving transistor and a pixel electrode.In display picture, the conducting of gate line driving transistor, then transistor will
Data wire send signal transmission to pixel electrode, to reach the purpose of display picture.Because driving transistor region can not be entered
Row display, is lightproof area, so the structure design of driving transistor directly affects the aperture opening ratio of pixel cell, therefore to driving
The structure design of transistor is one of main direction of studying of technology today personnel.
Based on this, the embodiment of the present application provides a kind of array base palte and display device, the semiconductor layer of driving transistor
Including bar shaped portion, first connecting portion and the part of second connecting portion three composition, bar shaped portion is arranged at pixel electrode in a first direction
On side, the overlapping region in grid and bar shaped portion is arranged at pixel electrode side in a first direction, to improve picture
The utilization rate of plain electrode both sides in a first direction, and pixel electrode enlarged-area in a second direction can be made, and then lifted
The aperture opening ratio of pixel cell, improves the display effect of display device.To achieve the above object, the technology that the embodiment of the present application is provided
Scheme is as follows, specific to combine shown in Fig. 1 a to Fig. 8, and the technical scheme that the embodiment of the present application is provided is described in detail.
With reference to shown in Fig. 1 a and Fig. 1 b, a kind of structural representation of array base palte that Fig. 1 a are provided for the embodiment of the present application,
Fig. 1 b are the structural representation in a driving transistor region in Fig. 1 a, wherein, array base palte includes：
X is arranged in the first direction multiple columns of pixel electrodes P and a plurality of data lines Data, each data wire Data pairs
Answer columns of pixel electrodes P described in, and data wire Data Y extensions, the first direction X and second direction Y in a second direction
Intersect, the data wire Data is connected by a driving transistor TFT with a pixel electrode Pi in the corresponding columns of pixel electrodes,
Wherein, the driving transistor TFT includes：
Semiconductor layer 100, the semiconductor layer 100 include in a second direction Y extend bar shaped portion 110, described second
The first connecting portion 101 that is connected with the first end in the bar shaped portion 110 on the Y of direction and on the first direction X with the bar
The second connecting portion 102 of the second end connection in shape portion 110；
With the overlapping grid 200 for setting of the bar shaped portion 110 insulation；
And, the first electrode 301 for setting is contacted with the first connecting portion 101, and connect with the second connecting portion 102
The second electrode 302 for setting is touched, wherein, the first electrode connects 301 and meets the data wire Data, and the second electrode 302 connects
Meet the pixel electrode Pi.
In a display device, both sides of the pixel electrode in a first direction on X correspond to alternatively non-transparent region, and the side region can
To design some modular constructions, fully to be utilized to it.So, as shown in the above, what the embodiment of the present application was provided
Technical scheme, the semiconductor layer of driving transistor includes bar shaped portion, first connecting portion and the part of second connecting portion three composition, by bar
Shape portion is arranged at pixel electrode side in a first direction, and the overlapping region in grid and bar shaped portion is arranged at into pixel electrode
Side in a first direction, to improve the utilization rate of pixel electrode both sides in a first direction, and can make pixel electrode exist
Enlarged-area in second direction, and then the aperture opening ratio of pixel cell is lifted, improve the display effect of display device.
In the embodiment of the application one, with specific reference to shown in Fig. 1 a, on the second direction Y, the second connecting portion
102 are located in the columns of pixel electrodes, the region between two neighboring pixel electrode Pi.Additionally, second connecting portion 102 can be with
Be with other regions, this application is not particularly limited, it is necessary to be designed according to practical application.
In the embodiment of the application one, driving transistor TFT can be preferably double channel driving transistor, i.e., with reference to Fig. 1 b
Shown, the grid 200 includes the first overlap that is overlapping with the bar shaped portion 110 insulation and being arranged along the second direction Y
201 and second overlap 202, with the interconnecting part 203 for connecting the overlap 202 of first overlap 201 and second.
Wherein, the interconnecting part 203 that the embodiment of the present application is provided is by the overlap of first overlap 201 and second
202 homonymy one end is connected, wherein, the grid of first overlap 201, the second overlap 202 and interconnecting part 203 composition
200 take the shape of the letter U.Designed using U-shaped, in double-gate structure, the leakage current of driving transistor TFT can be reduced, improve driving transistor
The stability of TFT, lifts display performance.
Further, in order to avoid driving transistor TFT receives illumination effect, and ensure driving transistor TFT conducting and
Blocking capability is stronger, in the embodiment of the application one, a light shield layer can also be set below semiconductor layer.It is specific to combine Fig. 2 a
With shown in Fig. 2 b, the structural representation of another array base palte that Fig. 2 a are provided for the embodiment of the present application, Fig. 2 b are one in Fig. 2 a
The structural representation in driving transistor region, wherein, on the light direction of the array base palte, positioned at the semiconductor layer
100 lower sections are additionally provided with light shield layer 400；
Wherein, the light shield layer 400 is overlapping with the bar shaped portion 110.
In the embodiment of the application one, with reference to shown in Fig. 2 b, when grid is U-shaped grid 200, the covering of light shield layer 400
Region at least include first overlap 201 and the second overlap 202 of grid 200 respectively with the overlapping region in bar shaped portion 110,
And, the region in corresponding bar shaped portion 110 between the first overlap 201 and the second overlap 202 is included, and then avoid driving
The raceway groove of transistor TFT receives illumination effect, it is ensured that the conducting of driving transistor TFT and blocking capability are strong.
In the embodiment of the application one, data wire Data and first electrode 301 can be made by same metal level, be entered
And data wire Data can be multiplexed first electrode 301.With reference to shown in Fig. 3, a kind of data wire for providing for the embodiment of the present application and
The structural representation of semiconductor layer, wherein, the data wire Data is located at same metal level with the first electrode 301, described
Data wire Data is multiplexed the first electrode 301, and the data wire Data on the second direction Y with the bar shaped portion
110 overlapping settings.
It should be noted that in the data wire Data that the embodiment of the present application is provided, its region at first electrode 301
Width can width be identical in itself with data wire Data, can also be more than or less than data wire Data width in itself, to this
Application is not particularly limited, it is necessary to carry out specific design according to practical application.
And, in the embodiment of the application one, gate line can be constituted by being connected with each other between grid 200, with reference to Fig. 4 institutes
Show, be a kind of structural representation of gate line that the embodiment of the present application is provided, wherein, each columns of pixel electrodes is along described
Two direction Y include the first pixel electrode to N pixel electrodes, and N is the integer not less than 1；
Wherein, in all driving transistor TFT that the ith pixel electrode of all columns of pixel electrodes is connected, respectively
The two driving transistor TFT connected with ith pixel electrode described in adjacent two, it is distinguished corresponding grid 200 and is connected with each other, with
Form the i-th gate line of the array base palte, i is the no more than positive integer of N.Wherein, with reference to shown in Fig. 4, two neighboring grid
It is connected by a connecting line 210 between 200, and then forms gate line.
In the embodiment of the application one, when the grid 200 takes the shape of the letter U, the two neighboring of i-th gate line is connected to
The grid 200, the opening of its U-shaped to this embodiment of the present application towards conversely, be not particularly limited, it is necessary to according to practical application
Carry out specific design.Using towards two opposite U-shaped grids, ensureing the distance between the first overlap and the second overlap
While, the link position of the grid of two neighboring driving transistor TFT can also be flexibly controlled, coordinate interlocking for pixel electrode
Arrangement, maximizes and improves aperture opening ratio.
It is the structural representation of another array base palte that the embodiment of the present application is provided with reference to shown in Fig. 5, wherein, it is described
Multiple columns of pixel electrodes are defined as the first columns of pixel electrodes P1 to M columns of pixel electrodes Pm, and each columns of pixel electrodes edge
The second direction Y includes that the first pixel electrode Pi1 to N pixel electrode Pin, N is integer not less than 1, M be not less than
2 integer (wherein, with N be 4, M for 3 are illustrated)；
Wherein, all pixels electrode of the columns of pixel electrodes of all even numbers is arranged in array, the pixel electrode of all odd numbers
The all pixels electrode of row is arranged in array, and the columns of pixel electrodes of the even number ith pixel electrode region, it is and described
The ith pixel electrode region of the columns of pixel electrodes of odd number Heterogeneous Permutation on the second direction Y, i be no more than N just
Integer.As shown in figure 5, the columns of pixel electrodes of odd number exceeds the columns of pixel electrodes of even number, with suitable for SPR (Sub Pixel
Rendering, sub-pixel renders treatment) display device of technology class pixel arrangement, the display resolution of display panel is improved, carry
Rise display effect.
In the embodiment of the application one, the two neighboring grid for being connected to i-th gate line is connected by a connecting line
It is logical；
Wherein, in the two neighboring described connecting line of i-th gate line is connected to, connecting line described in is located at and it
Between the ith pixel electrode and i+1 pixel electrode of corresponding columns of pixel electrodes, another connecting line is certainly corresponding to its
Columns of pixel electrodes the ith pixel electrode region insulation cross.Wherein, with reference to shown in Fig. 5, it is respectively defined as
Two neighboring connecting line is respectively connecting line 211 and connecting line 212 on one direction X, wherein, connecting line 211 is located at the first pixel
Between the first pixel electrode Pi1 and the second pixel electrode Pi2 of electrodes series P1；And, connecting line 212 is from the second columns of pixel electrodes
The first pixel electrode Pi1 regions insulation of P2 is crossed.
In the array base palte that the embodiment of the present application is provided, it can be top gate type array base palte, i.e. driving transistor TFT
It can be top gate type driving transistor；Can also be bottom gate type array base palte, i.e. driving transistor TFT can drive for bottom gate type
Dynamic transistor, is not particularly limited to this application.With specific reference to shown in Fig. 6, for a kind of top-gated that the embodiment of the present application is provided
The structural representation of type array base palte, wherein, the array base palte includes：
Bearing substrate 10；
Positioned at the active layer of the side of the bearing substrate 10, the active layer includes the semiconductor layer 100；
Deviate from the gate insulation layer 20 of the side of the bearing substrate 10 positioned at the active layer；
Deviate from the first metal layer of the side of the bearing substrate 10, the first metal layer bag positioned at the gate insulation layer 20
Include the grid 200；
Deviate from the separation layer 30 of the side of the bearing substrate 10 positioned at the first metal layer；
And, the second metal layer of the side of the bearing substrate 10, second metal are deviated from positioned at the separation layer 30
Layer includes first electrode 301 and second electrode 302, wherein, the first electrode 301 and second electrode 302 pass through via respectively
Be in contact setting with the first connecting portion 101 and second connecting portion 102.
And, also there is another separation layer 40 away from the side of bearing substrate 10 in second metal layer, and positioned at separation layer 40
Away from the side of bearing substrate 10 there is pixel electrode Pi, pixel electrode Pi to be in contact with second electrode 302 connection.
And, it is a kind of structural representation of bottom gate type array base palte that the embodiment of the present application is provided with reference to shown in Fig. 7,
Wherein, the array base palte includes：
Bearing substrate 10；
Positioned at the first metal layer of the side of the bearing substrate 10, the first metal layer includes the grid 200；
Deviate from the gate insulation layer 50 of the side of the bearing substrate 10 positioned at the first metal layer；
Deviate from the active layer of the side of the bearing substrate 10 positioned at the gate insulation layer 50, the active layer includes described half
Conductor layer 100；
Positioned at the active layer away from the side of the bearing substrate 10 second metal layer, the second metal layer includes the
One electrode 301 and second electrode 302, wherein, the first electrode 301 and second electrode 302 respectively with the first connecting portion
101 and second connecting portion 102 be in contact setting.
And, also there is another separation layer 60 away from the side of bearing substrate 10 in second metal layer, and positioned at separation layer 60
Away from the side of bearing substrate 10 there is pixel electrode Pi, pixel electrode Pi to be in contact with second electrode 302 connection.
Accordingly, the embodiment of the present application additionally provides a kind of display device, with specific reference to shown in Fig. 8, be the application implement
A kind of structural representation of display device that example is provided, wherein, the display device includes that there is above-mentioned any one embodiment to carry
The display panel 1000 of the array base palte of confession；
And, when display device is liquid crystal display device, display device also includes providing backlight for display panel 1000
The backlight source module 2000 in source (as shown by arrows).
It should be noted that the application is not particularly limited for the type of display device that provides, such as the application its
In his embodiment, display device can also be organic light-emitting display device.
The embodiment of the present application provides a kind of array base palte and display device, including the multiple pixels for arranging in the first direction
Electrodes series and a plurality of data lines, columns of pixel electrodes described in each data wire correspondence one, and the data wire is in a second direction
Extend, the first direction and second direction are intersected, the data wire is by a driving transistor and the corresponding pixel electrode
A pixel electrode is connected in row, wherein, the driving transistor includes：Semiconductor layer, the semiconductor layer is included along second party
To the bar shaped portion, the first connecting portion that is connected with the first end in the bar shaped portion in this second direction for extending and described the
The second connecting portion connected with second end in the bar shaped portion on one direction；With the overlapping grid for setting of bar shaped portion insulation；
And, the first electrode for setting is contacted with the first connecting portion, and the second electrode for setting is contacted with the second connecting portion,
Wherein, the first electrode connects the data wire, and the second electrode connects the pixel electrode.
As shown in the above, the technical scheme that the embodiment of the present application is provided, the semiconductor layer of driving transistor includes bar
Shape portion, first connecting portion and the part of second connecting portion three composition, in a first direction of pixel electrode is arranged at by bar shaped portion
Side, is arranged at pixel electrode side in a first direction, to improve pixel electrode by the overlapping region in grid and bar shaped portion
The utilization rate of both sides in a first direction, and pixel electrode enlarged-area in a second direction can be made, and then lift pixel list
The aperture opening ratio of unit, improves the display effect of display device.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or new using this practicality
Type.Various modifications to these embodiments will be apparent for those skilled in the art, determine herein
The General Principle of justice can in other embodiments be realized in the case where spirit or scope of the present utility model are not departed from.Cause
This, the utility model is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein
The most wide scope consistent with features of novelty.
Claims (13)
1. a kind of array base palte, including the multiple columns of pixel electrodes and a plurality of data lines for arranging in the first direction, each number
Extend in a second direction according to columns of pixel electrodes described in line correspondence one, and the data wire, the first direction and second direction are handed over
Fork, it is characterised in that the data wire is connected by a driving transistor with a pixel electrode in the corresponding columns of pixel electrodes,
Wherein, the driving transistor includes：
Semiconductor layer, the semiconductor layer include extend in a second direction bar shaped portion, in this second direction with the bar
Shape portion first end connection first connecting portion and connected with second end in the bar shaped portion in said first direction second
Connecting portion；
With the overlapping grid for setting of bar shaped portion insulation；
And, the first electrode for setting is contacted with the first connecting portion, and second for setting is contacted with the second connecting portion
Electrode, wherein, the first electrode connects the data wire, and the second electrode connects the pixel electrode.
2. array base palte according to claim 1, it is characterised in that in this second direction, the second connecting portion
In the columns of pixel electrodes, the region between two neighboring pixel electrode.
3. array base palte according to claim 1, it is characterised in that the grid includes and bar shaped portion insulation is handed over
The first overlap and the second overlap folded and arranged along the second direction, hand over first overlap and second is connected
The interconnecting part in folded portion.
4. array base palte according to claim 3, it is characterised in that the interconnecting part is by first overlap and second
Homonymy one end of overlap is connected, wherein, the grid of first overlap, the second overlap and interconnecting part composition takes the shape of the letter U.
5. array base palte according to claim 3, it is characterised in that on the light direction of the array base palte, be located at
The semiconductor layer lower section is additionally provided with light shield layer；
Wherein, the light shield layer is overlapping with the bar shaped portion.
6. array base palte according to claim 1, it is characterised in that the data wire is located at same with the first electrode
Metal level, the data wire is multiplexed the first electrode, and the data wire is handed over the bar shaped portion in this second direction
It is folded to set.
7. the array base palte according to claim 1~6 any one, it is characterised in that each columns of pixel electrodes edge
The second direction includes the first pixel electrode to N pixel electrodes, and N is the integer not less than 1；
Wherein, in all driving transistors that the ith pixel electrode with all columns of pixel electrodes is connected, respectively with it is adjacent
Two driving transistors of ith pixel electrode connection described in two, its corresponding grid of difference is connected with each other, to form the array
I-th gate line of substrate, i is the no more than positive integer of N.
8. array base palte according to claim 7, it is characterised in that when the grid takes the shape of the letter U, be connected to described i-th
The two neighboring described grid of gate line, the opening of its U-shaped is towards conversely.
9. array base palte according to claim 7, it is characterised in that the multiple columns of pixel electrodes is defined as the first pixel
Electrodes series are to M columns of pixel electrodes, and each columns of pixel electrodes includes the first pixel electrode extremely along the second direction
N pixel electrodes, N is the integer not less than 1, and M is the integer not less than 2；
Wherein, all pixels electrode of the columns of pixel electrodes of all even numbers is arranged in array, the columns of pixel electrodes of all odd numbers
All pixels electrode in array arrange, and the columns of pixel electrodes of the even number ith pixel electrode region, with the odd number
Columns of pixel electrodes ith pixel electrode region Heterogeneous Permutation in this second direction, i is the no more than positive integer of N.
10. array base palte according to claim 9, it is characterised in that be connected to the two neighboring grid of i-th gate line
Pole is connected by a connecting line；
Wherein, in the two neighboring described connecting line of i-th gate line is connected to, connecting line described in is located at corresponding to its
Columns of pixel electrodes the ith pixel electrode and i+1 pixel electrode between, another connecting line is from its corresponding picture
The ith pixel electrode region insulation of plain electrodes series is crossed.
11. array base paltes according to claim 1, it is characterised in that the array base palte includes：
Bearing substrate；
Positioned at the active layer of the bearing substrate side, the active layer includes the semiconductor layer；
Deviate from the gate insulation layer of the bearing substrate side positioned at the active layer；
Deviate from the first metal layer of the bearing substrate side positioned at the gate insulation layer, the first metal layer includes the grid
Pole；
Deviate from the separation layer of the bearing substrate side positioned at the first metal layer；
And, positioned at the separation layer away from the bearing substrate side second metal layer, the second metal layer includes the
One electrode and second electrode, wherein, the first electrode and second electrode are respectively by via and the first connecting portion and the
Two connecting portions are in contact setting.
12. array base paltes according to claim 1, it is characterised in that the array base palte includes：
Bearing substrate；
Positioned at the first metal layer of the bearing substrate side, the first metal layer includes the grid；
Deviate from the gate insulation layer of the bearing substrate side positioned at the first metal layer；
Deviate from the active layer of the bearing substrate side positioned at the gate insulation layer, the active layer includes the semiconductor layer；
Deviate from the second metal layer of the bearing substrate side positioned at the active layer, the second metal layer includes first electrode
And second electrode, wherein, the first electrode and second electrode are in contact with the first connecting portion and second connecting portion respectively
Set.
13. a kind of display devices, it is characterised in that the display device includes the battle array described in claim 1~12 any one
Row substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720003773.4U CN206301128U (en) | 2017-01-03 | 2017-01-03 | A kind of array base palte and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720003773.4U CN206301128U (en) | 2017-01-03 | 2017-01-03 | A kind of array base palte and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206301128U true CN206301128U (en) | 2017-07-04 |
Family
ID=59203790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720003773.4U Active CN206301128U (en) | 2017-01-03 | 2017-01-03 | A kind of array base palte and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206301128U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107845676A (en) * | 2017-10-23 | 2018-03-27 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), array base palte and display device |
-
2017
- 2017-01-03 CN CN201720003773.4U patent/CN206301128U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107845676A (en) * | 2017-10-23 | 2018-03-27 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), array base palte and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104777653B (en) | Array base palte, liquid crystal display panel and liquid crystal display device | |
| CN206619595U (en) | Display panel | |
| CN102314034B (en) | Active element, pixel structure, driving circuit and display panel | |
| CN102402087B (en) | Pixel structure, active element array substrate and flat display panel | |
| CN104699312B (en) | Touch screen display panel and electronic equipment | |
| US11980068B2 (en) | Display panel and display device with multiplexed photosensitive and display region | |
| CN105206219B (en) | Active element array substrate | |
| CN105093606B (en) | Array base palte, liquid crystal display panel and liquid crystal display device | |
| CN206248976U (en) | Array base palte and display device | |
| CN105068344A (en) | Display panel and pixel array thereof | |
| CN105974686A (en) | Array substrate and display panel | |
| CN101697053B (en) | Active component array substrate | |
| CN206074968U (en) | Array base palte and display device | |
| CN106098708A (en) | A kind of thin-film transistor array base-plate, display floater and display device | |
| CN106502474A (en) | A kind of array base palte and display floater | |
| US12039911B2 (en) | Display substrate including a plurality of shift register units | |
| CN208062051U (en) | array substrate and display device | |
| CN108364993A (en) | A kind of production method of display panel, display panel and display device | |
| CN107578700A (en) | Pixel structure | |
| CN111708237B (en) | Array substrate, display panel and display device | |
| CN104698699A (en) | Array substrate, display panel, display device and driving method thereof | |
| CN104614903B (en) | Pixel structure | |
| WO2014023010A1 (en) | Array substrate and liquid crystal display panel | |
| CN206301128U (en) | A kind of array base palte and display device | |
| CN215895193U (en) | Display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |