CN206282225U - Hardware power-down circuit - Google Patents
Hardware power-down circuit Download PDFInfo
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- CN206282225U CN206282225U CN201621140105.8U CN201621140105U CN206282225U CN 206282225 U CN206282225 U CN 206282225U CN 201621140105 U CN201621140105 U CN 201621140105U CN 206282225 U CN206282225 U CN 206282225U
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Abstract
A kind of hardware power-down circuit, the hardware power-down circuit includes：Pulses generation module；Pulse detection module, the pulse detection module is connected to the pulses generation module, for being detected to the pulse signal that pulses generation module is input into, and exports control signal corresponding with the pulse signal；Switch module, the switch module is connected to chip and power supply, for being turned on or off between the control signal control chip and power supply that are exported according to the pulse detection module.Above-mentioned hardware power-down circuit overcomes the integrated machine system cannot to be resetted the problem restarted after collapsing.
Description
Technical field
The utility model is related to intelligent terminal field, more particularly to a kind of hardware power-down circuit.
Background technology
The mobile terminal such as mobile phone, flat board product increasingly incorporates the life of people, and third-party application software uses increasingly frequency
It is numerous, smart mobile phone, flat board run it is third-party installation software or charge when generate heat it is larger, cause machine occur crash it is general
Rate is increasing.Current solution is that user is restarted by the way that battery roll is carried out into system reset, or multiple by software
Realize position.However, because the intelligent artifacts such as mobile phone and flat board are wide in order to improve battery and realize " three prevent "
The general non-removable all-in-one scheme of use battery, so almost cannot realize that system reset is restarted by dismantling battery；And lead to
Crossing the mode of software reset then needs the software and hardware of power management module normally to run, but in whole system software crash
In the case of, such software starts also cannot effectively be realized.So, above two method cannot all make equipment for all-in-one
Timely reset and restart, have a strong impact on the experience of consumer, greatly challenge is also brought after sale to enterprise, seriously increase enterprise
Cost even has influence on enterprise product image.
So, needing a kind of new power-down circuit badly, cannot reset restarting after solving the problems, such as integrated machine system collapse.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of hardware power-down circuit, overcomes integrated machine system to collapse
Cannot reset the problem restarted after bursting.
As described in the background art, all-in-one can neither dismantle battery, cannot also be carried out by software after system crash
Reset, cause all-in-one to reset and restart.The utility model proposes a kind of hardware power-down circuit and hardware power-off method, pass through
The mode of hardware power-off carries out power-off reset, overcomes above mentioned problem.
In order to solve the above problems, the utility model provides a kind of hardware power-down circuit, including：Pulses generation module；
Pulse detection module, the pulse detection module is connected to the pulses generation module, for what is be input into pulses generation module
Pulse signal is detected, and exports control signal corresponding with the pulse signal；Switch module, the switch module connection
To chip and power supply, for the conducting between the control signal control chip and power supply that are exported according to the pulse detection module or
Disconnect.
Optionally, the pulse detection module includes：Timer, the input of the timer is connected to the pulse and produces
Raw module, for when the pulse signal of pulses generation module input is detected, exporting the reference burst signal of fixed pulse width；Compare
Device, the first input end of the comparator is connected to the second input connection of the output end of the timer, the comparator
Output end to the pulses generation module and the comparator is connected to the switch module.
Optionally, the timer includes：Pulse detecting unit, the pulse detecting unit is connected to the pulses generation
Module, for detecting pulse signal, and exports trigger signal when pulse signal is detected；Timing unit, the timing list
Unit is connected to the first input end of the pulse detecting unit and the comparator, for being exported after trigger signal is received
The reference burst signal of fixed pulse width.
Optionally, the pulse detection module also includes phase inverter, and the pulses generation module is connected by the phase inverter
It is connected to the second input of the timer and the comparator.
Optionally, the switch module includes MOS transistor or triode；The pulses generation module includes power supply, connects
It is connected to the key switch of power supply.
The utility model has the advantage of work or closed mode in hardware layer control chip, it is to avoid because system collapses
Burst, cause equipment to restart the problem of reset, in smart machine system crash, can be believed by producing corresponding pulse
Number, control power supply disconnects with chip, closes system cut-off；Power supply is turned on chip again, chip is resumed work, be
System is restarted.
Brief description of the drawings
Fig. 1 is the structural representation of the hardware power-down circuit of the specific embodiment of the utility model one；
Fig. 2 is the structural representation of the hardware power-down circuit of the specific embodiment of the utility model one；
Fig. 3 is the structural representation of the hardware power-down circuit of the specific embodiment of the utility model one；
Fig. 4 is the structural representation of the hardware power-down circuit of the specific embodiment of the utility model one；
Fig. 5 is the structural representation of the timing unit of the hardware power-down circuit of the specific embodiment of the utility model one；
Fig. 6 is the schematic flow sheet of the hardware power-off method of the specific embodiment of the utility model one.
Specific embodiment
The specific embodiment of the hardware power-down circuit for providing the utility model below in conjunction with the accompanying drawings elaborates.
Fig. 1 is refer to, is the hardware power-down circuit schematic diagram of the specific embodiment of the utility model one.
The hardware power-down circuit includes：Pulses generation module 100；Pulse detection module 200, the pulse detection module
200 are connected to the pulses generation module 100, for being detected to the pulse signal that pulses generation module 100 is input into and defeated
Go out control signal corresponding with the pulse signal；Switch module 300, the switch module 300 is connected to chip 400 and power supply
500, for the conducting between the control signal control chip 400 and power supply 500 that are exported according to the pulse detection module 200 or
Disconnect.In the specific embodiment, the power supply 500 is also connected with pulse detection module 200, for giving pulse detection module
200 provide operating voltage；In other specific embodiments of the present utility model, the pulse detection module 200 can also be with
Other power supply modules are connected, to obtain operating voltage.
The pulses generation module 100 is used to produce pulse signal, output to pulse detection module 200, the pulse mode
Block 200 is used for the State- output control signal corresponding with the pulse signal according to the pulse signal for detecting；Switch module 300
For under control of the control signal, the state that is turned on or off being presented, so that the conducting between control chip 400 and power supply 500
Or off-state.When the chip 400 and power supply 500 are turned on, chip 400 is in running order, when chip 400 and power supply
During 500 disconnection, chip 400 is closed.
Work or closed mode of the such scheme in hardware layer control chip 400, it is to avoid because system crash, cause equipment
The problem of reset cannot be restarted, in mobile phone or smart machine system crash, can be produced accordingly by pulses generation module 100
Pulse signal, control power supply 500 disconnected with chip 400, close system cut-off；Power supply 500 is then set to be led with chip 400 again
It is logical, chip 400 is resumed work, system reboot.
Fig. 2 is refer to, in a specific embodiment of the present utility model, the pulse detection module 200 includes：It is fixed
When device 201, the input of the timer 2 01 is connected to the pulses generation module 100, in detection pulses generation module
During the pulse signal of 100 inputs, the reference burst signal of fixed pulse width is exported；Comparator 202, the first of the comparator 202
Input is connected to the output end of the timer 2 02, the second input of the comparator 202 is connected to the pulses generation
The output end of module 100 and the comparator 202 is connected to the switch module 300.
The timer 2 01 exports the reference of fixed pulse width under the pulse signal triggering that pulses generation module 100 is input into
Pulse information, the reference pulse information is determined by the time that timer 2 01 sets.The comparator 202 is used for relatively more described
The pulse signal of the input of pulses generation module 100 and the reference pulse information of the input of timer 2 01, and according to comparative result,
Output control signal, with the open and close state of controlling switch module 300.
Fig. 3 is refer to, the timer 2 01 (refer to Fig. 2) includes：Pulse detecting unit 211, the pulse detection list
Unit 211 is connected to the pulses generation module 100, is touched for detecting pulse signal, and being exported when pulse signal is detected
Signal；Timing unit 212, the timing unit 212 is connected to the pulse detecting unit 211 and the comparator 201
First input end, for after trigger signal is received export fixed pulse width reference burst signal.
The pulses generation module 100 includes power supply 101, is connected to the key switch 102 of working power 101, described to press
Key switch 102 passes through.In this specific embodiment, the key switch 102 is grounded, and the key switch 102 is chip
400 key, can be specifically the starting key of the smart machines such as mobile phone, flat board；Other are specific of the present utility model
In implementation method, the key switch 102 can also be other peripheral hardware buttons of smart machine, such as return key, volume key, lock
Screen key, Home key etc..
Because the key switch 102 is grounded, after the key switch 102 is pressed, a low level pulse can be produced
Signal.
The triggering of the timing unit 212 is designed to pulse and rises triggering, and such benefit can avoid pulse detection list
Judging by accident and start-up circuit occurs when detecting trailing edge in unit 211.So, in the specific embodiment, the pulse detection module 200
Also include phase inverter 203, the pulses generation module 100 is connected to the arteries and veins in the timer 2 01 by the phase inverter 203
The second input of detection unit 211 and the comparator 202 is rushed, for the low level for producing pulses generation module 100
Signal inversion is high level signal, and pulse detecting unit 211 can detect rising edge edge and the decline of the output pulse of phase inverter 203
Edge, and export the pulsewidth of certain hour width and trigger timing unit 212, the timing unit 212 is exported certain pulsewidth
Reference burst signal.
The reference burst signal and pulse signal as comparator 202 two input signals, the comparator 202
After being compared to two signals, corresponding control signal is exported.Timing unit 212 produces a pulse after triggering is received
Width is t2Timing high level signal as reference burst signal, the specific time can be pressed by circuit configuration, key switch
When, output and the pulse width of the time consistency of press of key switch 102 are t after the generation inverted device 203 of low level signal1's
High level t1, t2、t1Compare output control signal through comparator 202, controlling switch module 300 realizes break-make Electricity Functional.If t2>
t1, then the output of comparator 202 low level, switch module 300 turns on, and does not influence intelligent artifact normally to use；If t2<t1, comparator
202 output high level, close switch module 300, then power supply 500 disconnects to the supply access of chip 400, realizes hardware reset
Function.In the specific embodiment, the switch module 300 can be the switch elements such as MOS transistor or triode.
Reset is installed in other specific embodiments of the present utility model, in the smart machine and restarts software,
In the case that system is not collapsed also, after press of key switch certain hour (software reset's time), software is restarted in reset can make intelligence
Energy device powers down is restarted.The pulse width of the reference burst signal of the output of timing unit 212 can be set as more than software reset
Time, so, when within the normal switch machine time, chip 400 carries out normal operation by the software set time, does not influence to use；
When system exception software reset is invalid or cannot restart, for a long time by switching on and shutting down button or other buttons, hardware reset electricity
Road works, system cut-off, eliminates the trouble of unloading battery.
Fig. 4 is refer to, is the circuit realiration schematic diagram of the specific embodiment of the utility model one.
Triode T1 and resistance R2 constitutes phase inverter, and electric capacity C1 and resistance R3 constitutes differential rim detection impulse circuit.Institute
State 555 timers and constitute timing circuit as hardware power-off electric with resistance R4, R5, R7 and electric capacity triode T2, electric capacity C2, C3
The timing unit on road.Because the pulse width of differential detection circuit is restricted, in order that follow-up timing circuit is effectively triggered, use
Its input of triode T2 liftings has the level limit of triggering due to the trigger pulse of 555 timers to the triggering level of 555 timers
System, produces a negative pulse, negative pulse to be unable to reach 555 timers trigger level when differential detection is to drop edge, thus
Pulse-detecting circuit can only detect rising edge pulse signal with 555 timers, and this function avoids switch and produces from low to high
Error detection, improves the stabilization of system.555 timers produce fixed commutator pulse to export a high level signal and are exported with phase inverter
Signal is compared by comparator U2, if phase inverter output pulse width is than the pulse width of 555 timer fixed pulses
High then comparator exports a high level, closes PMOS Q1 pipes, realizes hardware power down function.
Fig. 5 is refer to, is the circuit of the timing unit of the hardware power-down circuit of another specific embodiment of the utility model
Realize figure.
Timing circuit in Fig. 5 can be with the timing unit in alternate figures 4, timing input Vin in circuit can be by
The phase inverter of triode T1 and resistance R2 compositions is produced in Fig. 4.
The operation principle of the timing unit is in two steps：
The first step：Produce a postpones signal.When be input into Vin be low level when, U3, U4 output be respectively high level with it is low
Level.When it is high level to be input into Vin, phase inverter U3, U4 output are respectively low level and high level.When Vin is by step-down high, instead
Phase device U3 outputs are changed into high level from low, and now electric capacity C4 is charged by R10, by charging interval t4U4 is charged to power half
When reach U4 threshold ones become by height, and realize the delay of Vin and Vout by step-down high.Resistance and capacitance can be adjusted, is made
Obtain t4=t2, so pulse width of output is t4Pulse signal Vout and pulse width be t2Pulse signal it is consistent, pass through
Comparator output, controlling switch module below；When Vin is by low uprising, phase inverter U3 is exported by step-down high, due to capacitance voltage
Can not be mutated, diode D3 conductings provide discharge path for C4 electric capacity, diode D3 pipes are Schottky diode, and response is fast,
Electric discharge is very fast, therefore phase inverter U4 inputs are very fast by step-down earial drainage high so that output uprises time delay without delay by low.With
On realize and will be input into by delay on earth high, and do not postpone to low to high, this aspect realizes the function of delay, one
Aspect realizes the function of edge of a pulse detection.
Second step：Extract postpones signal and realize timing function.Phase inverter U4 output delay pulses are coupled to by resistance R11
Triode T3 colelctor electrodes, and original non-delayed pulse input is to T3 base stages, when it is high level to be input into Vin, triode T3 conductings
It is low level that Vout is drawn；When Vin is low level, triode T3 is by Vout keeps high level.When Vin is by step-down high,
Due to postponing t4Reason, the defeated phase inverters of U4 go out in t4Height is remained (namely in delay period) in time period, and now
Vin has had changed into low level, T3 cut-offs, so Vout maintains U4 output waveforms, with pulse width t4, during by postponing
Between after phase inverter U4 outputs Vout be low level, realize pulse-width for t4Postpones signal extraction, due to t4Time
Can adjust and fixed, so as to complete timing t4Function, regulation circuit parameter makes t4=t2, then complete single with timing in Fig. 4
Function as unit.The pulse signal that Vout is exported as the input signal of comparator U2 with phase inverter compares, so as to realize
Hardware power-off restoration function.
Specific embodiment of the present utility model also provides a kind of hardware power-off method.The hardware power-off method, including：
Produce the first pulse signal；First pulse signal is detected, and exports control corresponding with first pulse signal
Signal processed；According to being turned on or off between the control signal control chip and power supply.
Fig. 6 is refer to, is that the hardware in the specific embodiment of the utility model one using above-mentioned hardware power-down circuit is powered off
The schematic flow sheet of method.
Step S1：Produce the first pulse signal.In a specific embodiment, the button of power supply is connected to by pressing
Switch produces the first pulse signal, and the width t1 of first pulse signal is identical with compressing time.In a specific embodiment party
In formula, the key switch ground connection, and the key switch is the key of chip, can be specifically the intelligence such as mobile phone, flat board
The starting key of energy equipment；In other specific embodiments of the present utility model, the key switch can also be that intelligence sets
Other standby peripheral hardware buttons, such as return key, volume key, screen locking key, Home key etc..Due to key switch ground connection, pressing
Under after the key switch, the first pulse signal of generation is low level pulse signal.
Subsequently, first pulse signal is detected, and exports control signal corresponding with the pulse signal, tool
Body includes：
Step S2：Timer is triggered by first pulse signal, one pulse width of output is believed for second pulse of t2
Number.In another specific embodiment of the present utility model, first pulse signal can also be carried out it is anti-phase after, passing through
The rising edging trigger timer of the pulse signal after detection reversely.
Step S3：Compare the pulse width of first pulse signal and the second pulse signal, if t2 ＞ t1, export
One control signal, makes chip be turned on power supply；If t2<T1, exports the second control signal, chip is disconnected with power supply.In this reality
With in a new specific embodiment, by comparator, the pulse to first pulse signal and the second pulse signal
Width is compared, and first control signal is low level, and the second control signal is high level.
Step S4：According to being turned on or off between control signal control chip and power supply.Can be by control signal control
Switch-off and conducting state between coremaking piece and power supply, specifically, the switch can be MOS transistor or three poles
Pipe.
Reset is installed in other specific embodiments of the present utility model, in the smart machine and restarts software,
In the case that system is not collapsed also, after press of key switch certain hour (software reset's time), software is restarted in reset can make intelligence
Energy device powers down is restarted.The pulse width t2 of second pulse signal can be set as more than software reset's time, so,
When in the normal switch machine time, chip carries out normal operation by the software set time, does not influence to use；When system exception software is multiple
When position is invalid or cannot restart, for a long time by switching on and shutting down button or other buttons so that the pulse width of the first pulse signal
T1 is more than the pulse width t2 of the second pulse signal, and hardware reset circuit work, system cut-off eliminates the fiber crops of unloading battery
It is tired.
The above is only preferred embodiment of the present utility model, it is noted that for the common skill of the art
Art personnel, on the premise of the utility model principle is not departed from, can also make some improvements and modifications, these improvements and modifications
Also should be regarded as protection domain of the present utility model.
Claims (4)
1. a kind of hardware power-down circuit, it is characterised in that including：
Pulses generation module；
Pulse detection module, the pulse detection module is connected to the pulses generation module, for defeated to pulses generation module
The pulse signal for entering is detected, and exports control signal corresponding with the pulse signal, and the pulse detection module includes：
Timer and comparator, the input of the timer are connected to the pulses generation module, in detection pulses generation mould
During the pulse signal of block input, the reference burst signal of fixed pulse width is exported, the first input end of the comparator is connected to institute
State the output end of timer, the second input of the comparator and be connected to the pulses generation module and the comparator
Output end be connected to switch module；
Switch module, the switch module is connected to chip and power supply, for the control exported according to the pulse detection module
Being turned on or off between signal control chip and power supply.
2. hardware power-down circuit according to claim 1, it is characterised in that the timer includes：Pulse detecting unit,
The pulse detecting unit is connected to the pulses generation module, for detecting pulse signal, and is detecting pulse signal
When export trigger signal；Timing unit, the timing unit is connected to the of the pulse detecting unit and the comparator
One input, the reference burst signal for exporting fixed pulse width after trigger signal is received.
3. hardware power-down circuit according to claim 1 and 2, it is characterised in that the pulse detection module also includes anti-
Phase device, the pulses generation module is connected to the second input of the timer and the comparator by the phase inverter.
4. hardware power-down circuit according to claim 1, it is characterised in that the switch module include MOS transistor or
Triode；The pulses generation module includes power supply, is connected to the key switch of power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621140105.8U CN206282225U (en) | 2016-10-20 | 2016-10-20 | Hardware power-down circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621140105.8U CN206282225U (en) | 2016-10-20 | 2016-10-20 | Hardware power-down circuit |
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| Publication Number | Publication Date |
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| CN206282225U true CN206282225U (en) | 2017-06-27 |
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ID=59085333
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| CN201621140105.8U Active CN206282225U (en) | 2016-10-20 | 2016-10-20 | Hardware power-down circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112900022A (en) * | 2021-01-15 | 2021-06-04 | 珠海格力电器股份有限公司 | Washing machine drainage structure, washing machine and control method |
-
2016
- 2016-10-20 CN CN201621140105.8U patent/CN206282225U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112900022A (en) * | 2021-01-15 | 2021-06-04 | 珠海格力电器股份有限公司 | Washing machine drainage structure, washing machine and control method |
| CN112900022B (en) * | 2021-01-15 | 2022-03-25 | 珠海格力电器股份有限公司 | Washing machine drainage structure, washing machine and control method |
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