CN206270715U - A kind of universal supervisory circuit plate of radar - Google Patents

Abstract

The utility model is related to a kind of supervisory circuit plate, more particularly to a kind of universal supervisory circuit plate of radar.The utility model includes FPGA module, Communication processing module, switch module and terminal display module, two-way communication link between the FPGA module and radar system, two-way communication link between FPGA module and Communication processing module, pass through switch module two-way communication link between Communication processing module and terminal display module, the switch module connects RJ45 network sockets by netting twine, the EP1C12Q240 chips of altera corp of the model U.S. production of fpga chip, the chip model of Communication processing module is W5300, small volume of the present utility model, it is low in energy consumption, simple structure.

Description

A kind of universal supervisory circuit plate of radar

Technical field

The utility model is related to a kind of supervisory circuit plate, more particularly to a kind of universal supervisory circuit plate of radar.

Background technology

The development of integrated circuit is the revolutionary achievement that microelectric technique development is brought, and integrated circuit is widely used in respectively Individual industry field, the household appliances from needed for daily life utilize integrated circuit extensively invariably to defence and military field.

Generally require to be acquired analog signal and data signal in the monitoring of radar and control, it is of the prior art Supervisory circuit plate is generally acquired using MCU and DSP come the analog signal and data signal to radar system, this monitoring Circuit board generally has the defect that volume is big, power consumption is high, fault rate is high, therefore needs a kind of small volume of proposition, low in energy consumption, structure badly Simple supervisory circuit plate.

Utility model content

The utility model is in order to overcome the above-mentioned deficiencies of the prior art, there is provided a kind of universal supervisory circuit plate of radar, The small volume of this supervisory circuit plate, low in energy consumption, simple structure, reliability are high.

To achieve the above object, the utility model employs following technical measures：

A kind of universal supervisory circuit plate of radar includes FPGA module, Communication processing module, switch module and terminal Display module, two-way communication link between the FPGA module and radar system is double between FPGA module and Communication processing module To communication connection, by switch module two-way communication link between Communication processing module and terminal display module, the exchange Machine module connects RJ45 network sockets by netting twine.

The utility model can also further be realized by following technical measures.

Preferably, the signal output part of the radar system passes sequentially through 422 turns of TTL circuits, the connection of 74245 integrated circuits The signal input part of FPGA module, the signal output part of FPGA module is defeated by the signal of TTL turns of 422 circuits connection radar system Enter end.

Preferably, the FPGA module is fpga chip, and the altera corp of the model U.S. of the fpga chip produces EP1C12Q240 chips.

Preferably, the chip model of the Communication processing module is W5300.

Further, the radar system at least includes that signal processor, radar transmitter, radar receiver, antenna turn Platform, the signal processor, radar transmitter, radar receiver, the antenna rotating platform two-way communication link between FPGA module.

Further, the FPGA module, Communication processing module, switch module, terminal display module, 422 turns of TTL electricity Road, 74245 integrated circuits and TTL turn 422 circuits and are integrated on same circuit board.

The beneficial effects of the utility model are：

1), the utility model includes FPGA module, Communication processing module, switch module and terminal display module, generation Having replaced MCU of the prior art and DSP, fpga chip has numerous I/O mouthfuls, and storage inside data volume is big, fpga chip The EP1C12Q240 chips of altera corp of model U.S. production, the chip model of Communication processing module is W5300, therefore this The small volume of utility model, low in energy consumption, simple structure.

Be worth it is emphasized that：The utility model only protect by above-mentioned physical unit and connect each physical unit it Between the circuit device or physical platform that are constituted, without regard to software section therein.

Brief description of the drawings

Fig. 1 is that circuit of the present utility model constitutes structured flowchart.

Reference implication in figure is as follows：

10-FPGA module, 20-Communication processing, 30-switch module of module

40-terminal display module

Specific embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the utility model, rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made The every other embodiment for being obtained, belongs to the scope of the utility model protection.

As shown in figure 1, a kind of universal supervisory circuit plate of radar includes FPGA module 10, Communication processing module 20, exchanges Machine module 30 and terminal display module 40, two-way communication link between the FPGA module 10 and radar system, FPGA module Two-way communication link between 10 and Communication processing module 20, by exchanging between Communication processing module 20 and terminal display module 40 The two-way communication link of machine module 30, the switch module 30 connects RJ45 network sockets by netting twine.

The signal output part of the radar system passes sequentially through 422 turns of TTL circuits, 74245 integrated circuits connection FPGA moulds The signal input part of block 10, the signal output part of FPGA module 10 turns the signal input that 422 circuits connect radar system by TTL End.

The FPGA module 10 is fpga chip, Al tera companies of the model U.S. production of the fpga chip EP1C12Q240 chips, the chip has numerous I/O mouthfuls, the characteristics of storage inside data volume is big.

The chip model of the Communication processing module 20 is W5300, and W5300 chips are a to realize the integrated of udp protocol Circuit.

The radar system at least includes signal processor, radar transmitter, radar receiver, antenna rotating platform, the letter Number processor, radar transmitter, radar receiver, the antenna rotating platform two-way communication link between FPGA module 10.

The FPGA module 10, Communication processing module 20, switch module 30,40,422 turns of TTL electricity of terminal display module Road, 74245 integrated circuits and TTL turn 422 circuits and are integrated on same circuit board.

The utility model when in use, can coordinate to be used with software of the prior art.With reference to existing Software in technology is described to operation principle of the present utility model, it must be noted that be：Match with the utility model The software of conjunction is not innovative part of the present utility model, nor part of the present utility model.

As shown in figure 1, the signal that antenna rotating platform sends is the running status of antenna, such as antenna rotation rate, antenna electrical work Make the information of the antenna running status of electric current, safety device etc., antenna rotating platform is connected to 422 turns of TTL circuits and carries out level conversion, TTL signal is delivered to the data/address bus of this supervisory circuit plate again, forms data TTL [7..0], and these data are connected to 74245 On the input pin of integrated circuit, parallel data selection is carried out, 74245 integrated circuits export IO [7..0], IO [7..0] connections Onto the FPDP of EP1C12Q240 chips.The signal that EP1C12Q240 chips send to antenna rotating platform carries out differentiation treatment, The signal after treatment is preserved again, the data address of preservation is DD [7..0].

The signal that radar transmitter sends is the working condition of emitter, for example, launch permission, transmission power, transmitting electricity Source, pumping signal etc., are 422 rs 232 serial interface signals, and radar transmitter is connected to 422 turns of TTL circuits and carries out level conversion, TTL signal The data/address bus of this supervisory circuit plate is delivered to again, data TTL [15..8] are formed, and these data are connected to 74245 integrated electricity On the input pin on road, parallel data selection is carried out, 74245 integrated circuits export IO [15..8], and IO [15..8] is connected to On the FPDP of EP1C12Q240 chips.The signal that EP1C12Q240 chips send to radar transmitter carries out differentiation treatment, The signal after treatment is preserved again, the data address of preservation is DD [15..8].

The signal that radar receiver sends is the working condition of receiver, for example intermediate-freuqncy signal, driving source, frequency source, under Frequency variation signal etc., is 422 rs 232 serial interface signals, and radar receiver is connected to 422 turns of TTL circuits and carries out level conversion, and TTL signal is defeated again The data/address bus of this supervisory circuit plate is delivered to, data TTL [23..16] are formed, these data are connected to 74245 integrated circuits Input pin on, carry out parallel data selection, 74245 integrated circuits export IO [23..16], and IO [23..16] is connected to On the FPDP of EP1C12Q240 chips.The signal that EP1C12Q240 chips send to radar receiver carries out differentiation treatment, The signal after treatment is preserved again, the data address of preservation is DD [23..16].

The signal that signal processor sends is the working condition of signal processing system, and such as signal processing system works at present Employed in the feedback information such as clock signal, bearing signal, filtering signal, Echo Processing, be 422 rs 232 serial interface signals, at signal Reason machine is connected to 422 turns of TTL circuits and carries out level conversion, and TTL signal is delivered to the data/address bus of this supervisory circuit plate again, is formed Data TTL [31..24], these data are connected on the input pin of 74245 integrated circuits, carry out parallel data selection, 74245 integrated circuits export IO [31..24], and IO [31..24] is connected on the FPDP of EP1C12Q240 chips. EP1C12Q240 chips carry out differentiation treatment to signal processing system, then preserve the signal after treatment, the data ground of preservation Location is DD [31..24].

The selection of signal processing channel, selection of interior external clock etc., by data bit DATA_OUT of the present utility model [31..24] is realized, fpga chip receives the network data that the transmission of W5300 chips comes, and these data is parsed, step-by-step Decompose, output DATA_OUT [31..24], these data form TTL_OUT [31..24] data by signal driving chip, TTL_OUT [31..24] data are connected to TTL and turn on the input pin of 422 circuits, and TTL turns 422 circuit output 422_1 [31..24] signal, 422_1 [31..24] reconnects control of the receiver realization to signal processing system.

The utility model control signal processor, radar transmitter, radar receiver, the control signal of antenna rotating platform, be Realized by data DATA_IN [7..0], DATA_IN [15..8], DATA_IN [23..16], DATA_IN [31..24], they The data DATA_IN [31..0] of composition 32, these data are transmitted by W5300 chips, and W5300 chips are received from remote The control command data at process control center.Fpga chip carries out data frame analyzing to DATA_IN [31..0], by each subsystem Control protocol, according to one-to-one relation, control, radar transmitter, radar receiver, signal processor.

Claims (6)

1. the universal supervisory circuit plate of a kind of radar, it is characterised in that：Including FPGA module (10), Communication processing module (20), Switch module (30) and terminal display module (40), the FPGA module (10) two-way communication and radar system between connect Connect, two-way communication link between FPGA module (10) and Communication processing module (20), Communication processing module (20) shows with terminal By switch module (30) two-way communication link between module (40), the switch module (30) connects RJ45 by netting twine Network socket.

2. a kind of universal supervisory circuit plate of radar as claimed in claim 1, it is characterised in that：The signal of the radar system Output end passes sequentially through 422 turns of TTL circuits, the signal input part of 74245 integrated circuits connection FPGA module (10), FPGA module (10) signal output part turns the signal input part that 422 circuits connect radar system by TTL.

3. a kind of universal supervisory circuit plate of radar as claimed in claim 2, it is characterised in that：The FPGA module (10) is Fpga chip, the EP1C12Q240 chips of altera corp of the model U.S. production of the fpga chip.

4. a kind of universal supervisory circuit plate of radar as claimed in claim 2, it is characterised in that：The Communication processing module (20) chip model is W5300.

5. a kind of universal supervisory circuit plate of radar as claimed in claim 1, it is characterised in that：The radar system is at least wrapped Signal processor, radar transmitter, radar receiver, antenna rotating platform are included, the signal processor, radar transmitter, radar connect Receipts machine, the antenna rotating platform two-way communication link between FPGA module (10).

6. a kind of universal supervisory circuit plate of radar as claimed in claim 2, it is characterised in that：The FPGA module (10), Communication processing module (20), switch module (30), terminal display module (40), 422 turns of TTL circuits, 74245 integrated circuits with And TTL turns 422 circuits and is integrated on same circuit board.