CN206259939U - A kind of EPON burst-mode receiver signal deteching circuit framework - Google Patents

Abstract

The utility model is related to a kind of EPON burst-mode receiver signal deteching circuit framework.Its circuit architecture includes amplification module, signal amplitude detection module, signal detection judging module, drive module and signal identification module, the utility model in burst-mode receiver limiting amplifier due to increased signal identification module, by the difference for comparing noise and lead code, identify useful signal, the probability that useful signal detection makes a mistake can be greatly reduced, compared with conventional method is by heightening limiting amplifier threshold voltage, receiver sensitivity index will not be reduced；And because signal of the present utility model differentiates carried out in the lead code period, at least only need 2bit durations, therefore high speed optical line terminal burst-mode receiver can be widely used in.

Description

A kind of EPON burst-mode receiver signal deteching circuit framework

Technical field

The utility model is related to information detection, belongs to communication technical field, and in particular to a kind of EPON is dashed forward The detection circuit framework of signalling, can be used for noise, interference and the discriminating of burst detection.

Background technology

The typical uplink of EPON (Passive Optical Network, PON) uses time division multiple acess (Time Division Multiplex Address, TDMA)) mode, as shown in figure 1, multiple ONT Optical Network Terminal (Optical Network Terminator, ONT) optical signal that sends through Optical Distribution Network (Optical Distribution Network, ODN the combining signal after) enters optical line terminal (Optical Line Terminator, OLT), it can be seen that OLT ends receive Machine is operated in burst mode.

The circuit framework of typical OLT ends receiver, as shown in Fig. 2 photodiode is the bursty data light letter for receiving Number it is transformed into photoelectric current, feeding burst mode is across resistance amplifying circuit (BM-TIA), its output feeding burst mode limited range enlargement The input of circuit (BM-LA), BM-LA carries out limited range enlargement to signal, while detection signal (Signal Detect, SD) is It is no effectively, finally, output data and SD signals to clock and data restoring circuit (CDR).

The algorithm of traditional BM-LA signal detections, as shown in figure 3, its principle is the amplitude that detection receives signal, then It is compared with threshold voltage set in advance, when the signal amplitude for detecting is more than threshold value, then output is detected effectively The logic level of signal；If being less than threshold value, return and receive new signal, output holding is not detected by useful signal logic.

The circuit framework of traditional BM-LA signal detections, as shown in figure 4, the signal that BM-LA will be received is first passed around and put Big module (AMP) is amplified, and is then output to signal amplitude detection module (Signal Level Detect), and detection is amplified The amplitude of signal afterwards, and it is compared, comparative result with threshold value set in advance (Siganl Level Seting) (Level Detect) output exports SD signals to outside to signal detection judging module (Signal Detect Decider) Interface；Usual SD can be connected to the JAM pins of BM-LA, to enable output driving (BUF) module.However, due to photodiode The interference in thermal noise, device noise and the external world, can cause under no signal input condition, be received in the input of BM-LA Transient pulse voltage, it is likely that more than threshold voltage, can thus cause that BM-LA under no signal input condition, is detected To the false judgment of useful signal, such error-logic is exported to receiver system, it is likely that cause OLT when TDMA works Occur abnormal.Most applications at present can only heighten the threshold voltage that BM-LA sets to reduce wrong probability of happening, but The sensitivity of whole receiver can be so reduced, the transmission range of optical-fiber network is sacrificed.

Utility model content

Technical problem to be solved in the utility model is to provide a kind of for EPON burst-mode receiver letter Number differentiate circuit framework and method, solve traditional BM-LA detection signals algorithm and circuit framework noise and interference shadow Under sound, signal detection is susceptible to the problem of mistake, reduces the probability that useful signal detection mistake occurs.

The technical scheme that the utility model solves above-mentioned technical problem is as follows：

A kind of EPON burst-mode receiver signal deteching circuit framework, including the inspection of amplification module, signal amplitude Survey module, signal detection judging module and drive module, it is characterised in that also including signal identification module；

The input of the signal amplitude detection module connects the input of the output end and drive module of amplification module respectively End；The output end of the signal amplitude detection module is connected with the input of signal detection judging module；The signal differentiates mould The input of block is connected with the output end of amplification module or is connected with the output end of signal amplitude detection module, and the signal differentiates The output end of module is connected with the input of signal detection judging module.

The beneficial effects of the utility model are：The utility model in burst-mode receiver BM-LA due to increased letter Number identification module, by comparing the difference of noise and lead code, identifies useful signal, significantly reduces useful signal detection The probability for making a mistake, compared with conventional method is by heightening BM-LA threshold voltages, will not reduce receiver sensitivity index； And because signal of the present utility model differentiates carried out in the lead code period, at least only need 2bit durations, therefore can be extensive Apply in high speed OLT burst-mode receivers.

On the basis of above-mentioned technical proposal, the utility model can also do following improvement.

Further, the signal identification module includes integrator, the first trigger, the second trigger, the 3rd trigger, the One delay cell, the second delay cell, comparator, the first OR gate and the second OR gate；

The integrator includes the constant current source, first switch pipe and the electric capacity that are sequentially connected, and in parallel with electric capacity Second switch pipe；

One end, the VTH and VTL of the first switch pipe are connected with three inputs of comparator respectively；

The clock of second trigger is connected along input with one end of first delay cell, the second trigger Triggering input termination logic high, output end connects the input of the first OR gate, and the RESET input connects the second delay cell One end, the output end of the first OR gate connects the other end of the second delay cell and the switch control terminal of second switch pipe simultaneously；

The triggering input connection output end of oppisite phase of first trigger, clock connects first switch simultaneously along input The other end of the switch control terminal of pipe and the first delay cell, the output end of first trigger connects the 3rd trigger Clock is along input；

The triggering input of the 3rd trigger connects the output end of the second OR gate, the input connection of the second OR gate The output end of comparator, another input connects the output end of the 3rd trigger.

Further, the mode of operation of the first switch pipe and second switch pipe is high level conducting, low level shut-off；Institute The first trigger and the second trigger are stated for rising edge clock is triggered, the 3rd trigger is triggered for clock falling edge, described The time that first delay cell is set is 2.0~2.2 times of bit data time, and the time that second delay cell is set is electricity Condenser discharge time, VTH and VTL are the magnitude of voltage related to pulse duty factor set in advance, and the dutycycle upper limit is represented respectively Value and lower limit.

Brief description of the drawings

Fig. 1 is the typical uplink transmission mode of EPON；

Fig. 2 is OLT burst-mode receiver block architecture diagrams；

Fig. 3 is the algorithm flow chart of traditional BM-LA signal detections；

Fig. 4 is the circuit framework of traditional BM-LA signal detections；

Fig. 5 be the utility model proposes BM-LA signal detections algorithm flow chart；

Fig. 6 be the utility model proposes BM-LA signal detections circuit framework block diagram；

Fig. 7 be the utility model proposes signal identification circuit schematic diagram.

Fig. 8 be the utility model proposes signal identification circuit input signal for useful signal timing diagram；

Fig. 9 be the utility model proposes signal identification circuit being made an uproar less than setting value in input signal pulse positive dutycycle The timing diagram of vocal input；

Figure 10 be the utility model proposes signal identification circuit the positive dutycycle of input signal pulse be more than setting value The timing diagram of noise inputs.

Specific embodiment

Principle of the present utility model and feature are described below in conjunction with accompanying drawing, example is served only for explaining this practicality It is new, it is not intended to limit scope of the present utility model.

The utility model is directed to conventional limiting amplifier BM-LA detection signals algorithm and circuit framework, in noise and interference Under the influence of, signal detection is susceptible to the problem of mistake, it is proposed that a kind of for EPON burst-mode receiver letter Number detection circuit framework and method, can greatly reduce useful signal detection mistake occur probability, its realize to noise It is with the Main Basiss that signal is differentiated：It is " 101010... " using the fixed form of PONOLT termination collection of letters lead codes, By comparing the difference of noise and lead code, useful signal is identified.

The utility model proposes a kind of algorithm for EPON burst-mode receiver signal detection, such as Fig. 5 Shown, its principle is the burst amplitude that detection is received, and then it is compared with threshold voltage set in advance, if Less than threshold value, then return and receive new signal, if the signal amplitude for detecting is more than threshold value, carries out next step signal and differentiate inspection Survey；Signal differentiates that pulse positive or negative dutycycle of the detection to signal at the appointed time is measured, if being unsatisfactory for presetting Value, then return and receive new signal, if meeting condition, export the effective burst for detecting.

Based on this principle, the utility model proposes a kind of EPON burst-mode receiver signal detecting method For：

(1) amplification module is amplified to the signal for receiving, and is then output to signal amplitude detection module, drive module And signal identification module；

(2) amplitude of amplification signal of the signal amplitude detection module to receiving detects, and by signal amplitude with it is pre- The threshold value for first setting is compared, if signal amplitude is less than threshold value, returns and receives new signal again, if the signal for detecting Amplitude is more than threshold value, then export the effective breadth signal that detects to signal detection judging module；

(3) signal identification module receives the output for amplifying signal or reception signal amplitude detection module of amplification module output Signal, and the pulse duty factor of the output signal for receiving is detected, if meeting value set in advance, output detects effectively prominent Signal, otherwise, then return and receive new signal；

(4) signal detection judging module, judges for the effective breadth signal and effective burst to receiving, When effective breadth signal and all effective effective burst, the SD useful signals that output is detected；

(5) drive module receives amplification module output signal, and enables signal control with JAM, when JAM is enabled, then will connect The amplifying circuit output signal for receiving enables output, when JAM is not enabled, then by the output clamper of drive circuit.

As shown in fig. 6, the utility model proposes the BM-LA circuit frameworks with signal identification circuit, including amplify mould Block, signal amplitude detection module, signal amplitude detection module and drive module, also including signal identification module；

Amplification module, for being amplified to the signal for receiving, then will amplify signal output to signal amplitude detection Module, drive module and signal identification module；

Signal amplitude detection module, the amplitude for the amplification signal to receiving detects, and by the amplitude with Threshold value set in advance is compared, if signal amplitude is less than threshold value, returns and receives new signal again, if the letter for detecting Number amplitude is more than threshold value, then export the effective breadth signal that detects to signal detection judging module；

Signal identification module, for receiving amplification module output signal or receiving the output letter of signal amplitude detection circuit Number, and the pulse duty factor of signal for receiving is detected, if meeting value set in advance, output detects effective burst To signal detection judging module, otherwise, then return and receive new signal again；

Signal detection judging module, judges for the effective breadth signal and effective burst to receiving, when When effective breadth signal and all effective effective burst, the SD useful signals that output is detected；

Drive module, controls for receiving amplification module output signal, and enabling signal with JAM, when JAM is enabled, then will The amplifying circuit output signal for receiving enables output, when JAM is not enabled, then by the output clamper of drive circuit.

Its course of work is:The signal that BM-LA will be received first passes around amplification module (AMP) and is amplified, then defeated Go out to signal amplitude detection (Signal Level Detect) module, detect the amplitude of amplified signal, and by its with set in advance Fixed threshold value (Siganl Level Seting) is compared, comparative result (Level Detect) output to signal amplitude inspection Slowdown monitoring circuit (Signal Detect Generator)；Signal identification circuit (Signal Discriminator) receives AMP outputs Signal (Path1) receives Signal Level Detect output signals, the pulse duty factor of detection signal, output Valid letters Number to Signal Detect Decider, only when Level Detect and Valid signals are all effective, Signal Detect Decider is just exported and is detected SD signals.

The utility model proposes signal identification circuit schematic diagram, as shown in fig. 7, it is main by integrator INTEGRATOR, the first trigger, the second trigger, the 3rd trigger, the first delay cell DELAY T1, the second delay cell DELAY T2, comparator COMPARE, the first OR gate OR and the second OR gate OR；DIN represents input signal, is input signal The signal exported after amplifying circuit AMP or signal amplitude detection circuit Signal Level Detect amplifies, such as Fig. 6 Middle path1 or path2 are input to the Differential Input of signal identification circuit Signal Discriminator, and RESET is by outside Input or the internal control signal for producing, are an externally input as shown in Figure 6.

Integrator INTEGRATOR includes the constant current source IB, first switch pipe SW1 and the electric capacity CAP that are sequentially connected, with And the second switch pipe SW2 in parallel with electric capacity；

One end, the VTH and VTL of the first switch pipe SW1 are connected with three inputs of comparator COMPARE respectively；

The clock of the second trigger FF2 is connected along input with one end of the first delay cell DELAY T1, The triggering input D of the second trigger FF2 connects logic high, and output end Q connects the input of the first OR gate OR1, resets defeated Enter to hold R to connect one end of the second delay cell DELAY T2, the output end of the first OR gate OR1 connects the second delay cell simultaneously The other end of DELAY T2 and the switch control terminal of second switch pipe SW2；

The triggering input D connection output end of oppisite phase QN of the first trigger FF1, clock connects simultaneously along input CLK Connect the switch control terminal of first switch pipe SW1 and the other end of the first delay cell DELAY T1, the first trigger FF1 Output end Q connect the 3rd trigger FF3 clock along input CLK；

The triggering input D of the 3rd trigger FF3 connects the output end of the second OR gate OR2, the one of the second OR gate OR2 Input end connects the output end of comparator COMPARE, and another input connects the output end Q of the 3rd trigger FF3.

Wherein first switch pipe SW1 and second switch pipe SW2 mode of operations are high level conducting, low level shut-off；FF1、 FF2 is triggered for rising edge clock, and FF3 is triggered for clock falling edge.The time that delay cell DELAY T1 are set is 2.0~2.2 Times bit data time, the time that delay cell DELAY T2 are set is capacitor discharge time, due to SW2 conducting resistance very littles, The time of T2 is generally very short, much smaller than 1bit data durations.VTH and VTL are the electricity related to pulse duty factor set in advance Pressure value, represents dutycycle higher limit and lower limit respectively.Delay cell DELAY T1, DELAY T2 and trigger FF2 composition Function is the signal of T2 to produce a relative signal to postpone T1, and pulse width.

The utility model proposes the signal identification circuit different inputs of correspondence timing diagram respectively as shown in Fig. 8 to Figure 10.

Fig. 8 input signals are the lead code of useful signal, and when positive pulse is arrived, integrator switch SW1 conductings start to electricity Capacity charge, Vintg voltages rise, and VTL is risen above and less than VTH as Vintg, and now comparator output VC is changed into electricity high Flat, when input signal is changed into low level, SW2 shut-offs, Vintg is held off preceding voltage, and VC equally keeps；When FF1 triggers When detecting second positive pulse rising edge, Q1 outputs are changed into low level from high level, and now FF3 triggers are exported to comparator VC carries out sampling output, and SD output signals are changed into high, and expression detects useful signal；Hereafter, because FF3 outputs are anti-by OR Input is fed to, therefore SD will always remain as height, be resetted until RESET signal is changed into high level.

Fig. 9 input signals are noise of the positive dutycycle of pulse less than setting value, because positive pulse duty cycle is short, are caused In the T1 times of regulation, Vintg integral voltages are consistently less than predeterminated voltage lower limit VTL, therefore comparator VC is output as low, FF3 Q1 trailing edges sampling after SD be output as it is low, expression do not detect useful signal；When next positive pulse comes interim, open again Begin to detect.

Figure 10 input signals are noise of the positive dutycycle of pulse more than setting value, because positive pulse duty cycle is long, Vintg Integral voltage can reach between VTL~VTH, therefore comparator VC outputs can be for some time high level；Vintg continues to increase After VTH, VC outputs are changed into low level again, and FF3 SD after the sampling of Q1 trailing edges are output as low, and expression is not detected effectively Signal；Then after the T2 positive pulses of Vsw2 arrive, Vintg can rapidly be discharged into zero level again, when next positive pulse is come Temporarily, detection is restarted.

Preferred embodiment of the present utility model is the foregoing is only, is not used to limit the utility model, it is all in this practicality Within new spirit and principle, any modification, equivalent substitution and improvements made etc. should be included in guarantor of the present utility model Within the scope of shield.

Claims (3)

1. a kind of EPON burst-mode receiver signal deteching circuit framework, including amplification module, signal amplitude detection Module, signal detection judging module and drive module, it is characterised in that also including signal identification module；

The input of the signal amplitude detection module connects the output end of amplification module and the input of drive module respectively；Institute The output end for stating signal amplitude detection module is connected with the input of signal detection judging module；The signal identification module it is defeated Enter end to be connected with the output end of amplification module or be connected with the output end of signal amplitude detection module, the signal identification module Output end is connected with the input of signal detection judging module.

2. EPON burst-mode receiver signal deteching circuit framework according to claim 1, it is characterised in that The signal identification module includes integrator, the first trigger, the second trigger, the 3rd trigger, the first delay cell, second Delay cell, comparator, the first OR gate and the second OR gate；

The integrator includes the constant current source, first switch pipe and the electric capacity that are sequentially connected, and in parallel with electric capacity second Switching tube；

One end, the VTH and VTL of the first switch pipe are connected with three inputs of comparator respectively；

The clock of second trigger is connected along input with one end of first delay cell, the triggering of the second trigger Input termination logic high, output end connects the input of the first OR gate, and the RESET input connects the one of the second delay cell End, the output end of the first OR gate connects the other end of the second delay cell and the switch control terminal of second switch pipe simultaneously；

The triggering input connection output end of oppisite phase of first trigger, clock connects first switch pipe simultaneously along input The other end of switch control terminal and the first delay cell, the output end of first trigger connects the clock of the 3rd trigger Along input；

The triggering input of the 3rd trigger connects the output end of the second OR gate, and the input connection of the second OR gate is compared The output end of device, another input connects the output end of the 3rd trigger.

3. EPON burst-mode receiver signal deteching circuit framework according to claim 2, it is characterised in that The mode of operation of the first switch pipe and second switch pipe is high level conducting, low level shut-off；

First trigger and the second trigger are rising edge clock triggering, and the 3rd trigger is touched for clock falling edge Hair, the time that first delay cell is set is 2.0~2.2 times of bit data time, second delay cell set when Between be capacitor discharge time, VTH and VTL is the magnitude of voltage related to pulse duty factor set in advance, and duty is represented respectively Than higher limit and lower limit.