CN206149389U - Image sensor and ramp signal generating device thereof - Google Patents
Image sensor and ramp signal generating device thereof Download PDFInfo
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- CN206149389U CN206149389U CN201620945082.1U CN201620945082U CN206149389U CN 206149389 U CN206149389 U CN 206149389U CN 201620945082 U CN201620945082 U CN 201620945082U CN 206149389 U CN206149389 U CN 206149389U
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Abstract
The utility model discloses an image sensor and ramp signal generating device thereof, the device includes: the ramp signal output, the current unit array, the load array, the control unit for control current cellular array output slope current signal, and then through load array output slope voltage signal, wherein, every current unit in the current unit array includes the current mirror, first selection transistor, the second choice transistor, the control end of current mirror provides the unit with the offset voltage who provides offset voltage and links to each other, the first end of current mirror with preset the power and link to each other, the first end of first selection transistor links to each other with the second end of current mirror, not the second termination ground of first selection transistor, the first end of second choice transistor links to each other with the second of current mirror end, the second end of second choice transistor links to each other with the ramp signal output. From this, the electric current of current unit output is more accurate, more stable, and slope voltage signal's voltage burr is littleer, makes ramp signal's the linearity better.
Description
Technical field
This utility model is related to image sensor technologies field, more particularly to a kind of ramp signal for imageing sensor
Generating meanss, and a kind of imageing sensor with the device.
Background technology
Ramp signal generating meanss in correlation technique, are generally opened one by one come defeated by the output switch in control electric current source
Go out an electric current for gradually increasing, then export the voltage for gradually increasing through load array.But, its problem for existing
It is that the output current of current source is forbidden, is easily biased the impact of voltage and supply voltage, and output switch switching (conducting/close
It is disconnected) when output current burr it is very big, and then cause burr during change in voltage also very big.
Therefore, correlation technique needs to be improved.
Utility model content
This utility model is intended at least to solve to a certain extent one of technical problem in correlation technique.For this purpose, this reality
It is to propose a kind of ramp signal generating meanss for imageing sensor with a new purpose, the electric current of the device is more accurate
More stable, ramp voltage burr is less.
Another purpose of the present utility model is to propose a kind of imageing sensor.
To reach above-mentioned purpose, on the one hand this utility model proposes a kind of ramp signal for imageing sensor occurs
Device, including：Ramp signal outfan, for exporting ramp voltage signal；Current unit array, the current unit array
Outfan is connected with the ramp signal outfan；Load array, the load array respectively with the current unit array
Outfan is connected with the ramp signal outfan；Control unit, described control unit is connected with the current unit array, institute
Control unit is stated for controlling the current unit array output ramping current signal, wherein, the ramping current signal is passed through
The load array transformation is the ramp voltage signal；Wherein, the current unit array includes multiple current units, each
Current unit includes current mirror, first choice transistor, the second selection transistor, control end and the offer biasing of the current mirror
The bias voltage of voltage provides unit and is connected, and the first end of the current mirror is connected with default power supply, the first choice crystal
The first end of pipe is connected with the second end of the current mirror, the second end ground connection of the first choice transistor, second choosing
Select the first end of transistor to be connected with the second end of the current mirror, the second end and the slope of second selection transistor
Signal output part is connected.
According to the utility model proposes the ramp signal generating meanss for imageing sensor, each current unit adopts
Constructed with current mirror, first choice transistor and the second selection transistor, the control end of current mirror is inclined with offer bias voltage
Put voltage providing unit to be connected, the first end of current mirror is connected with default power supply, the first end and electric current of first choice transistor
Second end of mirror is connected, the second end ground connection of first choice transistor, and the of the first end of the second selection transistor and current mirror
Two ends are connected, and the second end of the second selection transistor is connected with ramp signal outfan.Thus, electric current can be caused by current mirror
The electric current of unit output is more accurate, more stable, and first choice transistor turns and second are controlled when not needing electric current to export
Selection transistor closes the current direction ground so that current mirror offer, and first choice crystal is controlled when needing electric current to export
Pipe is closed and the second selection transistor is turned on, and so as to the electric current that whole process current mirror is provided is constant, and ramp signal can be made defeated
The voltage glitch for going out the ramp voltage signal of end output is less, makes the linearity of ramp signal more preferable.
Specifically, the bias voltage provides unit with the first biased electrical pressure side and the second biased electrical pressure side, the electricity
Stream mirror includes：First biasing transistor, the first end of the first biasing transistor is connected with the default power supply, and described first
The control end of biasing transistor is connected with the first biased electrical pressure side；Second biasing transistor, the second biasing transistor
First end with described first biasing transistor the second end be connected, it is described second bias transistor the second end respectively with it is described
The first end of first choice transistor is connected with the first end of second selection transistor, the control of the second biasing transistor
End processed is connected with the second biased electrical pressure side.
Further, each current unit also includes：Latch, the latch is connected to described control unit and correspondence
First choice transistor and the second selection transistor between, the control signal receiving terminal of the latch and described control unit
It is connected to receive the control signal of described control unit output, the first outfan of the latch and the first choice crystal
The control end of pipe is connected, and the second outfan of the latch is connected with the control end of second selection transistor；Wherein, institute
Latch is stated for carrying out signal latch according to the control signal, so that the second selection transistor constant conduction and described
First choice transistor is persistently turned off.
Specifically, the latch includes：First latching component, the first end of first latching component and the second end phase
Preset power supply described in Lian Houyu to be connected；Second latching component, the first end of second latching component and the first latch group
3rd end of part is connected and with primary nodal point, the second end of second latching component and the 4th of first latching component
End is connected and with secondary nodal point, and the 3rd end of second latching component is grounded after being connected with the 4th end；First column selection crystal
Pipe, the control end of the first column selection transistor is connected with described control unit, the first end of the first column selection transistor and
The primary nodal point is also connected after being connected with the control end of the first choice transistor；Second column selection transistor, described second
The control end of column selection transistor is connected with described control unit, first end and the secondary nodal point of the second column selection transistor
Also it is connected with the control end of second selection transistor after being connected；Row selects transistor, the row select the control end of transistor with
Described control unit is connected, the row select the first end of transistor respectively with the second end of the first column selection transistor and described
Second end of the second column selection transistor is connected, and the row selects the second end of transistor to be grounded.
Specifically, the latch also includes：First enables transistor, and described first enables the control end of transistor and institute
State control unit to be connected, the first end of the first enable transistor is connected with the primary nodal point, and described first enables crystal
The second end ground connection of pipe；Second enables transistor, and the control end of the second enable transistor is connected with described control unit, institute
The first end for stating the second enable transistor is connected with the secondary nodal point, and described second enables the second end ground connection of transistor.
Specifically, first latching component includes：The first transistor and transistor seconds, the of the first transistor
Used as the first end of first latching component, the first end of the transistor seconds is used as first latching component for one end
Second end, the control end of the transistor seconds be connected with the second end of the first transistor after as the first latch group
3rd end of part, the control end of the first transistor is locked after being connected with the second end of the transistor seconds as described first
Deposit the 4th end of component.
Specifically, second latching component includes：Third transistor and the 4th transistor, the control of the 4th transistor
End processed be connected with the first end of the third transistor after as second latching component first end, the third transistor
Control end be connected with the first end of the 4th transistor after as second latching component the second end, described is trimorphism
Used as the 3rd end of second latching component, the second end of the 4th transistor is used as the described second lock at second end of body pipe
Deposit the 4th end of component.
Specifically, the current unit array includes N × M current unit, and the N × M current unit constitutes N row M
The array of row, wherein, the row of latch selects the control end of transistor to link together in the M current unit per a line, each
The control end of the first column selection transistor of latch links together in N number of current unit of row, the N number of current unit per string
The control end of the second column selection transistor of middle latch links together.
To reach above-mentioned purpose, on the other hand this utility model proposes a kind of imageing sensor, including described is used for
The ramp signal generating meanss of imageing sensor.
According to the utility model proposes imageing sensor, believed by slope of the above-described embodiment for imageing sensor
Number generating meanss, can lift the performance of imageing sensor.
Description of the drawings
Fig. 1 is that the square frame of the ramp signal generating meanss for imageing sensor according to this utility model embodiment is illustrated
Figure；
Fig. 2 is electric current in ramp signal generating meanss for imageing sensor according to this utility model one embodiment
The circuit theory diagrams of unit；
Fig. 3 is the work of the ramp signal generating meanss for imageing sensor according to this utility model one embodiment
Time diagram；
Fig. 4 is electricity in ramp signal generating meanss for imageing sensor according to another embodiment of this utility model
The circuit theory diagrams of stream unit；
Fig. 5 is the ramp signal generating meanss for imageing sensor according to one specific embodiment of this utility model
Block diagram；
Fig. 6 is the working timing figure of Fig. 5；
Fig. 7 is the curve synoptic diagram of the current ramp signal according to this utility model one embodiment；And
Fig. 8 is the curve synoptic diagram of the voltage ramp signal according to this utility model one embodiment.
Specific embodiment
Embodiment of the present utility model is described below in detail, the example of the embodiment is shown in the drawings, wherein ad initio
Same or similar element is represented to same or similar label eventually or the element with same or like function.Below by ginseng
The embodiment for examining Description of Drawings is exemplary, it is intended to for explaining this utility model, and it is not intended that to this utility model
Restriction.
Below with reference to the accompanying drawings the ramp signal for imageing sensor to describe the proposition of this utility model embodiment occurs
Device and the imageing sensor with it.
Fig. 1 is that the square frame of the ramp signal generating meanss for imageing sensor according to this utility model embodiment is illustrated
Figure.As shown in figure 1, the ramp signal generating meanss for imageing sensor include：Ramp signal outfan Vramp, electric current list
Element array 10, load array 20 and control unit 30.
Wherein, ramp signal outfan Vramp is used to export ramp voltage signal；The outfan of current unit array 10 with
Ramp signal outfan Vramp is connected；Load array 20 is exported respectively with the outfan and ramp signal of current unit array 10
End Vramp is connected；Control unit 30 is connected with current unit array 10, and it is defeated that control unit 30 is used for control electric current cell array 10
Go out ramping current signal, wherein, ramping current signal is transformed to ramp voltage signal, i.e. control unit 30 through load array 20
By being controlled such that ramp signal outfan Vramp exports ramp voltage signal to current unit array 10.
Wherein, current unit array 10 includes multiple current units 101, as shown in Fig. 2 each current unit 101 includes
The control end of current mirror I1, first choice transistor ST1 and the second selection transistor ST2, current mirror I1 and offer bias voltage
Bias voltage provide unit 102 be connected, the first end of current mirror I1 is connected with default power supply VCC, first choice transistor ST1
First end be connected with second end of current mirror I1, second end of first choice transistor ST1 ground connection GND, second selects crystal
The first end of pipe ST2 is connected with second end of current mirror I1, the second end and the ramp signal outfan of the second selection transistor ST2
Vramp is connected.
Specifically, control unit 30 can be by controlling the turn-on and turn-off of first choice transistor ST1 come control electric current
Mirror I1 output electric current stream to ground, or by control the second selection transistor ST2 turn-on and turn-off come control electric current mirror I1
The electric current of output is exported from ramp signal outfan Vramp.
As shown in figure 3, the course of work of current unit 101 is as follows：
Within the t1 time periods, the exportable low level of control unit 30 to first choice transistor ST1 is controlling first choice
Transistor ST1 is turned on, and exports high level to the second selection transistor ST2 to control the second selection transistor ST2 shut-offs, now
The electric current stream of current mirror I1 outputs to, the output voltage of ramp signal outfan Vramp do not increase；
Within the t2 time periods, the exportable high level of control unit 30 to first choice transistor ST1 is controlling first choice
Transistor ST1 is turned off, and exports low level to the second selection transistor ST2 to control the second selection transistor ST2 conductings, now
The output voltage of the current direction ramp signal outfan Vramp of current mirror I1 outputs, ramp signal outfan Vramp increases,
The equivalent resistance for for example loading array 20 is R, and the electric current of current mirror I1 outputs is i, then ramp signal outfan Vramp's is defeated
Going out voltage increases i × R.
Thus, by control electric current flow direction ground, the voltage glitch of ramp signal outfan Vramp can be made less.
Specifically, as shown in Fig. 2 bias voltage provides unit 102 has the first biased electrical pressure side PVB1 and the second biasing
Voltage end PVB2, current mirror I1 includes：First biasing transistor BT1 and the second biasing transistor BT2.
Wherein, the first end of the first biasing transistor BT1 is connected with default power supply VCC, the control of the first biasing transistor BT1
End processed is that grid is connected with the first biased electrical pressure side PVB1；The first end of the second biasing transistor BT2 and the first biasing transistor
Second end of BT1 is connected, second end of the second biasing transistor BT2 respectively with the first end of first choice transistor ST1 and the
The first end of two selection transistor ST2 is connected, the control end and the second biased electrical pressure side PVB2 phase of the second biasing transistor BT2
Even.
That is, the first biased electrical pressure side PVB1 provides the first bias voltage for the first biasing transistor BT1, second is inclined
Put voltage end PVB2 and provide the second bias voltage for the second biasing transistor BT2, image current is more accurate, more stable.
Further, as shown in figure 4, each current unit 101 also includes：Latch 103, latch 103 is connected to control
Between unit processed 30 and corresponding first choice transistor ST1 and the second selection transistor ST2, the control signal of latch 103
Receiving terminal be connected with control unit 30 with reception control unit 30 export control signal, the first outfan of latch 103 with
The control end of first choice transistor ST1 is connected, the control of the second outfan of latch 103 and the second selection transistor ST2
End is connected；Wherein, latch 103 is used to carry out signal latch according to control signal, so that the second selection transistor ST2 persistently leads
Logical and first choice transistor ST1 is persistently turned off.
Specifically, as shown in figure 4, latch 103 includes：First latching component 1031, the second latching component 1032, first
Column selection transistor CT1, the second column selection transistor CT2 and row select transistor R1.
Wherein, the first end of the first latching component 1031 and the second end are connected after being connected with default power supply VCC；Second latches
The first end of component 1032 is connected and with primary nodal point with the 3rd end of the first latching component 1031, the second latching component 1032
The second end be connected with the 4th end of the first latching component 1031 and with secondary nodal point, the 3rd end of the second latching component 1032
It is grounded after being connected with the 4th end；The control end of the first column selection transistor CT1 and the first column selection signal output part of control unit 30
Coln be connected, the first end of the first column selection transistor CT1 be connected with primary nodal point after also with the control of first choice transistor ST1
End is connected；The control end of the second column selection transistor CT2 is connected with the second column selection signal output part col of control unit 30, and second
The first end of column selection transistor CT2 is also connected after being connected with secondary nodal point with the control end of the second selection transistor ST2；Row choosing is brilliant
The control end of body pipe RT1 is connected with the row selects signal outfan Row-En of control unit 30, and row selects the first end point of transistor RT1
It is not connected with second end of the first column selection transistor CT1 and second end of the second column selection transistor CT1, row selects transistor RT1's
Second end is grounded.
Specifically, as shown in figure 4, the first latching component 1031 includes：The first transistor T1 and transistor seconds T2.
Wherein, the first end of the first transistor T1 as the first latching component 1031 first end, transistor seconds T1's
First end as the first latching component 1031 the second end, the control end of transistor seconds T2 and second end of the first transistor T1
As the 3rd end of the first latching component 1031, the control end of the first transistor T1 and second end of transistor seconds T2 after being connected
As the 4th end of the first latching component 1031 after being connected.
Also, as shown in figure 4, the second latching component 1032 includes：Third transistor T3 and the 4th transistor T4.
Wherein, as the second latching component after the control end of the 4th transistor T4 is connected with the first end of third transistor T3
1032 first end, the control end of third transistor T3 be connected with the first end of the 4th transistor T4 after as the second latching component
1032 the second end, the second end of third transistor T3 as the second latching component 1032 the 3rd end, the 4th transistor T4's
Fourth end of second end as the second latching component 1032.
Specifically, control unit 30 can be (such as high by the effective row selects signal of row selects signal outfan Row-En outputs
Level), effective row selects signal can make row select transistor RT1 to turn on, if now control unit 30 is defeated by the first column selection signal
Go out to hold coln output low levels to control the first column selection transistor CT1 shut-offs, and exported by the second column selection signal output part col
To control the second column selection transistor CT2 conductings, then secondary nodal point is pulled low to low level, the second selection transistor ST2 to high level
Conducting, current direction ramp signal outfan Vramp, and by the first latching component 1031 and the second latching component 1032 by the
The level catch of two nodes is in low level；If control unit 30 by the first column selection signal output part coln export high level with
The first column selection transistor CT1 conductings are controlled, and exports low level to control the second column selection by the second column selection signal output part col
Transistor CT2 is turned off, then primary nodal point is pulled low to low level, first choice transistor ST1 conductings, current direction ground.
When control unit 30 exports invalid row selects signal (such as low level) by row selects signal outfan Row-En, row choosing
Transistor RT1 is turned off, and now no matter the first column selection signal output part coln and the second column selection signal output part col exports any letter
Number, the state of first choice transistor ST1 and the second selection transistor ST2 keeps constant.
It should be noted that the signal of the first column selection signal output part coln and the second column selection signal output part col outputs
It is complementary, i.e. the first column selection signal output part coln is low level, the second column selection signal output part col is high level, and the
One column selection signal output part coln is high level, and the second column selection signal output part col is low level.
It should be appreciated that the ramp signal of ramp signal outfan Vramp outputs can be that positive slope (is stepped up
), or negative slope (progressively reducing), positive slope and negative slope can be by adjusting the first column selection signal output part
The level state of coln and the second column selection signal output part col is realizing.
Further, as shown in figure 4, latch 103 also includes：First enables transistor ET1 and second enables transistor
ET2。
Wherein, the control end of the first enable transistor ET1 is connected with the first enable control end ENP of control unit 30, the
The first end of one enable transistor ET1 is connected with primary nodal point, and first enables the second end ground connection of transistor ET1；Second enables
The control end of transistor ET2 is connected with the second enable control end ENN of control unit 30, and second enables the first of transistor ET2
End is connected with secondary nodal point, and second enables the second end ground connection of transistor.
Specifically, control unit 30 can enable control end ENP output first and effectively enable signal by first, and first has
Effect enables signal turns on can the first enable transistor ET1, and then makes primary nodal point for low level, and the low level can make the first choosing
Select transistor ST1 conductings, the current direction ground of current source I1 outputs.
It should be appreciated that effectively enabling the first choice crystal that signal controls each current unit 101 by first
When pipe ST1 is turned on, the electric current of each current unit 101 flows to ground, and the output voltage of ramp signal outfan Vramp is pulled to
Minimum point.
In addition, control unit 30 can enable control end ENN output second by second effectively enables signal, it is oblique with what is arranged
The initial voltage of slope signal output part Vramp.
As described above, the control signal receiving terminal of latch 103 may include it is defeated with the first column selection signal of control unit 30
Go out to hold the control end of the first connected column selection transistor CT1 of coln and the second column selection signal output part col phases of control unit 30
The row choosing that the control end of the second column selection transistor CT2 even is connected with the row selects signal outfan Row-En of control unit 30 is brilliant
The control of the first enable transistor ET1 that the control end of body pipe RT1 is connected with the first enable control end ENP of control unit 30
End and the control end of the second enable transistor ET2 being connected with the second enable control end ENN of control unit 30.
A specific embodiment of the invention, as shown in figure 5, current unit array 10 may include N × M electric current list
101, N of unit × M current unit 101 constitutes the array of N rows M row, wherein, the row of latch in the M current unit per a line
The control end for selecting transistor RT1 links together, the first column selection transistor CT1 of latch in the N number of current unit per string
Control end link together, per string N number of current unit in latch the second column selection transistor CT1 control end connection
Together.Wherein, M, N are positive integer, and N can be equal with M.
That is, as shown in figure 5, the row of latch selects the control end of transistor RT1 in M current unit of the first row
With the first row of control unit 30 signal output part Row-En-1 can be selected to be connected, and so on, M current unit of Nth row
The row of middle latch selects the control end of transistor RT1 that signal output part Row-En-N phases can be selected with the Nth row of control unit 30
Even；The control end of the first enable transistor ET1 of latch can with the of control unit 30 in M current unit of the first row
One first enables control end ENP-1 and is connected, and so on, the first enable crystal of latch in M current unit of Nth row
The control end of pipe ET1 can enable control end ENP-N and be connected with the n-th first of control unit 30；M electric current list of the first row
The control end of the second enable transistor ET2 of latch can enable control end with first second of control unit 30 in unit
ENN-1 is connected, and so on, the control end of the second enable transistor ET2 of latch can be equal in M current unit of Nth row
Control end ENN-N is enabled with the n-th second of control unit 30 to be connected.
The control end of the second column selection transistor CT2 of latch can and control unit in N number of current unit of first row
30 first the second column selection signal output part col-1 is connected, and so on, the of latch in N number of current unit of m column
The control end of two column selection transistor CT2 can be connected with m-th the second column selection signal output part col-M of control unit 30, its
In, because the second column selection signal output part col and the first column selection signal output part coln is complementary signal, only with the second column selection signal
Describe as a example by outfan col.
Specifically, by taking Fig. 6 as an example, the work schedule of current unit array 10 can be as follows：
First, control unit 30 can enable control end ENP (including first first enable control end ENP-1 by first
Control end ENP-N is enabled to n-th first) effectively to enable signal be high level for output first, so that each current unit 101
Electric current all flows to ground, and the voltage of ramp signal outfan Vramp is pulled to minimum point GND.
Then, control unit 30 selects signal output part Row-En-1 to select signal output part Row- to Nth row by the first row
En-M produces the row selects signal of thermometer code formula, so that current unit array 10 is turned on line by line.In current unit array 10, often row is led
When logical, control unit 30 can be by first the second column selection signal output part col-1 to m-th the second column selection signal output part
Col-M produces column selection signal, so that the gating by column of the string string of current unit array 10, until last string, so repeats.
In other words, control unit 30 can the first row of first control electric current cell array 10 gate by column, then control electric current
Second row of cell array 10 is gated by column, by that analogy.Total output current of ramp signal outfan Vramp gradually increases,
As shown in fig. 7, each step electric current incrementss are the electric current i of current unit output, and finally, the electricity of ramp signal outfan Vramp
Pressure is also to be stepped up, as shown in figure 8, the electric current i × load array 20 of each step voltage increase Δ V=current units output
Effective resistance R.
More specifically, as shown in fig. 6, control unit 30 can select signal output part Row-En-1 outputs to have by the first row
Effect row selects signal is high level, and effective row selects signal can make row in the first row current unit select transistor RT1 to be both turned on, now,
Control unit 30 can by first the second column selection signal output part col-1 to m-th the second column selection signal output part col-M according to
The effective column selection signal of secondary output is high level, to control the electric current list of the current unit of the first row first row to the first row m column
Unit gates by column, and the voltage for making ramp signal outfan Vramp is stepped up.
After M current unit of the first row is gated, control unit 30 can pass through the second row selects signal outfan
It is high level that Row-En-2 exports effective row selects signal, and effective row selects signal can make row in the second row current unit select transistor
RT1 is both turned on, and now, control unit 30 can be believed by first the second column selection signal output part col-1 to the column selection of m-th second
Number outfan col-M is sequentially output effective column selection signal i.e. high level, to control the current unit of the second row first row to second
The current unit of row m column is also gated by column, makes the voltage of ramp signal outfan Vramp in M current unit of the first row
It is stepped up on the basis of when gating.And so on, until each current unit in current unit array 10 is gated.
To sum up, the ramp signal generating meanss for imageing sensor for being proposed according to this utility model embodiment, each
Current unit is using current mirror, first choice transistor and the second selection transistor construction, control end and the offer of current mirror
The bias voltage of bias voltage provides unit and is connected, and the first end of current mirror is connected with default power supply, first choice transistor
First end is connected with the second end of current mirror, the second end ground connection of first choice transistor, the first end of the second selection transistor
It is connected with the second end of current mirror, the second end of the second selection transistor is connected with ramp signal outfan.Thus, by common source
The current mirror of pole and grid can cause the electric current that current unit is exported more accurate, more stable, and not need electric current output time control
First choice transistor turns processed and the second selection transistor are closed so that the current direction ground that provides of current mirror, and is needing
Control first choice transistor is closed and the second selection transistor is turned on when electric current is exported, so as to the offer of whole process current mirror
Electric current is constant, and the voltage glitch of the ramp voltage signal of ramp signal outfan output can be made less, makes the line of ramp signal
Property degree is more preferable.
Finally, this utility model embodiment also proposed a kind of imageing sensor, including above-described embodiment for image
The ramp signal generating meanss of sensor.
According to the imageing sensor that this utility model embodiment is proposed, by above-described embodiment for imageing sensor
Ramp signal generating meanss, can lift the performance of imageing sensor.
In description of the present utility model, it is to be understood that term " " center ", " longitudinal direction ", " horizontal ", " length ", " width
Degree ", " thickness ", " on ", D score, "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom " " interior ", " outward ", " suitable
The orientation or position relationship of the instruction such as hour hands ", " counterclockwise ", " axial direction ", " radial direction ", " circumference " is based on orientation shown in the drawings
Or position relationship, be for only for ease of description this utility model and simplify description, rather than indicate or imply indication device or
Element must have specific orientation, with specific azimuth configuration and operation, therefore it is not intended that to limit of the present utility model
System.
Additionally, term " first ", " second " are only used for describing purpose, and it is not intended that indicating or implying relative importance
Or the implicit quantity for indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can express or
Implicitly include at least one this feature.In description of the present utility model, " multiple " are meant that at least two, such as two
It is individual, three etc., unless otherwise expressly limited specifically.
In this utility model, unless otherwise clearly defined and limited, term " installation ", " connected ", " connection ", " Gu
It is fixed " etc. term should be interpreted broadly, it is for example, it may be fixedly connected, or be detachably connected or integral；Can be
It is mechanically connected, or electrically connects；Can be joined directly together, it is also possible to be indirectly connected to by intermediary, can be two
The connection of element internal or the interaction relationship of two elements, unless otherwise clearly restriction.For the common skill of this area
For art personnel, concrete meaning of the above-mentioned term in this utility model can be as the case may be understood.
In this utility model, unless otherwise clearly defined and limited, fisrt feature second feature " on " or D score
Can be the first and second feature directly contacts, or the first and second features are by intermediary mediate contact.And, first is special
Levy second feature " on ", " top " and " above " but fisrt feature directly over second feature or oblique upper, or only
Represent that fisrt feature level height is higher than second feature.Fisrt feature second feature " under ", " lower section " and " below " can be with
Be fisrt feature immediately below second feature or obliquely downward, or be merely representative of fisrt feature level height less than second feature.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means to combine specific features, structure, material or spy that the embodiment or example are described
Point is contained at least one embodiment of the present utility model or example.In this manual, to the schematic table of above-mentioned term
State and be necessarily directed to identical embodiment or example.And, the specific features of description, structure, material or feature can be with
Combine in an appropriate manner in any one or more embodiments or example.Additionally, in the case of not conflicting, this area
Technical staff the feature of the different embodiments or example described in this specification and different embodiment or example can be entered
Row is combined and combined.
Although embodiment of the present utility model has been shown and described above, it is to be understood that above-described embodiment is
Exemplary, it is impossible to it is interpreted as to restriction of the present utility model, one of ordinary skill in the art is in scope of the present utility model
It is interior above-described embodiment to be changed, be changed, being replaced and modification.
Claims (9)
1. a kind of ramp signal generating meanss for imageing sensor, it is characterised in that include：
Ramp signal outfan, for exporting ramp voltage signal；
Current unit array, the outfan of the current unit array is connected with the ramp signal outfan；
Load array, the load array respectively with the outfan and the ramp signal outfan phase of the current unit array
Even；
Control unit, described control unit is connected with the current unit array, and described control unit is used to control the electric current
Cell array exports ramping current signal, wherein, the ramping current signal is the slope through the load array transformation
Voltage signal；
Wherein, the current unit array includes multiple current units, and each current unit includes current mirror, first choice crystal
Pipe, the second selection transistor, the control end of the current mirror provides unit and is connected with the bias voltage for providing bias voltage, described
The first end of current mirror is connected with default power supply, the first end of the first choice transistor and the second end phase of the current mirror
Even, the second end ground connection of the first choice transistor, the of the first end of second selection transistor and the current mirror
Two ends are connected, and the second end of second selection transistor is connected with the ramp signal outfan.
2. ramp signal generating meanss for imageing sensor according to claim 1, it is characterised in that the biasing
Voltage providing unit has the first biased electrical pressure side and the second biased electrical pressure side, and the current mirror includes：
First biasing transistor, the first end of the first biasing transistor is connected with the default power supply, first biasing
The control end of transistor is connected with the first biased electrical pressure side；
Second biasing transistor, described second biases the first end of transistor and the second end phase of the described first biasing transistor
Even, the second end of the second biasing transistor selects brilliant with the first end of the first choice transistor and described second respectively
The first end of body pipe is connected, and the control end of the second biasing transistor is connected with the second biased electrical pressure side.
3. ramp signal generating meanss for imageing sensor according to claim 1 and 2, it is characterised in that each
Current unit also includes：
Latch, the latch is connected to described control unit and corresponding first choice transistor and the second selection transistor
Between, the control signal receiving terminal of the latch is connected to receive the control of described control unit output with described control unit
Signal, the first outfan of the latch is connected with the control end of the first choice transistor, and the second of the latch
Outfan is connected with the control end of second selection transistor；
Wherein, the latch is used to carry out signal latch according to the control signal, so that second selection transistor is held
Continue conducting and the first choice transistor is persistently turned off.
4. ramp signal generating meanss for imageing sensor according to claim 3, it is characterised in that the latch
Device includes：
First latching component, the first end of first latching component and the second end are connected after being connected with the default power supply；
Second latching component, the first end of second latching component is connected and has with the 3rd end of first latching component
Primary nodal point, the second end of second latching component is connected and with second section with the 4th end of first latching component
Point, the 3rd end of second latching component is grounded after being connected with the 4th end；
First column selection transistor, the control end of the first column selection transistor is connected with described control unit, first column selection
The first end of transistor is also connected after being connected with the primary nodal point with the control end of the first choice transistor；
Second column selection transistor, the control end of the second column selection transistor is connected with described control unit, second column selection
The first end of transistor is also connected after being connected with the secondary nodal point with the control end of second selection transistor；
Row selects transistor, the row to select the control end of transistor to be connected with described control unit, and the row selects the first of transistor
End is connected respectively with the second end of the first column selection transistor and the second end of the second column selection transistor, and the row choosing is brilliant
The second end ground connection of body pipe.
5. ramp signal generating meanss for imageing sensor according to claim 4, it is characterised in that the latch
Device also includes：
First enables transistor, and the control end of the first enable transistor is connected with described control unit, and described first enables
The first end of transistor is connected with the primary nodal point, and described first enables the second end ground connection of transistor；
Second enables transistor, and the control end of the second enable transistor is connected with described control unit, and described second enables
The first end of transistor is connected with the secondary nodal point, and described second enables the second end ground connection of transistor.
6. ramp signal generating meanss for imageing sensor according to claim 4, it is characterised in that described first
Latching component includes：
The first transistor and transistor seconds, the first end of the first transistor is used as the first of first latching component
End, the first end of the transistor seconds as first latching component the second end, the control end of the transistor seconds
As the 3rd end of first latching component, the control of the first transistor after being connected with the second end of the first transistor
End processed be connected with the second end of the transistor seconds after as first latching component the 4th end.
7. ramp signal generating meanss for imageing sensor according to claim 4, it is characterised in that described second
Latching component includes：
Third transistor and the 4th transistor, the control end of the 4th transistor is connected with the first end of the third transistor
Afterwards as the first end of second latching component, the first end of the control end of the third transistor and the 4th transistor
As the second end of second latching component after being connected, the second end of the third transistor is used as second latching component
The 3rd end, the 4th end of the second end of the 4th transistor as second latching component.
8. ramp signal generating meanss for imageing sensor according to claim 4, it is characterised in that the electric current
Cell array includes N × M current unit, and the N × M current unit constitutes the array of N rows M row, wherein, the M per a line
The row of latch selects the control end of transistor to link together in individual current unit, latch in the N number of current unit per string
The control end of the first column selection transistor link together, the second column selection crystal of latch in the N number of current unit per string
The control end of pipe links together.
9. a kind of imageing sensor, it is characterised in that include according to any one of claim 1-8 for image sensing
The ramp signal generating meanss of device.
Priority Applications (1)
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| CN201620945082.1U CN206149389U (en) | 2016-08-25 | 2016-08-25 | Image sensor and ramp signal generating device thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620945082.1U CN206149389U (en) | 2016-08-25 | 2016-08-25 | Image sensor and ramp signal generating device thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109040630A (en) * | 2017-06-08 | 2018-12-18 | 三星电子株式会社 | The ramp signal generator of imaging sensor and imaging sensor including it |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109040630A (en) * | 2017-06-08 | 2018-12-18 | 三星电子株式会社 | The ramp signal generator of imaging sensor and imaging sensor including it |
| CN109040630B (en) * | 2017-06-08 | 2021-04-27 | 三星电子株式会社 | Ramp signal generator of image sensor and image sensor including the same |
| US10987421B2 (en) | 2017-06-08 | 2021-04-27 | Samsung Electronics Co., Ltd. | Ramp signal generator of image sensor, and image sensor including same |
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