CN206115985U - Shift register unit, shift register ware, gate drive circuit, display device - Google Patents
Shift register unit, shift register ware, gate drive circuit, display device Download PDFInfo
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- CN206115985U CN206115985U CN201621194863.8U CN201621194863U CN206115985U CN 206115985 U CN206115985 U CN 206115985U CN 201621194863 U CN201621194863 U CN 201621194863U CN 206115985 U CN206115985 U CN 206115985U
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Abstract
The utility model provides a shift register unit, the shift register unit includes signal input part, signal output part, low level signal end, input module, pull -up module, drop -down module and drop -down control module, the shift register unit still includes voltage stabilizing module, the shift register unit still includes voltage stabilizing module, voltage stabilizing module connects drop -down control module's input with between the low level signal end, voltage stabilizing module can the output stage of shift register unit will drop -down control module's input with low level signal end switches on, just voltage stabilizing module allows to follow drop -down control module's input extremely the unidirectional flux of low level signal end. The utility model provides a shift register, a gate drive circuit, a display device. At the output stage, the control end voltage fluctuation of the drop -down module of shift register unit is little to can ensure normally closing of grid line.
Description
Technical Field
The utility model relates to a display device field specifically relates to a shift register unit, one kind including this shift register unit shift register, including this shift register's gate drive circuit and including this gate drive circuit's display device.
Background
The grid driving circuit of the display device comprises a shift register, and the shift register comprises cascaded shift register units. After the output of the shift register unit is finished, the pull-up node and the signal output end of the shift register unit need to be subjected to discharge reset.
In the pull-down stage, the low level voltage output by the control end of the pull-down control module to the pull-down module is easily affected by the pull-down output of the display area, and the voltage of the control end of the pull-down module is unstable, so that the normal turn-off of the grid line is affected.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a shift register unit, one kind include this shift register unit's shift register, including this shift register's gate drive circuit and including this gate drive circuit's display device. The voltage of a pull-down node of the shift register unit is stable in a pull-down stage, and the grid line can be ensured to be normally closed.
In order to achieve the above object, the present invention provides a shift register unit, which comprises a signal input terminal, a signal output terminal, a low level signal terminal, an input module, a pull-up module, a pull-down module and a pull-down control module;
the input end of the input module is connected with the signal input end, and the output end of the input module is connected with the control end of the pull-up module;
the output end of the pull-up module is connected with the signal output end, and the pull-up module can conduct the input end of the pull-up module with the output end of the pull-up module when the control end of the pull-up module receives a high level signal;
the input end of the pull-down module is connected with the low level signal end, the output end of the pull-down module is connected with the signal output end, and the pull-down module can conduct the input end of the pull-down module and the output end of the pull-down module when the control end of the pull-down module receives a high level signal;
the output end of the pull-down control module is connected with the control end of the pull-down module, the input end of the pull-down control module is connected with the control end of the pull-up module, and the pull-down control module is used for outputting a low level signal to the control end of the pull-down module in the output stage of the shift registering unit and outputting a high level signal to the control end of the pull-down module in the pull-down stage of the shift registering unit; wherein,
the shift registering unit further comprises a voltage stabilizing module, the voltage stabilizing module is connected between the input end of the pull-down control module and the low level signal end, the voltage stabilizing module can conduct the input end of the pull-down control module and the low level signal end in the output stage of the shift registering unit, and the voltage stabilizing module can allow unidirectional conduction of the low level signal end from the input terminal of the pull-down control module.
Preferably, the shift registering unit includes a reset module and a reset terminal, the reset terminal is connected to the control terminal of the reset module, the voltage stabilizing module includes a voltage stabilizing transistor, a first pole of the voltage stabilizing transistor is connected to the low level signal terminal and a first input terminal of the reset module, a second pole and a gate of the voltage stabilizing transistor are connected to a second input terminal of the reset module and to an input terminal of the pull-down control module, a first output terminal of the reset module is connected to the signal output terminal, and a second output terminal of the reset module is connected to the control terminal of the pull-up module.
Preferably, the width-to-length ratio of the regulator transistor is greater than or equal to 2.
Preferably, the reset module comprises a first reset transistor and a second reset transistor, a first pole of the first reset transistor is formed as a first output end of the reset module, a second pole of the first reset transistor is formed as a first input end of the reset module, and a gate of the first reset transistor is formed as a control end of the reset module;
the grid electrode of the second reset transistor is connected with the grid electrode of the first reset transistor, the first pole of the second reset transistor is formed as the second output end of the reset module, and the second pole of the second reset transistor is formed as the second input end of the reset module.
Preferably, the input module comprises an input transistor, a gate of the input transistor is connected with a first pole to form an input end of the input module, and a second pole of the input transistor is formed as an output end of the input module.
Preferably, the input module further includes a filter transistor, a first pole of the filter transistor is connected to the first pole of the input transistor, a second pole of the filter transistor is connected to the second pole of the input transistor, and a gate of the filter transistor is connected to the first clock signal terminal.
Preferably, the pull-up module includes a pull-up transistor and a memory cell, a gate of the pull-up transistor is formed as a control terminal of the pull-up transistor, a first pole of the pull-up transistor is connected to a second clock signal terminal, a second pole of the pull-up transistor is connected to the signal output terminal, one end of the memory cell is connected to the gate of the pull-up transistor, and the other end of the memory cell is connected to the second pole of the pull-up transistor.
Preferably, the pull-down module comprises a first pull-down transistor and a second pull-down transistor;
a gate of the first pull-down transistor is formed as a control terminal of the pull-down module, a first pole of the first pull-down transistor is formed as an output terminal of the pull-down module, and a second pole of the first pull-down transistor is formed as an input terminal of the pull-down module;
the grid electrode of the second pull-down transistor is connected with the grid electrode of the first pull-down transistor, the first pole of the second pull-down transistor is connected with the control end of the pull-up module, and the second pole of the second pull-down transistor is connected with the input end of the pull-down control module.
Preferably, the pull-down module further includes a third pull-down transistor, a gate of the third pull-down transistor is connected to the first clock signal terminal, a first pole of the third pull-down transistor is connected to the first pole of the first pull-down transistor, and a second pole of the third pull-down transistor is connected to the input terminal of the pull-down control module.
Preferably, the pull-down control module includes a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, and a fourth pull-down control transistor,
the grid electrode of the first pull-down control transistor is connected with a first clock signal end, the first pole of the first pull-down control transistor is connected with the grid electrode of the first pull-down control transistor, and the second pole of the first pull-down control transistor is connected with the first pole of the fourth pull-down control transistor;
the grid electrode of the second pull-down control transistor is connected with the second pole of the first pull-down control transistor, the first pole of the second pull-down control transistor is connected with the first pole of the first pull-down control transistor, and the second pole of the second pull-down control transistor is connected with the control end of the pull-down module;
the grid electrode of the third pull-down control transistor is connected with the control end of the pull-up module, and the second pole of the third pull-down control transistor is connected with the second pole of the fourth pull-down control transistor and forms the input end of the pull-down control module;
and the grid electrode of the fourth pull-down control transistor is connected with the grid electrode of the third pull-down control transistor, and the first pole of the fourth pull-down control transistor is connected with the control end of the pull-down module.
As another aspect of the present invention, a shift register is provided, which includes cascaded multi-stage shift register units, wherein at least one of the shift register units is the above shift register unit provided by the present invention.
As a further aspect of the present invention, a gate driving circuit is provided, the gate driving circuit includes a shift register, wherein the shift register is the present invention provides an above shift register.
As another aspect of the present invention, there is provided a display device, which includes a gate driving circuit, wherein the gate driving circuit is the above gate driving circuit provided by the present invention.
Because the voltage stabilizing module is connected between the low level signal input end and the pull-down control module, when the voltage of the low level signal input end rises, the voltage stabilizing module disconnects the low level signal end from the input end of the pull-down control module, and the voltage in one end of the voltage stabilizing module, which is connected with the input end of the pull-down control module, is maintained at the low level signal before the low level signal input end is pulled high, so that the voltage fluctuation of the control end of the pull-down module can be prevented, the input end and the output end of the pull-down module are ensured to be conducted, the grid line is ensured to be normally turned off, and the display effect of the display device comprising the shift register.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a block diagram of a shift register unit according to the present invention;
fig. 2 is a circuit structure diagram of the shift register unit provided by the present invention;
fig. 3 is a signal timing diagram of the shift register unit according to the present invention.
Description of the reference numerals
100: the input module 200: pull-up module
300: the pull-down module 400: pull-down control module
500: the reset module 600: voltage stabilizing module
Detailed Description
The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings. It is to be understood that the description of the embodiments herein is for purposes of illustration and explanation only and is not intended to limit the invention.
The utility model provides a unit is deposited IN aversion, as shown IN FIG. 1, the unit is deposited IN the aversion includes signal input part IN, signal output part OUT, low level signal end Vss, first clock signal end CLK1, input module 100, pull-up module 200, pull-down module 300, pull-down control module 400 and voltage stabilizing module 600.
The input terminal of the input module 100 is connected to the signal input terminal IN, and the output terminal of the input module 100 is connected to the control terminal PU of the pull-up module 200.
The output end of the pull-up module 200 is connected to the signal output end OUT, and the pull-up module 200 can conduct the input end of the pull-up module with the output end of the pull-up module when the control end of the pull-up module 200 receives a high level signal.
The input terminal of the pull-down block 300 is connected to the low level signal terminal Vss, and the output terminal of the pull-down block 300 is connected to the signal output terminal OUT. The pull-down module 300 is capable of turning on the input terminal of the pull-down module 300 and the output terminal of the pull-down module 300 when the control terminal of the pull-down module 300 receives a high level signal.
The output terminal of the pull-down control module 400 is connected to the control terminal of the pull-down module 300, and the pull-down control module 140 is configured to output a low level signal to the control terminal of the pull-down module 300 during the output stage of the shift register unit, and output a high level signal to the control terminal of the pull-down module 300 during the pull-down stage of the shift register unit.
The voltage stabilizing module 600 is connected between the input terminal of the pull-down control module 400 and the low level signal terminal Vss, the voltage stabilizing module 600 can conduct the input terminal of the pull-down control module 400 and the low level signal terminal Vss at the output stage of the shift register unit, and the voltage stabilizing module 600 allows unidirectional conduction from the input terminal of the pull-down control module 400 to the low level signal terminal. The unidirectional conduction here means that the current is allowed to flow from the input terminal of the pull-down control module 400 to the low-level signal terminal Vss, but the current is not allowed to flow from the low-level signal terminal to the input terminal of the pull-down control module 400.
As shown in FIG. 3, the duty cycle of the shift register unit includes an input stage T1, an output stage T2, and a pull-down stage T3.
IN the input stage t1, the signal input terminal IN receives a high-level signal, and charges the control terminal PU of the pull-up module 200 through the input module 100.
In the output stage t2, the input terminal of the pull-up module 200 is turned on with the signal output terminal OUT, and in this stage, the pull-up stage 200 inputs a high level signal, which is output to the output terminal OUT. At this stage, the pull-down control module 400 outputs a low level signal to the control terminal of the pull-down module 300, so as to ensure that the input terminal and the output terminal of the pull-down module 300 are disconnected.
In the output stage t3, the pull-down control module 400 outputs a high signal to the control terminal of the pull-down module 300, so as to turn on the input terminal and the output terminal of the pull-down module 300 to discharge the signal output terminal OUT.
Since the voltage at the signal output terminal OUT is gradually decreased during the discharging stage, the level of the low level signal input terminal Vss is pulled high.
Because the voltage stabilizing module 600 is connected between the low level signal input terminal Vss and the pull-down control module 400, and the voltage stabilizing module only allows the unidirectional conduction from the input terminal of the pull-down module to the low level signal terminal, therefore, in the output stage, the low level voltage Vss can be raised to the high level signal instantly along with the output, and due to the unidirectional conduction function of the voltage stabilizing module 600, the signal that the low level signal terminal Vss is pulled to the high level can not be transmitted to the control terminal PD of the pull-down module 300, thereby preventing the voltage fluctuation of the control terminal PD of the pull-down module 300, ensuring the conduction of the input terminal and the output terminal of the pull-down module 300, and ensuring the normal turn-off of the gate line, which is beneficial to improving the display effect of.
In addition, the voltage stabilizing module 600 can store the power to ensure that the voltage of the terminal of the voltage stabilizing module 600 connected to the pull-down module 300 is maintained at a low level signal.
Therefore, the voltage stabilizing module 600 is configured to ensure that both a sufficiently low signal is output and the output voltage level of the pull-down module 300 is stable.
In the present invention, the specific structure of the voltage regulator module 600 is not limited, for example, the voltage regulator module 600 may be a diode, the anode of the diode is connected to the input terminal of the pull-down control module 400, and the cathode of the diode is connected to the low level signal terminal.
As a preferred embodiment, the shift register unit shown in fig. 2 includes a Reset module 500 and a Reset terminal Reset, the Reset terminal Reset being connected to the control terminal of the Reset module 500, in this embodiment, the voltage regulation module 600 includes a voltage regulation transistor M13, a first pole of the voltage regulation transistor M13 is connected to the low level signal terminal Vss and the first input terminal of the Reset module 500, a second pole and a gate of the voltage regulation transistor M13 are connected to the second input terminal of the Reset module 500 and the input terminal of the pull-down control module 400. A first output terminal of the reset module 500 is connected to the signal output terminal OUT, and a second output terminal of the reset module 500 is connected to the control terminal of the pull-up module 200.
The gate of the zener transistor M13 is connected to the first pole, forming a diode connection. When the voltage of the first pole of the voltage stabilizing transistor M13 rises, the voltage stabilizing transistor M13 forms diode connection, prevents the signal from flowing backwards, and ensures that the voltage of the second pole of the voltage stabilizing transistor M13 is not changed.
The larger the width-to-length ratio of the transistor, the smaller the resistance. In the present invention, in order to reduce the power consumption of the regulator module 600, it is preferable that the width-to-length ratio of the regulator transistor M13 is greater than or equal to 2.
The utility model discloses in, there is not special restriction to the concrete structure of module 600 that resets, as long as can reset at the control end that draws down terminal pair signal output OUT and pull-up module 200 can. In the embodiment shown in fig. 2, the reset module 200 includes a first reset transistor M3 and a second reset transistor M9. A first pole of the first Reset transistor M3 is formed as a first output terminal of the Reset block and is connected to the signal output terminal OUT, a second pole of the first Reset transistor M3 is formed as a first input terminal of the Reset block and is connected to the low-level signal terminal Vss, and a gate of the first Reset transistor M3 is formed as a control terminal of the Reset block and is connected to the Reset terminal Reset.
The gate of the second reset transistor M9 is connected to the gate of the first reset transistor M3, the first pole of the second reset transistor M9 is formed as the second output terminal of the reset module 500 and connected to the control terminal PU of the pull-up module 200, and the second pole of the second reset transistor M9 is formed as the second input terminal of the reset module 500 and connected to the second pole of the voltage regulator transistor M13.
The Reset terminal Reset is used for receiving a Reset signal, and when the Reset signal is valid at the output terminal of the shift register unit, the first Reset transistor M3 and the second Reset transistor M9 are both turned on. Since the voltage across the regulator transistor M13 is maintained at a lower level, the control terminal of the pull-up module 200 and the signal output terminal OUT can be reset well.
In the present invention, the specific structure of the input module 100 is not particularly limited. IN the preferred embodiment shown IN fig. 2, the input module 100 comprises an input transistor M8, the gate and first pole of the input transistor M8 forming an input terminal of the input module 100 connected to the signal input terminal IN, and the second pole of the input transistor M8 forming an output terminal of the input module 100 connected to the control terminal 200 of the pull-up module 200. When the signal input terminal IN inputs a high level signal, the input transistor M8 is turned on, thereby charging the control terminal of the pull-up module 200.
To better charge the control terminal PU of the pull-up module 200, the input module 100 further preferably includes a filter transistor M10, a first pole of the filter transistor M10 is connected to the first pole of the input transistor M8, a second pole of the filter transistor M10 is connected to the second pole of the input transistor M8, and a gate of the filter transistor M10 is connected to the first clock signal CLK1 terminal.
As shown IN fig. 3, IN the input stage, the first clock signal terminal CLK1 inputs a high level signal, and thus, the pull-up transistor M8 and the filter transistor M110 are turned on, so that the input signal can charge the control terminal of the pull-up module 200 from the signal input terminal IN.
In the output stage, the signal inputted from the first clock signal terminal CLK1 is a low level signal, the input transistor M8 is turned off, and the filter transistor M10 is also turned off.
IN the pull-down phase, the signal inputted from the first clock signal terminal CLK1 is a high level signal, so that the filter transistor M10 is turned on, and the low level signal inputted from the signal input terminal IN is discharged to the control terminal PU of the pull-up module 200.
In the present invention, there is no particular limitation on the specific structure of the pull-up module 200, and in the embodiment shown in fig. 2, the pull-up module 200 includes a pull-up transistor M4 and a storage unit C. The gate of pull-up transistor M4 is formed as the control terminal of pull-up transistor M4, the first pole of pull-up transistor M4 is connected to the second clock signal terminal CLK2, the second pole of pull-up transistor M4 is connected to the signal output terminal OUT, one end of memory cell C is connected to the gate of pull-up transistor M4, and the other end of memory cell C is connected to the second pole of pull-up transistor M4.
A first terminal of pull-up transistor M4 is an input terminal of pull-up module 200, and a second terminal of pull-up transistor M4 is an output terminal of pull-up module 200. In the input phase t1, the input module 100 charges the storage unit C. At output stage T2, the bootstrap action of the storage capacitor C couples the gate of pull-up transistor M4 to a higher potential, thereby turning on pull-up transistor M4. At this time, the second clock signal terminal CLK2 inputs a high level signal, so that a high level signal can be output from the signal output terminal OUT.
The memory cell C may be a storage capacitor.
In the embodiment shown in fig. 2, the pull-down module 300 includes a first pull-down transistor M2 and a second pull-down transistor M7.
The gate of the first pull-down transistor M2 is formed as a control terminal of the pull-down module 300 and is connected to the output terminal of the pull-down control module 400, the first pole of the first pull-down transistor M2 is formed as an output terminal of the pull-down module 300 and is connected to the signal output terminal OUT, and the second pole of the first pull-down transistor M2 is formed as an input terminal of the pull-down module 300 and is connected to the low-level signal input terminal Vss.
Preferably, the pull-down module further includes a third pull-down transistor M1, a gate of the third pull-down transistor M1 is connected to the first clock signal terminal CLK, a first pole of the third pull-down transistor M1 is connected to the first pole of the first pull-down transistor M2, and a second pole of the third pull-down transistor M1 is connected to the input terminal of the pull-down control module 400.
The gate of the second pull-down transistor M7 is connected to the gate of the first pull-down transistor M2, the first pole of the second pull-down transistor M7 is connected to the control terminal of the pull-up module 200, and the second pole of the second pull-down transistor M7 is connected to the input terminal of the pull-down control module 400.
The pull-down module 300 including the first pull-down transistor M2 and the second pull-down transistor M7 is capable of simultaneously pulling down the control terminal of the pull-up module 200 and the signal output terminal OUT during the output phase.
In the embodiment shown in fig. 2, the pull-down control module 400 includes a first pull-down control transistor M11, a second pull-down control transistor M12, a third pull-down control transistor M5, and a fourth pull-down control transistor M6.
The gate of the first pull-down control transistor M11 is connected to the first clock signal terminal CLK1, the first pole of the first pull-down control transistor M11 is connected to the gate of the first pull-down control transistor M11, and the second pole of the first pull-down control transistor M11 is connected to the first pole of the fourth pull-down control transistor M5.
The gate of the second pull-down control transistor M12 is connected to the second pole of the first pull-down control transistor M11, the first pole of the second pull-down control transistor M12 is connected to the first pole of the first pull-down control transistor M11, and the second pole of the second pull-down control transistor M12 is connected to the control terminal PD of the pull-down module 300.
The gate of the third pull-down control transistor M5 is connected to the control terminal of the pull-up module 200, and the second pole of the third pull-down control transistor M5 is connected to the second pole of the fourth pull-down control transistor M6, and is formed as an input terminal of the pull-down control module 400, which is connected to one terminal of the regulator module 600.
The gate of the fourth pull-down control transistor M6 is connected to the gate of the third pull-down control transistor M5, and the first pole of the fourth pull-down control transistor M6 is connected to the control terminal PD of the pull-down module 300.
The operation of the shift register unit shown in fig. 2 will be described in detail with reference to fig. 2 and 3.
At the input stage t1, the first clock signal is a high signal, the second clock signal is a low signal, and the input signal is a high signal. The input transistor M8 and the filter transistor M10 are turned on, the memory cell C of the pull-up module 200 is charged, the pull-up transistor M4 is turned on, and the second clock signal is at a low level, so the signal output terminal OUT of the shift register unit outputs a low level at the input stage t 1. At the same time, the first pull-down control transistor M11 is turned on, so that the second pull-down control transistor M12 is turned on, the third pull-down control transistor M5 and the fourth pull-down control transistor M6 are turned on, the voltage stabilizing transistor M13 is turned on, so that a low level signal is output to the control terminal of the pull-down module 300, and the first pull-down transistor M2 and the second pull-down transistor M7 are both turned off. The third pull-down transistor M1 is turned on to turn on the signal output terminal OUT and the low level signal terminal Vss, further ensuring that the signal output terminal OUT outputs a low level signal.
In the output stage t2, the input signal is a low level signal, the memory cell C is bootstrapped, the control terminal of the pull-up module 200 is coupled to a higher potential, the pull-up transistor M4 is turned on, the second clock signal is a high level, and the signal output terminal OUT outputs a high level. Since the first clock signal is a low level signal, the first pull-down control transistor M11 and the second pull-down control transistor M12 are turned off, the third pull-down control transistor M5 and the fourth pull-down control transistor M6 are turned on, the control terminal of the pull-down module 300 is turned on with the gate and the first pole of the voltage stabilizing transistor M13, the control terminal PD of the pull-down module 300 is pulled down, the first pull-down transistor M2, the second pull-down transistor M7 and the third pull-down transistor M1 are all turned off, and it is ensured that the output stage signal output terminal OUT outputs a high level signal.
In the pull-down period t3, the first clock signal is a high level signal, and therefore, the first pull-down control transistor M11 and the second pull-down control transistor M12 are turned on to raise the potential of the control terminal PD of the pull-down module 300 to a high level. At this time, the first pull-down transistor M2, the second pull-down transistor M7, and the third pull-down transistor M1 are all turned on, thereby pulling the signal output terminal OUT and the control terminal PU of the pull-up module 200 low. The Reset terminal Reset receives the high level signal, turns on the first Reset transistor M3 and the second Reset transistor M9, and pulls the signal output terminal OUT and the control terminal PU of the pull-up module 200 low.
As another aspect of the present invention, a shift register is provided, which includes cascaded multi-stage shift register units, wherein at least one of the shift register units is the above shift register unit provided by the present invention.
Preferably, all shift register units in the shift register are the above shift register units provided by the present invention.
As a further aspect of the present invention, a gate driving circuit is provided, the gate driving circuit includes a shift register, wherein the shift register is the present invention provides an above shift register.
As an aspect of the present invention, there is provided a display device, the display device includes a gate driving circuit, wherein the gate driving circuit is the present invention provides the above gate driving circuit.
It is to be understood that the above embodiments are merely exemplary embodiments that have been employed to illustrate the principles of the present invention, and that the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (13)
1. A shift register unit comprises a signal input end, a signal output end, a low-level signal end, an input module, a pull-up module, a pull-down module and a pull-down control module;
the input end of the input module is connected with the signal input end, and the output end of the input module is connected with the control end of the pull-up module;
the output end of the pull-up module is connected with the signal output end, and the pull-up module can conduct the input end of the pull-up module with the output end of the pull-up module when the control end of the pull-up module receives a high level signal;
the input end of the pull-down module is connected with the low level signal end, the output end of the pull-down module is connected with the signal output end, and the pull-down module can conduct the input end of the pull-down module and the output end of the pull-down module when the control end of the pull-down module receives a high level signal;
the output end of the pull-down control module is connected with the control end of the pull-down module, the input end of the pull-down control module is connected with the control end of the pull-up module, and the pull-down control module is used for outputting a low level signal to the control end of the pull-down module in the output stage of the shift registering unit and outputting a high level signal to the control end of the pull-down module in the pull-down stage of the shift registering unit; it is characterized in that the preparation method is characterized in that,
the shift registering unit further comprises a voltage stabilizing module, the voltage stabilizing module is connected between the input end of the pull-down control module and the low level signal end, the voltage stabilizing module can conduct the input end of the pull-down control module and the low level signal end in the output stage of the shift registering unit, and the voltage stabilizing module allows unidirectional conduction from the input end of the pull-down control module to the low level signal end.
2. The shift register unit according to claim 1, wherein the shift register unit comprises a reset module and a reset terminal, the reset terminal is connected to the control terminal of the reset module, the voltage regulator module comprises a voltage regulator transistor, a first pole of the voltage regulator transistor is connected to the low level signal terminal and a first input terminal of the reset module, a second pole and a gate of the voltage regulator transistor are connected to a second input terminal of the reset module and to the input terminal of the pull-down control module, a first output terminal of the reset module is connected to the signal output terminal, and a second output terminal of the reset module is connected to the control terminal of the pull-up module.
3. The shift register cell of claim 2, wherein the width-to-length ratio of the regulator transistor is greater than or equal to 2.
4. The shift register unit according to claim 2, wherein the reset module comprises a first reset transistor and a second reset transistor, a first pole of the first reset transistor is formed as a first output terminal of the reset module, a second pole of the first reset transistor is formed as a first input terminal of the reset module, and a gate of the first reset transistor is formed as a control terminal of the reset module;
the grid electrode of the second reset transistor is connected with the grid electrode of the first reset transistor, the first pole of the second reset transistor is formed as the second output end of the reset module, and the second pole of the second reset transistor is formed as the second input end of the reset module.
5. The shift register unit according to any one of claims 1 to 4, wherein the input block comprises an input transistor, a gate of the input transistor is connected to a first pole of the input transistor and forms an input terminal of the input block, and a second pole of the input transistor forms an output terminal of the input block.
6. The shift register unit of claim 5, wherein the input module further comprises a filter transistor, a first pole of the filter transistor is connected to the first pole of the input transistor, a second pole of the filter transistor is connected to the second pole of the input transistor, and a gate of the filter transistor is connected to the first clock signal terminal.
7. The shift register unit according to any one of claims 1 to 4, wherein the pull-up module includes a pull-up transistor and a memory cell, a gate of the pull-up transistor is formed as a control terminal of the pull-up transistor, a first pole of the pull-up transistor is connected to the second clock signal terminal, a second pole of the pull-up transistor is connected to the signal output terminal, one end of the memory cell is connected to the gate of the pull-up transistor, and the other end of the memory cell is connected to the second pole of the pull-up transistor.
8. The shift register unit according to any one of claims 1 to 4, wherein the pull-down module comprises a first pull-down transistor and a second pull-down transistor;
a gate of the first pull-down transistor is formed as a control terminal of the pull-down module, a first pole of the first pull-down transistor is formed as an output terminal of the pull-down module, and a second pole of the first pull-down transistor is formed as an input terminal of the pull-down module;
the grid electrode of the second pull-down transistor is connected with the grid electrode of the first pull-down transistor, the first pole of the second pull-down transistor is connected with the control end of the pull-up module, and the second pole of the second pull-down transistor is connected with the input end of the pull-down control module.
9. The shift register unit of claim 8, wherein the pull-down module further comprises a third pull-down transistor, a gate of the third pull-down transistor is connected to the first clock signal terminal, a first pole of the third pull-down transistor is connected to the first pole of the first pull-down transistor, and a second pole of the third pull-down transistor is connected to the input terminal of the pull-down control module.
10. The shift register unit according to any one of claims 1 to 4, wherein the pull-down control module comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, and a fourth pull-down control transistor,
the grid electrode of the first pull-down control transistor is connected with a first clock signal end, the first pole of the first pull-down control transistor is connected with the grid electrode of the first pull-down control transistor, and the second pole of the first pull-down control transistor is connected with the first pole of the fourth pull-down control transistor;
the grid electrode of the second pull-down control transistor is connected with the second pole of the first pull-down control transistor, the first pole of the second pull-down control transistor is connected with the first pole of the first pull-down control transistor, and the second pole of the second pull-down control transistor is connected with the control end of the pull-down module;
the grid electrode of the third pull-down control transistor is connected with the control end of the pull-up module, and the second pole of the third pull-down control transistor is connected with the second pole of the fourth pull-down control transistor and forms the input end of the pull-down control module;
and the grid electrode of the fourth pull-down control transistor is connected with the grid electrode of the third pull-down control transistor, and the first pole of the fourth pull-down control transistor is connected with the control end of the pull-down module.
11. A shift register comprising cascaded multiple stages of shift registering units, wherein at least one of the shift registering units is the shift registering unit according to any one of claims 1 to 10.
12. A gate driver circuit comprising a shift register, wherein the shift register is according to claim 11.
13. A display device comprising a gate driver circuit, wherein the gate driver circuit is the gate driver circuit of claim 12.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621194863.8U CN206115985U (en) | 2016-10-27 | 2016-10-27 | Shift register unit, shift register ware, gate drive circuit, display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621194863.8U CN206115985U (en) | 2016-10-27 | 2016-10-27 | Shift register unit, shift register ware, gate drive circuit, display device |
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| CN206115985U true CN206115985U (en) | 2017-04-19 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111312146A (en) * | 2020-03-04 | 2020-06-19 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
| US11151959B2 (en) | 2020-03-04 | 2021-10-19 | Tcl China Star Optoelectronics Technology Co., Ltd. | GOA circuit and display device |
-
2016
- 2016-10-27 CN CN201621194863.8U patent/CN206115985U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111312146A (en) * | 2020-03-04 | 2020-06-19 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
| CN111312146B (en) * | 2020-03-04 | 2021-07-06 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
| US11151959B2 (en) | 2020-03-04 | 2021-10-19 | Tcl China Star Optoelectronics Technology Co., Ltd. | GOA circuit and display device |
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