CN206060303U - USB OTG current-limiting circuits - Google Patents
USB OTG current-limiting circuits Download PDFInfo
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- CN206060303U CN206060303U CN201621073264.0U CN201621073264U CN206060303U CN 206060303 U CN206060303 U CN 206060303U CN 201621073264 U CN201621073264 U CN 201621073264U CN 206060303 U CN206060303 U CN 206060303U
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Abstract
This application discloses USB OTG current-limiting circuits, including：Voltage detecting circuit, for detecting the charging voltage on VBUS；First current-limiting circuit and the second current-limiting circuit, are used to adjust the charging current on VBUS；Control circuit, connects voltage detecting circuit, the first current-limiting circuit and the second current-limiting circuit respectively；First threshold and Second Threshold are set with voltage detecting circuit, first threshold is less than Second Threshold, when voltage detecting circuit detects the voltage of VBUS less than first threshold, control circuit the first current-limiting circuit of control is closed, the second current-limiting circuit is open-minded；When voltage detecting circuit detects the voltage of VBUS more than Second Threshold, the first current-limiting circuit of control circuit control is opened, the second current-limiting circuit is closed；This utility model arranges different charging current limit values according to the battery electric quantity from equipment during usb communication, so as to ensure USB normal communications, reduces the power consumption of main equipment.
Description
Technical field
The disclosure relates generally to telecommunications field, and in particular to communication connection circuitry, more particularly to USB OTG limits
Current circuit.
Background technology
With the popularization of mobile terminal, in order to realize directly not carrying out data between each electronic equipment by computer
The purpose of exchange, a kind of agreement of OTG (on-the-go) are arisen at the historic moment.This technology can be such that two electronic equipments directly enter
Row communication.
Support that the electronic equipment of OTG agreements is both provided with USB OTG interfaces, in main equipment and the mistake from equipment usb communication
Cheng Zhong, it is the charging current from equipment charge to need a circuit realiration to limit main equipment, and keeps USB normal communications.
In the USB OTG interfaces of existing equipment, only using a current limliting chip to VBUS (energization pins of USB port)
On electric current carry out current limliting, it is impossible to adjust charging current, USB communicating interrupt can be caused when battery electric quantity is relatively low, for example,
When main equipment is communicated to mobile phone USB, charge modes of the USB in low-power consumption, the pattern require the electricity for having 4.4V on VBUS
If pressure mobile phone electricity is too low, then when the voltage on the VBUS of USB is less than 4.2V, communication can be interrupted；When mobile phone
When electricity is more sufficient, USB communications can be normally carried out, if now charging current is larger, the energy consumption of main equipment again can be larger.
Utility model content
In view of drawbacks described above of the prior art or deficiency, expect to provide a kind of USB of scalable charging current
OTG current-limiting circuits.
The USB OTG current-limiting circuits that this utility model is provided include：Voltage detecting circuit, for detecting the charging on VBUS
Voltage；First current-limiting circuit and the second current-limiting circuit, are used to adjust the charging current on VBUS；Control circuit, connects respectively
Voltage detecting circuit, the first current-limiting circuit and the second current-limiting circuit；First threshold and are set with the voltage detecting circuit
Two threshold values, first threshold are less than Second Threshold Second Threshold；When voltage detecting circuit detects that the voltage of VBUS is less than first threshold
When, control circuit the first current-limiting circuit of control is closed, the second current-limiting circuit is open-minded；When voltage detecting circuit detects the voltage of VBUS
During more than Second Threshold, the first current-limiting circuit of control circuit control is opened, the second current-limiting circuit is closed.
According to the technical scheme that the embodiment of the present application is provided, the voltage detecting circuit includes dual pathways voltage detecting core
Piece, the voltage checking chip：Its power pins is connected with VBUS；Its power pins is also grounded by electric capacity C5；Which is first electric
Pressure sense pins are connected with VBUS by resistance R5；Its second voltage sense pins is by resistance R6 and first voltage sense pins
Connection；Its second voltage sense pins is also grounded by resistance R7；Its grounding pin is directly grounded；Its first signal output pin
Pass through resistance R8 and resistance R9 respectively with secondary signal output pin and connect power supply；By the resistance for adjusting resistance R5, R6 and R7
The first threshold and Second Threshold of setting voltage detection chip；When first voltage sense pins and second voltage sense pins are sensed
Magnitude of voltage when be respectively less than first threshold, first signal output pin and secondary signal output pin export low electricity
It is flat；It is when the magnitude of voltage that first voltage sense pins and second voltage sense pins are sensed is all higher than Second Threshold, described
First signal output pin and secondary signal output pin export high level.
According to the technical scheme that the embodiment of the present application is provided, the control circuit includes CPU, the CPU, its first signal
Input pin and secondary signal input pin the first signal output pin and secondary signal respectively with the voltage checking chip
Output pin connects；Its first control signal output pin and the second control signal output pin draw in first signal input
Foot and secondary signal input pin export high level and low level when being high level respectively；Its first control signal is exported
Pin and the second control signal output pin are low level in the first signal input pin and secondary signal input pin
When export low level and high level respectively.
According to the technical scheme that the embodiment of the present application is provided, first current-limiting circuit includes the first current limiting switch chip,
The first current limiting switch chip, its input pin are connected with VBUS, and are grounded by electric capacity C1；It is described which enables pin connection
The first control signal output pin of CPU；Which is arranged pin and is grounded by resistance R1；Its output pin is grounded by electric capacity C2；
Its grounding pin is directly grounded；The cut-off current I of the first current-limiting circuit can be set by adjusting the resistance R11lim。
According to the technical scheme that the embodiment of the present application is provided, second current-limiting circuit includes the second current limiting switch chip,
The second current limiting switch chip, its input pin are connected with VBUS, and are grounded by electric capacity C4；It is described which enables pin connection
The second control signal output pin of CPU；Which is arranged pin and is grounded by resistance R3；Its output pin is grounded by electric capacity C3；
Its grounding pin is directly grounded；The cut-off current I of the second current-limiting circuit can be set by adjusting the resistance R32lim。
Above-mentioned cut-off current I1limLess than cut-off current I2lim。
When the battery electric quantity from equipment is less, the voltage of the first voltage sense pins sensing of voltage checking chip
Value exports low level less than first threshold, first signal output pin and secondary signal output pin；First control of CPU
Signal output pin processed and the second control signal output pin export high level and low level respectively；First current limiting switch chip is closed
Close；Second current limiting switch chip is opened, and now the cut-off current on VBUS is I2lim。
When the battery electric quantity from equipment is more, the voltage of the second voltage sense pins sensing of voltage checking chip
Value exports high level more than Second Threshold, first signal output pin and secondary signal output pin；CPU first is controlled
Signal output pin and the second control signal output pin export low level and high level respectively；First current limiting switch chip is opened
Open；Second current limiting switch chip is closed, and now the cut-off current on VBUS is I1lim。
Above-mentioned technical proposal of the present utility model, has used multiple chips to build circuit, has realized the voltage according to VBUS on USB
Value current limliting is adjusted, and switches cut-off current；Different charging current limits are arranged according to the battery electric quantity from equipment during usb communication
Value, so as to ensure USB normal communications, reduces the power consumption of main equipment；Voltage detecting circuit in this utility model is provided with first
Threshold value and Second Threshold, form between first threshold and Second Threshold to the relief area of voltage detecting point so that the result of detection
More accurately, detection circuit is more stable.
Description of the drawings
By reading the detailed description made to non-limiting example made with reference to the following drawings, the application other
Feature, objects and advantages will become more apparent upon：
Fig. 1 is the theory diagram of this utility model USB OTG current-limiting circuits；
Fig. 2 is the circuit diagram of voltage detecting circuit；
Fig. 3 is the circuit diagram of control circuit；
Fig. 4 is the circuit diagram of the first current-limiting circuit；
Fig. 5 is the circuit diagram of the second current-limiting circuit；
Fig. 6 is the circuit diagram of USB port；
Fig. 7 is the workflow diagram of USB OTG current-limiting circuits.
In figure：10th, voltage detecting circuit；20、VBUS；30th, the first current-limiting circuit；40th, the second current-limiting circuit；50th, control
Circuit；U2, voltage checking chip；SENSE1, first voltage sense pins；SENSE2, second voltage sense pins；GND1, electricity
The grounding pin of pressure detection chip；OUT1, the first signal output pin；OUT2, secondary signal output pin；VDD, voltage detecting
The energization pins of chip；U4、CPU；IO1, the first signal input pin；IO2, secondary signal input pin；IO3, the first control
Signal output pin；IO4, the second control signal output pin；U1, the first current limiting switch chip；/ ON1, the first current limiting switch core
The enable pin of piece；The setting pin of SET1, the first current limiting switch chip；The signal output of OUT3, the first current limiting switch chip
Pin；The input pin of IN1, the first current limiting switch chip；The grounding pin of GND2, the first current limiting switch chip；U3, the second limit
Stream switch chip；The enable pin of/ON2, the second current limiting switch chip；The setting pin of SET2, the second current limiting switch chip；
The signal output pin of OUT4, the second current limiting switch chip；The input pin of IN2, the second current limiting switch chip；GND3, second
The grounding pin of current limiting switch chip；J1, USB interface.
Specific embodiment
With reference to the accompanying drawings and examples the application is described in further detail.It is understood that this place is retouched
The specific embodiment stated is used only for explaining related invention, rather than the restriction to the invention.It also should be noted that, in order to
It is easy to description, in accompanying drawing, illustrate only the part related to invention.
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the application can phase
Mutually combine.Below with reference to the accompanying drawings and in conjunction with the embodiments describing the application in detail.
Fig. 1 is refer to, the theory diagram of USB OTG current-limiting circuits, the circuit include：
Voltage detecting circuit 10, for detecting the charging voltage on VBUS 20；First current-limiting circuit 30 and the second current limliting electricity
Road 40, is used to adjust the charging current on VBUS 20；Control circuit 50, connects voltage detecting circuit 10, the first current limliting respectively
Circuit 30 and the second current-limiting circuit 40；First threshold and Second Threshold, first threshold are set with the voltage detecting circuit 10
Less than Second Threshold；When voltage detecting circuit 10 detects the voltage of VBUS 20 less than first threshold, control circuit control first
Current-limiting circuit 30 is closed, the second current-limiting circuit 40 is open-minded；When voltage detecting circuit 10 detects that the voltage of VBUS 20 is more than the second threshold
During value, open, the second current-limiting circuit 40 is closed by the first current-limiting circuit 30 for the control of control circuit 50.
In main equipment with from during device talk, if more sufficient from equipment electricity, its charging current can be less, now
Main equipment is larger with the communication power consumption from equipment, can decline from equipment voltage, and above-mentioned first threshold is lower limit under now voltage
Position test point；If very low from equipment electricity, its charging current is larger, can step up from equipment voltage, and Second Threshold is this
When voltage lifting position-limit test point.
As shown in Fig. 2 in a preferred embodiment, the voltage detecting circuit 10 (for example may be used by voltage checking chip U2
Being dual pathways voltage detector TPS3780) and its peripheral circuit composition, the 6th pin of U2 is energization pins VDD, the pin
It is grounded by electric capacity C5, and is connected with VBUS 20 and powers to U2；1st pin of U2 is first voltage sense pins SENSE1, should
Pin is connected with VBUS 20 by resistance R5；3rd pin of U2 is second voltage sense pins SENSE2, and the pin is by electricity
Resistance R6 is connected with the 1st pin；3rd pin of U2 is also grounded by resistance R7, and the bleeder circuit formed between R5, R6 and R7 can
The sensing voltage of the 1st pin and the 3rd pin is adjusted, while also cause the input of the 1st pin and the 3rd pin that there is hysteresis characteristic,
Short and small burr pulse can be suppressed, so that it is guaranteed that output is accurate；2nd pin of U2 is grounding pin GND1, and the pin is direct
Ground connection；5th pin of U2 and the 4th pin are respectively the first signal output pin OUT1 and secondary signal output pin OUT2, and
And passing through resistance R8 and resistance R9 connection power supply VCC1 respectively, VCC1 is provided by control circuit 50 herein；When the 1st pin and the 3rd
When the voltage being input on pin is less than first threshold, the 5th pin and the 4th pin are driven via storage capacitors simultaneously as low level.Draw when the 1st
When the voltage being input on foot and the 3rd pin is higher than Second Threshold, the 5th pin and the 4th pin are changed into high level simultaneously.
When standard USB is communicated, the magnitude of voltage on VBUS 20 is 5V, and the low-power consumption charge mode of USB is requirement VBUS 20
On have the voltage of 4.4V, many experiments show that USB is unable to normal communication when the voltage on VBUS 20 is less than 4.2V, because
In this above-mentioned voltage detecting circuit 10, the first threshold for arranging voltage can for example be 4.2V, and Second Threshold can for example be
4.3V, forms relief area between first threshold and Second Threshold, it is to avoid the situation of signal bounce occurs in Near The Critical Point in voltage.
As shown in figure 3, the CPU U4 of the control circuit 50 can for example be torch power GT7, the 1st pin of U4 and the 2nd draws
Foot is respectively the first signal input pin IO1 and secondary signal input pin IO2, and its 3rd pin and the 4th pin are respectively first
Control signal output pin IO3 and the second control signal output pin IO4；1st pin and the 2nd pin of U4 respectively with U2
5 pins and the connection of the 4th pin；When the input of the 1st pin and the 2nd pin of U4 is low level, its high electricity of the 3rd pin output
Flat, the 4th pin output low level；When the 1st pin and the 2nd pin of U4 are high level, its 3rd pin output low level,
4th pin exports high level.
As shown in figure 4, first current-limiting circuit 30 includes the first current limiting switch chip U1, such as the first current limiting switch core
Piece U1 can use current limliting P-channel metal-oxide-semiconductor field-effect transistor on and off switch IA4010；1st pin of U1 is
Output pin OUT3, the pin are signal output pin, are grounded by electric capacity C2；The 2nd pin grounding pin GND2 of U1, this draws
Foot is directly grounded；To arrange pin SET1, the pin is grounded 3rd pin of U1 by resistance R1, resistance and this electricity of resistance R1
The cut-off current on road is inversely proportional to, the cut-off current I of the first current-limiting circuit 30 in the present embodiment1limFor example can be set to by resistance R1
100mA；4th pin of U1 is connected with the 3rd pin of U4 after pin serial connection resistance R2 to enable pin/ON1；Draw the 5th of U1
Foot is input pin IN1, and the pin is connected with VBUS20, is also grounded by electric capacity C1.
As shown in figure 5, second current-limiting circuit 40 includes the second current limiting switch chip U3, such as U3 can also be using limit
Stream P-channel metal-oxide-semiconductor field-effect transistor on and off switch IA4010；1st pin of U3 is output pin OUT4,
The pin is signal output pin, is grounded by electric capacity C3；2nd pin of U3 is grounding pin GND3, and the pin is directly grounded；
To arrange pin SET2, the pin is grounded 3rd pin of U3 by resistance R3, the resistance of resistance R3 and the cut-off current of this circuit into
Inverse ratio, the cut-off current I of the second current-limiting circuit 40 in the present embodiment2limFor example 500mA can be set to by resistance R3；The of U3
4 pins are connected with the 4th pin of U4 after pin serial connection resistance R4 to enable pin/ON2；5th pin of U3 is input pin
IN2, the pin are connected with VBUS 20, are also grounded by electric capacity C4.
The circuit of USB interface J1 is illustrated in figure 6, the 1st pin of the 1st pin and U3 of U1 is connected to the 1st pin of J1.
The course of work of this circuit is illustrated in figure 7, is connected with being set up by USB OTG from equipment in main equipment starting up
When connecing, the U3 that U4 is controlled in U1 and the second current-limiting circuit 40 in the first current-limiting circuit 30 is opened, and is setting up communication
Incipient stage gives sufficiently large electric current, it is ensured that for different electricity can set up communication from equipment.
After connection establishment, voltage detecting circuit 10 starts to detect the voltage on VBUS 20 that the initial voltage from equipment is relatively low
When, the 1st pin of U2 and the 3rd pin sense the voltage less than such as 4.2V, and now U2 controls its 5th pin and
4 pins export low level, and U4 controls its 3 pin after receiving the low level signal that its 1st pin and the 2nd pin are input at the same time
With the 4th pin respectively to U1 and U3 output high level and low level, now U1 closings, U3 are opened, the charging current on VBUS 20
It is limited to such as 500mA；Charging voltage can be drawn high by high charge current, it is ensured that what USB was communicated is normally carried out, when in charging voltage
When rising above such as 4.3V, the 1st pin of U2 and the 3rd pin sense the voltage more than 4.3V, and USB can just normal open
News, U4 control its 3rd pin and pin point after receiving the high level signal that its 1st pin and the 2nd pin are input at the same time
Not to U1 and U3 output low levels and high level, now U1 is opened, and U3 is closed, and the charging current on VBUS 20 is limited to for example
100mA, reduces the charging energy consumption of main equipment.
If the electricity after connection establishment from equipment is higher, the 1st pin of U2 and the 3rd pin are sensed more than for example
The voltage of 4.3V, USB can normal communication, U4 receive at the same time its 1st pin and the 2nd pin input high level signal after control
Its 3rd pin and the 4th pin are made respectively to U1 and U3 output low levels and high level, now U1 unlatchings, U3 are closed, VBUS 20
On charging current be limited to such as 100mA, reduce the charging energy consumption of main equipment.
Above example is a kind of example embodiment of technical scheme, above-mentioned voltage detecting circuit 10,
One current-limiting circuit 30 and the second current-limiting circuit 40 can also adopt other can be with the voltage detecting circuit 10 of type and current-limiting circuit.
Above description is only the preferred embodiment and the explanation to institute's application technology principle of the application.People in the art
Member is it should be appreciated that invention scope involved in the application, however it is not limited to the technology of the particular combination of above-mentioned technical characteristic
Scheme, while should also cover in the case of without departing from the inventive concept, is carried out by above-mentioned technical characteristic or its equivalent feature
Combination in any and other technical schemes for being formed.Such as features described above has similar work(with (but not limited to) disclosed herein
The technical scheme that the technical characteristic of energy is replaced mutually and formed.
Claims (5)
1. a kind of USB OTG current-limiting circuits, it is characterised in that the circuit includes：
Voltage detecting circuit (10), for detecting the charging voltage on VBUS (20)；
First current-limiting circuit (30) and the second current-limiting circuit (40), are used to adjust the charging current on VBUS (20)；
Control circuit (50), connects voltage detecting circuit (10), the first current-limiting circuit (30) and the second current-limiting circuit (40) respectively；
First threshold and Second Threshold are set with the voltage detecting circuit (10), first threshold is less than Second Threshold；Work as electricity
When the voltage of pressure detection circuit (10) detection VBUS (20) is less than first threshold, control circuit (50) controls the first current-limiting circuit
(30) closing, the second current-limiting circuit (40) are open-minded；When voltage detecting circuit (10) detects that the voltage of VBUS (20) is more than the second threshold
During value, control circuit (50) the first current-limiting circuit of control (30) is opened, the second current-limiting circuit (40) is closed.
2. USB OTG current-limiting circuits according to claim 1, it is characterised in that
The voltage detecting circuit (10) includes dual pathways voltage checking chip (U2), the voltage checking chip (U2)：
Its power pins (VDD) are connected with VBUS (20)；
Its power pins (VDD) are also grounded by electric capacity C5；
Its first voltage sense pins (SENSE1) is connected with VBUS (20) by resistance R5；
Its second voltage sense pins (SENSE2) is connected with first voltage sense pins (SENSE1) by resistance R6；
Its second voltage sense pins (SENSE2) is also grounded by resistance R7；
Its grounding pin (GND1) is directly grounded；
Its first signal output pin (OUT1) and secondary signal output pin (OUT2) pass through resistance R8 and resistance R9 respectively and connect
Connect power supply；
By the first threshold and Second Threshold of resistance setting voltage detection chip (U2) of regulation resistance R5, R6 and R7；
When the magnitude of voltage that first voltage sense pins (SENSE1) and second voltage sense pins (SENSE2) are sensed is respectively less than
When one threshold value, first signal output pin (OUT1) and secondary signal output pin (OUT2) export low level；
When the magnitude of voltage that first voltage sense pins (SENSE1) and second voltage sense pins (SENSE2) are sensed is all higher than
When two threshold values, first signal output pin (OUT1) and secondary signal output pin (OUT2) export high level.
3. USB OTG current-limiting circuits according to claim 1 and 2, it is characterised in that
The control circuit (10) includes CPU (U4), the CPU (U4),
Its first signal input pin (IO1) and secondary signal input pin (IO2) respectively with the voltage checking chip (U2)
The first signal output pin (OUT1) and secondary signal output pin (OUT2) connection；
Its first control signal output pin (IO3) and the second control signal output pin (IO4) are in first signal input
Pin (IO1) and secondary signal input pin (IO2) export high level and low level when being high level respectively；
Its first control signal output pin (IO3) and the second control signal output pin (IO4) are in first signal input
Pin (IO1) and secondary signal input pin (IO2) export low level and high level when being low level respectively.
4. USB OTG current-limiting circuits according to claim 3, it is characterised in that
First current-limiting circuit (30) includes the first current limiting switch chip (U1), the first current limiting switch chip (U1),
Its input pin (IN1) connection VBUS (20), and be grounded by electric capacity C1；
Which enables the first control signal output pin (IO3) that pin (/ON1) connects the CPU (U4)；
Which is arranged pin (SET1) and is grounded by resistance R1；
Its output pin (OUT3) is grounded by electric capacity C2；
Its grounding pin (GND2) is directly grounded；
The cut-off current I of the first current-limiting circuit (30) is set by adjusting the resistance R11lim。
5. USB OTG current-limiting circuits according to claim 4, it is characterised in that
Second current-limiting circuit (40) includes the second current limiting switch chip (U3), the second current limiting switch chip (U3),
Its input pin (IN2) connection VBUS (20), and be grounded by electric capacity C4；
Which enables the second control signal output pin (IO4) that pin (/ON2) connects the CPU (U4)；
Which is arranged pin (SET2) and is grounded by resistance R3；
Its output pin (OUT4) is grounded by electric capacity C3；
Its grounding pin (GND3) is directly grounded；
The cut-off current I of the second current-limiting circuit (40) is set by adjusting the resistance R32lim。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621073264.0U CN206060303U (en) | 2016-09-22 | 2016-09-22 | USB OTG current-limiting circuits |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621073264.0U CN206060303U (en) | 2016-09-22 | 2016-09-22 | USB OTG current-limiting circuits |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108829621A (en) * | 2018-07-17 | 2018-11-16 | 天津瑞发科半导体技术有限公司 | A kind of usb expansion function device |
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2016
- 2016-09-22 CN CN201621073264.0U patent/CN206060303U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108829621A (en) * | 2018-07-17 | 2018-11-16 | 天津瑞发科半导体技术有限公司 | A kind of usb expansion function device |
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Granted publication date: 20170329 Termination date: 20190922 |