CN206058177U - A kind of safe CPU debugging systems - Google Patents
A kind of safe CPU debugging systems Download PDFInfo
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- CN206058177U CN206058177U CN201620657882.3U CN201620657882U CN206058177U CN 206058177 U CN206058177 U CN 206058177U CN 201620657882 U CN201620657882 U CN 201620657882U CN 206058177 U CN206058177 U CN 206058177U
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Abstract
The utility model discloses a kind of safe CPU debugging systems, including master chip and debugging acid；Safe CPU, bus module and master cpu are included in the master chip, wherein safe CPU passes sequentially through safe cpu bus interface, bus module, master cpu EBI being connected with master cpu；Debugging acid is provided with the first pin, and master cpu is provided with the second pin being connected with the first pin；Also include the monitoring module being connected with safe cpu bus interface, the monitoring module is additionally provided with monitoring module EBI, monitoring module EBI is connected with master cpu EBI by bus module, and the monitoring module is provided with the interrupt requests end being connected with master cpu.This utility model is with low cost, and debugging is convenient, safe, even if safe CPU occurs hanging dead phenomenon, debugging acid can also obtain the abnormal state information of safe CPU, and so as to find and orientation problem, debugging effect is high, reduces the risk that master chip normally can not be used.
Description
Technical field
This utility model belongs to safe CPU debugging field, more particularly to a kind of safe CPU debugging systems.
Background technology
In the security system, in order to ensure the information security of whole system, it is impossible to by safe CPU（Central
Processing Unit, central processing unit）UART（Universal Asynchronous Receiver/
Transmitter, universal asynchronous receiving-transmitting transmitter）、JTAG（Joint Test Action Group, joint test working group）
The indirect modes such as interface duplex are directed or through Deng debugging interface to be connected on master chip pin.As UART, JTAG etc. are adjusted
Mouth of trying is not drawn, and will be unable to find and orientation problem after exception occurs in safe CPU, and this can be brought to the debugging of safe CPU
Very big challenge.
With the development of information technology, in order to solve thing followed information security issue, more and more safety are now
System adopts multi-CPU architecture, wherein comprising safe CPU and master cpu.Wherein safe CPU is responsible for the information security of whole system, main
Control CPU is responsible for other functions of system.
Because the debugging interface of safe CPU is not can connect on master chip pin, debugging acid can only pass through master control
Communication mechanism between CPU and safe CPU is obtaining the partial information and state of safe CPU.As shown in figure 1, existing safety
CPU debugging systems include master chip 1 and debugging acid 2；Safe CPU9, bus module 8 and master control are included in the master chip 1
CPU7, safe CPU9 are provided with safe cpu bus interface 12,13, and master cpu 7 is provided with master cpu EBI 14,15, wherein pacifying
Full CPU9 passes sequentially through safe cpu bus interface 12,13, bus module 8,7 phase of master cpu EBI 14,15 and master cpu
Even, debugging acid 2 is provided with the first pin 3,4, and master cpu 7 is provided with the second pin 5,6 being connected with the first pin 3,4.Bus mould
Block 8 is also connected with memory module 18, and memory module 18 is mainly used in safe CPU9 operation programs, the operation journey of master cpu 7
Communication between sequence, safe CPU9 and master cpu 7.Memory module 18 includes SRAM（In piece/piece outside）, depositor, SDRAM
With flash etc..
Although existing safe CPU debugging systems ensure that information security, but when safe CPU9 occurs hanging dead phenomenon
（Caused by the abnormal conditions such as illegal address are accessed）When, it is as now master cpu 7 cannot be carried out with the communication of safe CPU9, main
Control CPU7 also just has no idea to obtain other any states of safe CPU9 and information, so as to find and orientation problem, drop
Debugging effect of lower security CPU9, increases the risk that master chip 1 normally can not be used.
The content of the invention
When dead phenomenon occurs hanging in safe CPU, existing safe CPU debugging systems cannot find and orientation problem, safety
Debugging effect of CPU is low, and the risk that master chip normally can not be used is big.The purpose of this utility model is, for above-mentioned existing
A kind of deficiency of technology, there is provided safe CPU debugging systems for improving.
To solve above-mentioned technical problem, the technical scheme adopted by this utility model is：
A kind of safe CPU debugging systems, including master chip and debugging acid；Safe CPU, bus mould are included in the master chip
Block and master cpu, wherein safe CPU passes sequentially through safe cpu bus interface, bus module, master cpu EBI and master control
CPU is connected；Debugging acid is provided with the first pin, and master cpu is provided with the second pin being connected with the first pin；Also include and safety
The monitoring module that cpu bus interface is connected, the monitoring module are additionally provided with monitoring module EBI, and monitoring module EBI leads to
Cross bus module to be connected with master cpu EBI, the monitoring module is provided with the interrupt requests end being connected with master cpu.
By said structure, by connecting a monitoring module on safe cpu bus interface, monitoring module is used to monitor
Whether occur in that on safe cpu bus that accessing illegal address etc. is easily caused the dead Common Abnormity phenomenon of safe CPU extensions.Once occur
Abnormal phenomena, monitoring module read the abnormal state information of safe CPU, while sending interrupt requests letter by interrupt requests end
Number give master cpu, then master cpu by bus module reading monitoring module in abnormal state information.Final debugging acid
Abnormal state information can be inquired.
Used as a kind of optimal way, the monitoring module includes the register module being connected with each other and bus detection module,
The register module is connected with the bus module by monitoring module EBI, the bus detection module and the peace
Full cpu bus interface is connected, and the bus detection module is connected with master cpu by interrupt requests end.
Register module workflow：Safe CPU can go to access register module by bus module, can be by matching somebody with somebody
Put the register module to decide whether to open monitoring, and specifically monitor what kind of abnormal access（For example monitor illegal
Address or illegal request type are all monitored）.Have no progeny in master cpu receives abnormal access and can pass through bus module
Read register module to obtain the specifying information of abnormal conditions.
Bus detection module is used for real-time detection, when the information such as the address on safe cpu bus or access type occurs
It is anticipated that abnormal conditions when corresponding information on safe cpu bus can be stored in register module, while in triggering
Break signal, sends interrupt request singal to master cpu by interrupt requests end.
Compared with prior art, this utility model is with low cost, and debugging is convenient, safe, even if hanging occurs in safe CPU
Dead phenomenon, debugging acid can also obtain the abnormal state information of safe CPU, and so as to find and orientation problem, debugging effect is high, drop
The risk that low master chip normally can not be used.
Description of the drawings
Fig. 1 is the structural representation of existing safe CPU debugging systems.
Structural representations of the Fig. 2 for one embodiment of this utility model.
Fig. 3 is the structural representation of monitoring module in Fig. 2.
Wherein, 1 is master chip, and 2 is debugging acid, and 3 and 4 is the first pin, and 5 and 6 is the second pin, and 7 is master cpu, 8
For bus module, 9 is safe CPU, and 10 is monitoring module, and 11 is interrupt requests end, and 12 and 13 is safe cpu bus interface, 14
It is master control cpu bus interface with 15,16 and 17 is monitoring module EBI, and 18 is memory module, and 19 is register module,
20 is bus detection module.
Specific embodiment
As shown in Fig. 2 an embodiment of the present utility model includes master chip 1 and debugging acid 2；Include in the master chip 1
Safe CPU9, bus module 8 and master cpu 7, safe CPU9 are provided with safe cpu bus interface 12,13, and master cpu 7 is provided with master
Control cpu bus interface 14,15, wherein safe CPU9 passes sequentially through safe cpu bus interface 12,13, bus module 8, master cpu
EBI 14,15 is connected with master cpu 7；Debugging acid 2 is provided with the first pin 3,4, and master cpu 7 is provided with and the first pin 3,
4 the second pins 5,6 being connected；Also include the monitoring module 10 being connected with safe cpu bus interface 12,13, the monitoring module 10
Monitoring module EBI 16,17 is additionally provided with, monitoring module EBI 16,17 is connect with master cpu bus by bus module 8
Mouth 14,15 is connected, and the monitoring module 10 is provided with the interrupt requests end 11 being connected with master cpu 7.Bus module 8 also with storage
Device module 18 be connected, memory module 18 be mainly used in safe CPU9 operation programs, 7 operation program of master cpu, safe CPU9 and
Communication between master cpu 7.Memory module 18 includes SRAM（In piece/piece outside）, depositor, SDRAM and flash etc..
The monitoring module 10 includes the register module 19 being connected with each other and bus detection module 20, the depositor mould
Block 19 is connected with the bus module 8 by monitoring module EBI 16,17, the bus detection module 20 and the safety
Cpu bus interface 12,13 is connected, and the bus detection module 20 is connected with master cpu 7 by interrupt requests end 11.
Debugging acid 2 refers to that can pass through the first pin 3,4 is connected with outside CPU to be debugged and inquires about and control
The instrument of CPU state.Two the first pins 3,4 are shown in Fig. 2, debugging acid 2 are not represented and there was only two the first pins 3,4,
The number of actual first pin 3,4 is determined according to debugging interface type.
Master chip 1 has certain information security function.Master cpu 7 is responsible for the CPU of groundwork in referring to master chip 1.Peace
Full CPU9 is responsible for the CPU of information security in referring to master chip 1.Bus module 8 plays modules in referring to master chip 1 and mutually interconnects
The module of effect is connect, agreement and interface conversion effect is played.
Monitoring module 10 is responsible for the module of the safe CPU9 bus states of monitoring in referring to master chip 1.When safe CPU9 occurs
During abnormal conditions, monitoring module 10 exports interrupt request singal to master cpu 7 by interrupt requests end 11.
Second pin 5,6 is the debugging pin of master chip 1, illustrates two the second pins 5,6, do not represent main core in Fig. 2
The number that piece 1 only has two the second pins 5,6, actual second pin 5,6 is determined according to debugging interface type.
In the same manner, two safe cpu bus interfaces 12,13 are shown in Fig. 2, safe CPU9 are not represented and there was only two bus letters
Number；Two master cpu EBIs 14,15 are shown in Fig. 2, master cpu 7 are not represented and there was only two bus signals；Show in Fig. 2
Go out two monitoring module EBIs 16,17, do not represent monitoring module 10 and there was only two bus signals.Actual bus quantity is equal
Determined according to bus type.
Operation principle of the present utility model is as follows：
Monitoring module 10 is used for the working condition for monitoring safe CPU9.When safe CPU9 normal works, monitoring module 10
Any safe cpu bus interface 12 will not be obtained, any information on 13；When monitoring module 10 finds to go out in safe CPU9 buses
When now access illegal address, request type etc. are likely to result in the dead access of safe CPU9 extensions in meeting record security CPU9 buses
Abnormal state information（Reference address, access type, access length etc.）, while sending interrupt requests letter by interrupt requests end 11
Number give master cpu 7, then master cpu 7 by bus module 8 read monitoring module 10 in abnormal state information.It is final to debug
Instrument 2 can inquire abnormal state information.Commissioning staff is can be found that substantially according to abnormal state information and orientation problem.Treat
Exclude or shield after relevant issues subsequently through means such as modification software programs, can proceed with debugging.
Claims (2)
1. a kind of safe CPU debugging systems, including master chip（1）And debugging acid（2）；The master chip（1）It is interior comprising safe CPU
（9）, bus module（8）And master cpu（7）, wherein safe CPU（9）Pass sequentially through safe cpu bus interface（12,13）, bus
Module（8）, master cpu EBI（14,15）And master cpu（7）It is connected；Debugging acid（2）It is provided with the first pin（3,4）,
Master cpu（7）It is provided with and the first pin（3,4）The second connected pin（5,6）；Characterized in that, also including total with safe CPU
Line interface（12,13）Connected monitoring module（10）, the monitoring module（10）It is additionally provided with monitoring module EBI（16,17）,
Monitoring module EBI（16,17）By bus module（8）With master cpu EBI（14,15）It is connected, the monitoring mould
Block（10）It is provided with and master cpu（7）Connected interrupt requests end（11）.
2. safe CPU debugging systems as claimed in claim 1, it is characterised in that the monitoring module（10）Including mutually interconnecting
The register module for connecing（19）With bus detection module（20）, the register module（19）By monitoring module EBI
（16,17）With the bus module（8）It is connected, the bus detection module（20）With the safe cpu bus interface（12,13）
It is connected, the bus detection module（20）By interrupt requests end（11）With master cpu（7）It is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620657882.3U CN206058177U (en) | 2016-06-29 | 2016-06-29 | A kind of safe CPU debugging systems |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620657882.3U CN206058177U (en) | 2016-06-29 | 2016-06-29 | A kind of safe CPU debugging systems |
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| CN206058177U true CN206058177U (en) | 2017-03-29 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107273291A (en) * | 2017-06-14 | 2017-10-20 | 湖南国科微电子股份有限公司 | A kind of processor debugging method and system |
| CN107423243A (en) * | 2017-04-18 | 2017-12-01 | 深圳市有芯半导体技术有限公司 | It is a kind of to prevent CPU from hanging dead method |
-
2016
- 2016-06-29 CN CN201620657882.3U patent/CN206058177U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107423243A (en) * | 2017-04-18 | 2017-12-01 | 深圳市有芯半导体技术有限公司 | It is a kind of to prevent CPU from hanging dead method |
| CN107423243B (en) * | 2017-04-18 | 2020-09-15 | 深圳市有芯半导体技术有限公司 | Method for preventing CPU from being hung up |
| CN107273291A (en) * | 2017-06-14 | 2017-10-20 | 湖南国科微电子股份有限公司 | A kind of processor debugging method and system |
| CN107273291B (en) * | 2017-06-14 | 2021-01-01 | 湖南国科微电子股份有限公司 | Processor debugging method and system |
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