CN205920745U

CN205920745U - Pixel circuit , display panel and display device

Info

Publication number: CN205920745U
Application number: CN201620917837.7U
Authority: CN
Inventors: 张毅; 张锴; 玄明花; 高永益; 皇甫鲁江
Original assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Current assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Priority date: 2016-08-22
Filing date: 2016-08-22
Publication date: 2017-02-01
Anticipated expiration: 2026-08-22

Abstract

The utility model provides a pixel circuit, display panel and display device, this pixel circuit of includes storage capacitance, organic light -emitting diode, drive transistor, sends out light controlling circuit, reset circuit, threshold value compensation circuit, first data write circuit, reference voltage write circuit and initializing circuit. This pixel circuit, display panel and display device can carry out the compensation of resistance drop and threshold voltage to display panel, has improved drive current's homogeneity, and then has improved the homogeneity that display panel shows, reduces the high contrast of leakage current when guaranteeing black attitude simultaneously to and make through the proportion that adjustment light emitting time accounted for a frame display time section and guarantee accurate demonstration under the low gray scale condition.

Description

Image element circuit, display floater and display device

Technical field

Embodiment of the disclosure is related to a kind of image element circuit, display floater and display device.

Background technology

In display field, Organic Light Emitting Diode (oled) display floater has self-luminous, contrast is high, energy consumption is low, regard Angle is wide, fast response time, can be used for flexibility panel, using wide temperature range, be simple to manufacture the features such as, there is wide development Prospect.

Due to These characteristics, Organic Light Emitting Diode (oled) display floater goes for mobile phone, display, notebook Computer, digital camera, instrument and meter etc. have the device of display function.

Utility model content

Embodiment of the disclosure provides a kind of image element circuit, comprising: storage capacitance, including first being connected with primary nodal point End and the second end being connected with secondary nodal point；Organic Light Emitting Diode, including the first pole being connected with the 3rd node；Drive crystal Pipe, including the grid being connected with described primary nodal point, wherein, described driving transistor is configured to according to described primary nodal point Voltage controls described organic light-emitting diode；Emission control circuit, is configured to receive LED control signal and according to institute State LED control signal and control described organic light-emitting diode or shutoff；Reset circuit, is configured to receive the control that resets Signal simultaneously writes resetting voltage according to described reseting controling signal to described primary nodal point；Threshold compensation circuitry, is configured to connect Receive the first scanning signal and offset voltage, wherein, described compensation are write to described primary nodal point according to described first scanning signal Voltage is the threshold voltage sum of the first supply voltage and described driving transistor；First data write circuit, is configured to connect Receive the first scanning signal data signal and described data signal is write to described secondary nodal point according to described first scanning signal； Reference voltage write circuit, is configured to receive the second scanning signal and according to described second scanning signal to described secondary nodal point Write reference voltage；And initializing circuit, it is configured to receive described first scanning signal or described reseting controling signal simultaneously Described initialization voltage is write to the 3rd node according to described first scanning signal or described reseting controling signal.

For example, in the image element circuit that the embodiment of the present disclosure provides, described initialization voltage is equal to described resetting voltage.

For example, in the image element circuit that the embodiment of the present disclosure provides, described Organic Light Emitting Diode also includes the second pole, institute State the second pole of Organic Light Emitting Diode and second source line electrically connects to receive second source voltage, described organic light-emitting diodes The first of pipe extremely anode, the second extremely negative electrode of described Organic Light Emitting Diode, described initialization voltage and described second electricity Source difference in voltage is less than the bright voltage of described Organic Light Emitting Diode.

For example, in the image element circuit that the embodiment of the present disclosure provides, described initialization voltage is less than or equal to described second electricity Source voltage.

For example, in the image element circuit that the embodiment of the present disclosure provides, described reset circuit includes the first transistor, described threshold Value compensation circuit includes transistor seconds, and described first data write circuit includes third transistor, described reference voltage write Circuit includes the 4th transistor, and described emission control circuit includes the 5th transistor, and described initializing circuit includes the 6th crystal Pipe.

For example, in the image element circuit that the embodiment of the present disclosure provides, the grid of described driving transistor and described first segment Point electrical connection, the first pole of described driving transistor electrically connects to receive the first supply voltage with the first power line, described driving Second pole of transistor is electrically connected with fourth node；First pole of described Organic Light Emitting Diode is electrically connected with described 3rd node Connect, the second pole of described Organic Light Emitting Diode is electrically connected with second source line to receive second source voltage；Described storage electricity The first end held is electrically connected with described primary nodal point, and the second end of described storage capacitance is electrically connected with described secondary nodal point；Described The grid of the first transistor is electrically connected with reseting controling signal line to receive described reseting controling signal, described the first transistor First pole is electrically connected with reset voltage line to receive described resetting voltage, the second pole of described the first transistor and described first segment Point electrical connection；The grid of described transistor seconds electrically connects to receive the first scanning signal with the first scan signal line, and described First pole of two-transistor is electrically connected with described primary nodal point, and the second pole of described transistor seconds and described fourth node are electrically connected Connect；The grid of described third transistor is electrically connected with described first scan signal line to receive described first scanning signal, described First pole of third transistor is electrically connected with data signal line to receive described data signal, the second pole of described third transistor Electrically connect with described secondary nodal point；The grid of described 4th transistor is electrically connected with the second scan signal line to receive described second Scanning signal, the first pole of described 4th transistor is electrically connected with reference voltage line to receive described reference voltage, and the described 4th Second pole of transistor is electrically connected with described secondary nodal point；The grid of described 5th transistor is electrically connected with LED control signal line To receive described LED control signal, the first pole of described 5th transistor is electrically connected with described 3rd node, and the described 5th is brilliant Second pole of body pipe is electrically connected with described fourth node；The grid of described 6th transistor and the first scan signal line or the control that resets Holding wire processed electrically connects to receive described first scanning signal or described reseting controling signal, the first pole of described 6th transistor Electrically connect with described reset voltage line to receive described resetting voltage, the second pole of described 6th transistor and described 3rd node Electrical connection.

For example, in the image element circuit that the embodiment of the present disclosure provides, described driving transistor, described the first transistor, institute State transistor seconds, described third transistor, described 4th transistor, described 5th transistor and described 6th transistor equal For p-type transistor.

For example, in the image element circuit that the embodiment of the present disclosure provides, described driving transistor, described the first transistor, institute State transistor seconds, described third transistor, described 4th transistor, described 5th transistor and described 6th transistor equal For thin film transistor (TFT).

For example, the image element circuit that the embodiment of the present disclosure provides, also includes the second data write circuit, is configured to receive institute State reseting controling signal and described data signal and described data is write to described secondary nodal point according to described reseting controling signal Signal.

For example, in the image element circuit that the embodiment of the present disclosure provides, described reset circuit includes the first transistor, described threshold Value compensation circuit includes transistor seconds, and described first data write circuit includes third transistor, described reference voltage write Circuit includes the 4th transistor, and described emission control circuit includes the 5th transistor, and described initializing circuit includes the 6th crystal Pipe, described second data write circuit includes the 7th transistor.

For example, in the image element circuit that the embodiment of the present disclosure provides, the grid of described driving transistor and described first segment Point electrical connection, the first pole of described driving transistor electrically connects to receive the first supply voltage with the first power line, described driving Second pole of transistor is electrically connected with fourth node；First pole of described Organic Light Emitting Diode is electrically connected with described 3rd node Connect, the second pole of described Organic Light Emitting Diode is electrically connected with second source line to receive second source voltage；Described storage electricity The first end held is electrically connected with described primary nodal point, and the second end of described storage capacitance is electrically connected with described secondary nodal point；Described The grid of the first transistor is electrically connected with reseting controling signal line to receive described reseting controling signal, described the first transistor First pole is electrically connected with reset voltage line to receive described resetting voltage, the second pole of described the first transistor and described first segment Point electrical connection；The grid of described transistor seconds electrically connects to receive the first scanning signal with the first scan signal line, and described First pole of two-transistor is electrically connected with described primary nodal point, and the second pole of described transistor seconds is electrically connected with described 3rd node Connect；The grid of described third transistor is electrically connected with described first scan signal line to receive described first scanning signal, described First pole of third transistor is electrically connected with data signal line to receive described data signal, the second pole of described third transistor Electrically connect with described secondary nodal point；The grid of described 4th transistor is electrically connected with the second scan signal line to receive described second Scanning signal, the first pole of described 4th transistor is electrically connected with reference voltage line to receive described reference voltage, and the described 4th Second pole of transistor is electrically connected with described secondary nodal point；The grid of described 5th transistor is electrically connected with LED control signal line To receive described LED control signal, the first pole of described 5th transistor is electrically connected with described 3rd node, and the described 5th is brilliant Second pole of body pipe is electrically connected with described fourth node；The grid of described 6th transistor and the first scan signal line or the control that resets Holding wire processed electrically connects to receive described first scanning signal or described reseting controling signal, the first pole of described 6th transistor Electrically connect with described reset voltage line to receive described resetting voltage, the second pole of described 6th transistor and described 3rd node Electrical connection；The grid of described 7th transistor electrically connects to receive described reseting controling signal with reseting controling signal line, described First pole of the 7th transistor is electrically connected with data signal line to receive described data signal, the second pole of described 7th transistor Electrically connect with described secondary nodal point.

For example, in the image element circuit that the embodiment of the present disclosure provides, described driving transistor, described the first transistor, institute State transistor seconds, described third transistor, described 4th transistor, described 5th transistor, described 6th transistor and Described 7th transistor is p-type transistor.

For example, in the image element circuit that the embodiment of the present disclosure provides, described driving transistor, described the first transistor, institute State transistor seconds, described third transistor, described 4th transistor, described 5th transistor, described 6th transistor and Described 7th transistor is thin film transistor (TFT).

Embodiment of the disclosure also provides a kind of display floater, the image element circuit providing including disclosure any embodiment.

For example, the display floater that the embodiment of the present disclosure provides, also includes: data driver, is configured to described pixel Circuit provides described data signal；Scanner driver, is configured to provide described LED control signal, institute to described image element circuit State the first scanning signal, described second scanning signal and described reseting controling signal.

Embodiment of the disclosure also provides a kind of display device, the display floater providing including disclosure any embodiment.

The disclosure provides a kind of image element circuit, display floater and display device, display floater can be carried out resistance drop and Threshold voltage compensation, improves the uniformity of driving current, and then improves the uniformity that display floater shows, reduces leakage simultaneously Ensureing high-contrast during black state, and by adjusting fluorescent lifetime and accounting for a frame, electric current shows that the ratio of time period makes low Ensure under the conditions of GTG accurately to show.

Brief description

In order to be illustrated more clearly that the technical scheme of the embodiment of the present disclosure, below will be in embodiment or description of Related Art The accompanying drawing of required use be briefly described it should be apparent that, drawings in the following description merely relate to some of the disclosure Embodiment, restriction not of this disclosure.

Fig. 1 is a kind of one of schematic diagram of image element circuit that the embodiment of the present disclosure provides；

Fig. 2 is the two of the schematic diagram of a kind of image element circuit that the embodiment of the present disclosure provides；

Fig. 3 is the three of the schematic diagram of a kind of image element circuit that the embodiment of the present disclosure provides；

Fig. 4 is the four of the schematic diagram of a kind of image element circuit that the embodiment of the present disclosure provides；

Fig. 5 is the five of the schematic diagram of a kind of image element circuit that the embodiment of the present disclosure provides；

Fig. 6 is a kind of schematic diagram of display floater that the embodiment of the present disclosure provides；

Fig. 7 is a kind of schematic diagram of display device that the embodiment of the present disclosure provides；

Fig. 8 and Fig. 9 is the exemplary driver' s timing figure of the image element circuit as shown in Figure 3 that the embodiment of the present disclosure provides； And

Figure 10 and Figure 11 is the exemplary driver' s timing of the image element circuit as shown in Figure 5 that the embodiment of the present disclosure provides Figure.

Specific embodiment

Below in conjunction with accompanying drawing, the technical scheme in the embodiment of the present disclosure is clearly and completely described with reference to attached The non-limiting example embodiment that in figure illustrates and describes in detail in the following description, the example being more fully described below the disclosure is implemented Example and their various features and Advantageous details.It should be noted that the feature shown in figure is not required to be drawn to scale.This The open description eliminating known materials, assembly and Technology, thus do not make the example embodiment of the disclosure obscure.Given Example be only intended to the enforcement that is conducive to understanding disclosure example embodiment, and enable those skilled in the art real further Apply example embodiment.Thus, these examples are understood not to the restriction of the scope of embodiment of this disclosure.

Unless otherwise specifically defined, the technical term that the disclosure uses or scientific terminology should be disclosure art Inside there is the ordinary meaning that the personage of general technical ability is understood." first ", " second " and similar word used in the disclosure Language is not offered as any order, quantity or importance, and is used only to distinguish different ingredients.Additionally, in the disclosure In each embodiment, same or similar reference number represents same or similar component.

In Organic Light Emitting Diode (organic light-emitting diode, oled) display floater, can exist Resistance drop (ir drop) phenomenon, resistance drop is the i.e. electric current because the self-resistance partial pressure of wire in display floater causes During wire in display floater, according to Ohm's law, wire can produce certain voltage drop.Therefore, positioned at different positions The pixel cell put also is differed by resistance drop effect, and it is uneven that this can lead to display floater to show.Therefore, need Resistance drop in oled display floater is compensated.

And, in oled display floater, the threshold voltage of the driving transistor in each pixel cell is due to preparing work Skill may have differences each other, and the impact due to such as temperature change, and the threshold voltage of driving transistor also can produce The phenomenon of raw drift.Therefore, the difference of the threshold voltage of each driving transistor is likely to lead to display floater display uneven Even.Therefore, so also result in the need for threshold voltage is compensated.

And, there may be leakage current in oled pixel compensation circuit, still may have 0.01～0.03 nit in black state (nit) brightness, leads to obtain real black, therefore cannot realize high-contrast.

In addition, the data voltage that the GTG of oled display device distinguishes circuit driven controls, (the example when showing low GTG As when using at night), drive circuit is difficult to accomplish precise control under conditions of exporting low luma data voltage.

Embodiment of the disclosure provides a kind of image element circuit, display floater, display device and driving method, can be to display surface Plate carries out resistance drop and threshold voltage compensation, improves the uniformity of driving current, and then improves what display floater showed Uniformity, when reducing leakage current to ensure high-contrast during black state, and to account for a frame display by adjustment fluorescent lifetime simultaneously Between the ratio of section make to ensure accurately to show under the conditions of low GTG.

Embodiment of the disclosure provides a kind of image element circuit 100, as shown in figure 1, this image element circuit 100 includes: storage electricity Hold c, Organic Light Emitting Diode oled, driving transistor dt, emission control circuit 110, reset circuit 120, threshold compensation circuitry 130th, the first data write circuit 140, reference voltage write circuit 150 and initializing circuit 160.

For example, as shown in figure 1, storage capacitance c is included the first end being connected with primary nodal point n1 and connected with secondary nodal point n2 The second end connecing.Organic Light Emitting Diode oled includes the first pole being connected with the 3rd node n3.Driving transistor dt include with The grid that primary nodal point n1 connects；The voltage that driving transistor dt is configured to according to primary nodal point n1 controls organic light-emitting diodes Pipe oled lights.Emission control circuit 110 is configured to receive LED control signal em and controlled according to LED control signal em Organic Light Emitting Diode oled lights or turns off.Reset circuit 120 is configured to receive reseting controling signal reset and according to multiple Position control signal reset writes resetting voltage vint to primary nodal point n1.Threshold compensation circuitry 130 is configured to receive first sweeps Retouch signal gate and offset voltage is write to primary nodal point n1 according to the first scanning signal gate, described offset voltage is the first electricity Source voltage elvdd and threshold voltage vth sum elvdd+vth of described driving transistor.First data write circuit 140 is joined It is set to reception the first scanning signal gate data signal data and write to secondary nodal point n2 according to the first scanning signal gate Data signal data.Reference voltage write circuit 150 is configured to receive the second scanning signal scan and according to the second scanning letter Number scan writes reference voltage vref to secondary nodal point n2.Initializing circuit 160 is configured to receive the first scanning signal gate Or reseting controling signal reset being write to the 3rd node n3 according to the first scanning signal gate or reseting controling signal reset Initialization voltage vre.

For example, as shown in Fig. 2 in the image element circuit 100 that the embodiment of the present disclosure provides, initialization voltage vre is equal to multiple Position voltage vint.That is, resetting voltage can be simultaneously used for reset circuit 120 and initializing circuit 160, this set can To save voltage output port, simplify circuit, cost-effective.

For example, as shown in Fig. 2 in the image element circuit 100 that the embodiment of the present disclosure provides, Organic Light Emitting Diode oled is also Including the second pole, second pole of Organic Light Emitting Diode oled is electrically connected with second source line to receive second source voltage elvss.For example, the first of Organic Light Emitting Diode extremely anode, the second extremely negative electrode of Organic Light Emitting Diode.Initialization electricity The difference of pressure vre and second source voltage elvss is less than the bright voltage of Organic Light Emitting Diode oled.So, initializing circuit 160 to the 3rd node n3 write initialization voltage vre, can be to voltage (the i.e. sun of Organic Light Emitting Diode of the 3rd node n3 The voltage of pole) initialization, the difference of initialization voltage vre and second source voltage elvss is less than Organic Light Emitting Diode oled's Bright voltage can avoid abnormal luminous, the lifting display quality of Organic Light Emitting Diode after initialization.

For example, in the image element circuit 100 that the embodiment of the present disclosure provides, initialization voltage vre is less than or equal to second source Voltage elvss.For example, initialization voltage vre can make organic light emission two after initialization less than or equal to second source voltage elvss Pole pipe is in the state of reverse cut-off, prevents the abnormal luminous of Organic Light Emitting Diode, lifts display quality.

For example, as shown in figure 3, in the image element circuit 100 that the embodiment of the present disclosure provides, reset circuit 120 includes first Transistor t1, threshold compensation circuitry 130 includes transistor seconds t2, and the first data write circuit 140 includes third transistor t3, Reference voltage write circuit 150 includes the 4th transistor t4, and emission control circuit 110 includes the 5th transistor t5, initialization electricity Road 160 includes the 6th transistor t6.

For example, as shown in figure 3, the embodiment of the present disclosure provide image element circuit 100 in, the grid of driving transistor dt with Primary nodal point n1 electrically connects；First pole of driving transistor dt is electrically connected with the first power line to receive the first supply voltage elvdd；Second pole of driving transistor dt is electrically connected with fourth node n4.First pole and the 3rd of Organic Light Emitting Diode oled Node n3 electrically connects；Second pole of Organic Light Emitting Diode oled is electrically connected with second source line to receive second source voltage elvss.The first end of storage capacitance c is electrically connected with primary nodal point n1；Second end of storage capacitance c and secondary nodal point n2 are electrically connected Connect.The grid of the first transistor t1 is electrically connected with reseting controling signal line to receive reseting controling signal reset；The first transistor First pole of t1 is electrically connected with reset voltage line to receive resetting voltage vint；Second pole of the first transistor t1 and primary nodal point N1 electrically connects.The grid of transistor seconds t2 is electrically connected with the first scan signal line to receive the first scanning signal gate；Second First pole of transistor t2 is electrically connected with primary nodal point n1；Second pole of transistor seconds t2 is electrically connected with fourth node n4.The The grid of three transistor t3 is electrically connected with the first scan signal line to receive the first scanning signal gate；The of third transistor t3 One pole is electrically connected with data signal line with receiving data signal data；Second pole of third transistor t3 and secondary nodal point n2 are electrically connected Connect.The grid of the 4th transistor t4 is electrically connected with the second scan signal line to receive the second scanning signal scan；4th transistor First pole of t4 is electrically connected with reference voltage line to receive reference voltage vref；Second pole of the 4th transistor t4 and secondary nodal point N2 electrically connects.The grid of the 5th transistor t5 is electrically connected with LED control signal line to receive LED control signal em；5th is brilliant First pole of body pipe t5 is electrically connected with the 3rd node n3；Second pole of the 5th transistor t5 is electrically connected with fourth node n4.6th The grid of transistor t6 electrically connect with the first scan signal line or reseting controling signal line with receive the first scanning signal gate or Reseting controling signal reset；First pole of the 6th transistor t6 is electrically connected with reset voltage line to receive resetting voltage vint；The Second pole of six transistor t6 is electrically connected with the 3rd node n3.

It should be noted that first pole of the 6th transistor t6 includes but is not limited to shown in Fig. 3 and reset voltage line To receive the situation of resetting voltage vint, first pole of the 6th transistor t6 can also be electrically connected with initialization voltage line for electrical connection To receive initialization voltage vre.

For example, the embodiment of the present disclosure provide image element circuit 100 in, driving transistor dt, the first transistor t1, second Transistor t2, third transistor t3, the 4th transistor t4, the 5th transistor t5 and the 6th transistor t6 are p-type transistor.

For example, the embodiment of the present disclosure provide image element circuit 100 in, driving transistor dt, the first transistor t1, second Transistor t2, third transistor t3, the 4th transistor t4, the 5th transistor t5 and the 6th transistor t6 are film crystal Pipe, such as p-type thin film transistor.

It should be noted that the transistor adopting in embodiment of the disclosure can be all thin film transistor (TFT) or field effect is brilliant Body pipe or other characteristic identical switching devices.The source electrode of the transistor adopting here, drain electrode can be symmetrical in structure, So its source electrode, drain electrode can be as broad as long in structure.In embodiment of the disclosure, remove grid to distinguish transistor The two poles of the earth outside pole, directly describe wherein one extremely first pole, another extremely second pole, so in the embodiment of the present disclosure all Or the first pole of portion of transistor and the second pole can exchange as needed.For example, the crystal described in the embodiment of the present disclosure The first of pipe can be extremely source electrode, and second can be extremely drain electrode；Or, the first of transistor extremely drains, the second extremely source electrode. Additionally, distinguishing and transistor can be divided into N-shaped and p-type transistor according to the characteristic of transistor, embodiment of the disclosure is to drive Transistor dt, the first transistor t1, transistor seconds t2, third transistor t3, the 4th transistor t4, the 5th transistor t5 and 6th transistor t6 illustrates as a example being p-type transistor.Based on the disclosure to the description of this implementation and teaching, ability Domain those of ordinary skill can be readily apparent that under the premise of not making creative work the embodiment of the present disclosure adopts n-type transistor Or the implementation of N-shaped and p-type transistor combination, therefore, these implementations are also in the protection domain of the disclosure.

For example, as shown in figure 4, the image element circuit 100 that the embodiment of the present disclosure provides also includes the second data write circuit 170.Second data write circuit 170 is configured to receive reseting controling signal reset data signal data and according to reset Control signal reset writes data signal data to secondary nodal point n2.

For example, as shown in figure 5, in the image element circuit 100 that the embodiment of the present disclosure provides, reset circuit 120 includes first Transistor t1, threshold compensation circuitry 130 includes transistor seconds t2, and the first data write circuit 140 includes third transistor t3, Reference voltage write circuit 150 includes the 4th transistor t4, and emission control circuit 110 includes the 5th transistor t5, initialization electricity Road 160 includes the 6th transistor t6, and the second data write circuit 170 includes the 7th transistor t7.

For example, as shown in figure 5, the embodiment of the present disclosure provide image element circuit 100 in, the grid of driving transistor dt with Primary nodal point n1 electrically connects；First pole of driving transistor dt is electrically connected with the first power line to receive the first supply voltage elvdd；Second pole of driving transistor dt is electrically connected with fourth node n4.First pole and the 3rd of Organic Light Emitting Diode oled Node n3 electrically connects；Second pole of Organic Light Emitting Diode oled is electrically connected with second source line to receive second source voltage elvss.The first end of storage capacitance c is electrically connected with primary nodal point n1；Second end of storage capacitance c and secondary nodal point n2 are electrically connected Connect.The grid of the first transistor t1 is electrically connected with reseting controling signal line to receive reseting controling signal reset；The first transistor First pole of t1 is electrically connected with reset voltage line to receive resetting voltage vint；Second pole of the first transistor t1 and primary nodal point N1 electrically connects.The grid of transistor seconds t2 is electrically connected with the first scan signal line to receive the first scanning signal gate；Second First pole of transistor t2 is electrically connected with primary nodal point n1；Second pole of transistor seconds t2 is electrically connected with fourth node n4.The The grid of three transistor t3 is electrically connected with the first scan signal line to receive the first scanning signal gate；The of third transistor t3 One pole is electrically connected with data signal line with receiving data signal data；Second pole of third transistor t3 and secondary nodal point n2 are electrically connected Connect.The grid of the 4th transistor t4 is electrically connected with the second scan signal line to receive the second scanning signal scan；4th transistor First pole of t4 is electrically connected with reference voltage line to receive reference voltage vref；Second pole of the 4th transistor t4 and secondary nodal point N2 electrically connects.The grid of the 5th transistor t5 is electrically connected with LED control signal line to receive LED control signal em；5th is brilliant First pole of body pipe t5 is electrically connected with the 3rd node n3；Second pole of the 5th transistor t5 is electrically connected with fourth node n4.6th The grid of transistor t6 electrically connect with the first scan signal line or reseting controling signal line with receive the first scanning signal gate or Reseting controling signal reset；First pole of the 6th transistor t6 is electrically connected with reset voltage line to receive resetting voltage vint；The Second pole of six transistor t6 is electrically connected with the 3rd node n3.The grid of the 7th transistor t7 is electrically connected with reseting controling signal line To receive reseting controling signal reset；First pole of the 7th transistor t7 is electrically connected with data signal line with receiving data signal data；Second pole of the 7th transistor t7 is electrically connected with secondary nodal point n2.

It should be noted that first pole of the 6th transistor t6 includes but is not limited to shown in Fig. 5 and reset voltage line To receive the situation of resetting voltage vint, first pole of the 6th transistor t6 can also be electrically connected with initialization voltage line for electrical connection To receive initialization voltage vre.

For example, the embodiment of the present disclosure provide image element circuit 100 in, driving transistor dt, the first transistor t1, second Transistor t2, third transistor t3, the 4th transistor t4, the 5th transistor t5, the 6th transistor t6 and the 7th transistor t7 It is p-type transistor.

For example, the embodiment of the present disclosure provide image element circuit 100 in, driving transistor dt, the first transistor t1, second Transistor t2, third transistor t3, the 4th transistor t4, the 5th transistor t5, the 6th transistor t6 and the 7th transistor t7 It is thin film transistor (TFT), such as p-type thin film transistor.

Embodiment of the disclosure also provides a kind of display floater 10, as shown in fig. 6, display floater 10 to include the disclosure arbitrary The image element circuit 100 that embodiment provides.

For example, display floater 10 includes multiple image element circuits 100 in matrix arrangement, and each image element circuit 100 is used for driving Move at least one sub-pixel for emitting light, what this at least one sub-pixel was sent can be HONGGUANG, green glow, blue light, also or be white Light etc..

For example, as shown in fig. 6, the display floater 10 that the embodiment of the present disclosure provides also includes: data driver 11, scanning are driven Dynamic device 12 and controller 13.The instruction that data driver 11 is configured to according to controller 13 provides data to image element circuit 100 Signal data；The instruction that scanner driver 12 is configured to according to controller 13 provides LED control signal to image element circuit 100 Em, the first scanning signal gate, the second scanning signal scan and reseting controling signal reset etc..

For example, display floater 10 also includes data signal line, LED control signal line, the first scan signal line, second sweeps Retouch holding wire and reseting controling signal line (not shown in Fig. 6).Data driver 11 is to image element circuit by data signal line 100 offer data signals data；Scanner driver 12 passes through LED control signal line, the first scan signal line respectively, second sweeps Retouch holding wire and reseting controling signal line to each image element circuit 100 provide LED control signal em, the first scanning signal gate, Second scanning signal scan and reseting controling signal reset etc..

For example, display floater 10 also include power supply (voltage source or current source, in figure is not shown), the first power line, second Power line, reference voltage line and reset voltage line (not shown in Fig. 6), described power supply is configured to by the first power supply Line, second source line, reference voltage line and reset voltage line to image element circuit 100 provide the first supply voltage elvdd, second Supply voltage elvss, reference voltage vref and resetting voltage vint etc..

Embodiment of the disclosure also provides a kind of display device 1, as shown in fig. 7, display device 1 includes the arbitrary reality of the disclosure The display floater 10 of example offer is provided.

For example, the display device that the embodiment of the present disclosure provides can include mobile phone, panel computer, television set, display, pen Remember any product with display function such as this computer, DPF, navigator or part.

Embodiment of the disclosure also provides a kind of driving method of image element circuit 100 as shown in Figure 3.For example, as Fig. 8 institute Show, show in the time period in a frame, this driving method includes reseting stage t1, data write and valve value compensation stage t2, pressure drop Compensated stage t3 and glow phase t4.

In reseting stage t1, arranging LED control signal em is to close voltage, and setting reseting controling signal reset is to open Voltage, setting the first scanning signal gate is to close voltage, and setting the second scanning signal scan is cut-in voltage, setting data letter Number data is invalid data signal.

In data write and valve value compensation stage t2, setting LED control signal em is to close voltage, and setting resets and controls Signal reset is to close voltage, and setting the first scanning signal gate is cut-in voltage, and setting the second scanning signal scan is to close Voltage, setting data signal data is valid data signal.

In voltage-drop compensation stage t3, arranging LED control signal em is to close voltage, and setting reseting controling signal reset is Close voltage, setting the first scanning signal gate is to close voltage, and setting the second scanning signal scan is cut-in voltage, arranges number It is believed that number data is invalid data signal.

In glow phase t4, setting LED control signal em is cut-in voltage, and setting reseting controling signal reset is to close Voltage, setting the first scanning signal gate is to close voltage, and setting the second scanning signal scan is cut-in voltage, setting data letter Number data is invalid data signal.

For example, the cut-in voltage in the embodiment of the present disclosure refers to make the electricity of respective transistor first pole and second level conducting Pressure, closes voltage and refers to make the voltage that the first pole of respective transistor and the second level disconnect.When transistor is p-type transistor When, cut-in voltage is low-voltage (for example, 0v), and closing voltage is high voltage (for example, 5v)；When transistor is for n-type transistor, Cut-in voltage is high voltage (for example, 5v), and closing voltage is low-voltage (for example, 0v).Drive waveforms shown in Fig. 8 to Figure 11 are equal Taking p-type transistor as a example illustrate, that is, cut-in voltage is low-voltage (for example, 0v), close voltage for high voltage (for example, 5v).Invalid data signal is, for example, low voltage signal (for example, 0v), and valid data signal for example, includes light-emitting data information Signal, illustrate in Fig. 8 to Figure 11 taking high voltage signal as a example.

For example, with reference to Fig. 3 and Fig. 8, in reseting stage t1, LED control signal em is to close voltage, reseting controling signal Reset is cut-in voltage, and the first scanning signal gate is to close voltage, and the second scanning signal scan is cut-in voltage, and data is believed Number data is invalid data signal.Now, the first transistor t1 and the 4th transistor t4 is in the conduction state, transistor seconds T2, third transistor t3 and the 5th transistor t5 are closed.Resetting voltage vint is transferred to by the first transistor t1 Reference voltage vref is transferred to secondary nodal point n2 by one node n1, the 4th transistor t4.That is, reset circuit receives to reset and controls letter Number reset simultaneously writes resetting voltage vint according to reseting controling signal reset to primary nodal point n1；Reference voltage write circuit connects Receive the second scanning signal scan and reference voltage vref is write to secondary nodal point n2 according to the second scanning signal scan.

In data write and valve value compensation stage t2, LED control signal em is to close voltage, reseting controling signal reset For closing voltage, the first scanning signal gate is cut-in voltage, and the second scanning signal scan is to close voltage, data signal data For valid data signal.Now, transistor seconds t2 and third transistor t3 are in the conduction state, the first transistor t1, the 4th Transistor t4 and the 5th transistor t5 is closed.Now, third transistor t3 is by the voltage vdata of valid data signal It is transferred to secondary nodal point n2, the voltage of secondary nodal point n2 turns to vdata by the vref change of reseting stage t1, i.e. the first data is write Enter circuit to receive the first scanning signal gate data signal data and write to secondary nodal point n2 according to the first scanning signal gate Enter data signal data.Driving transistor dt is connected into diode structure, the electricity of primary nodal point n1 by transistor seconds t2 conducting Press as elvdd+vth, wherein, elvdd is the first supply voltage, and vth is the threshold voltage of driving transistor, i.e. valve value compensation Circuit receives the first scanning signal gate and writes offset voltage, described benefit according to the first scanning signal gate to primary nodal point n1 Repay threshold voltage vth sum elvdd+vth that voltage is the first supply voltage elvdd and described driving transistor.For example, here In the stage, the voltage difference at storage capacitance c two ends is elvdd+vth-vdata.

In voltage-drop compensation stage t3, LED control signal em is to close voltage, and reseting controling signal reset is to close electricity Pressure, the first scanning signal gate is to close voltage, and the second scanning signal scan is cut-in voltage, and data signal data is invalid number It is believed that number.4th transistor t4 is in the conduction state, the first transistor t1, transistor seconds t2, third transistor t3 and the 5th Transistor t5 is closed.Now, reference voltage vref is transferred to secondary nodal point n2 by the 4th transistor t4 again, due to The boot strap (i.e. the voltage at storage capacitance two ends will not be mutated) of storage capacitance c, the voltage of primary nodal point n1 is changed into elvdd+ vth-vdata+vref.

In glow phase t4, LED control signal em is cut-in voltage, and reseting controling signal reset is to close voltage, the Scan signal gate be close voltage, the second scanning signal scan be cut-in voltage, data signal data be invalid number it is believed that Number.4th transistor t4 and the 5th transistor are in the conduction state, the first transistor t1, transistor seconds t2 and third transistor T3 is closed.The voltage of primary nodal point n1 is maintained at elvdd+vth-vdata+vref, and glow current ioled passes through to drive Dynamic transistor dt and the 5th transistor t5 flows into Organic Light Emitting Diode oled, and Organic Light Emitting Diode oled lights.That is, light Control circuit receives LED control signal em and controls Organic Light Emitting Diode oled to light according to LED control signal em.Luminous Electric current ioled meets following saturation current formula:

k(vgs-vth)²=k (elvdd+vth-vdata+vref-elvdd-vth)²=k (vref-vdata)²

Wherein,μ_nFor the channel mobility of driving transistor, cox is driving transistor unit plane Long-pending channel capacitance, w and l is respectively channel width and the channel length of driving transistor, and vgs is the grid source electricity of driving transistor Pressure (grid voltage of driving transistor and the difference of source voltage).

By seeing in above formula that the electric current flowing through oled is unrelated with the threshold voltage of driving transistor dt, with elvdd's Voltage is also unrelated.Therefore, on the extraordinary threshold voltage that compensate for driving transistor dt of this image element circuit and elvdd cabling Resistance drop (ir drop).

For example, when the grid of the 6th transistor t6 electrically connects reception the first scanning signal gate with the first scan signal line When, in data write and valve value compensation stage t2, the 6th transistor t6 is in the conduction state, and the current potential of the 3rd node n3 is initial Change voltage vre (for example, initialization voltage vre is equal to resetting voltage vint).For example, initialization voltage vre and second source electricity The difference of pressure elvss is less than the bright voltage of Organic Light Emitting Diode oled, and for example, initialization voltage vre is less than or equal to second Supply voltage elvss, can prevent the abnormal luminous of Organic Light Emitting Diode, lift display quality.In glow phase t4, Six transistor t6 are closed, and when showing black picture, the voltage of the 3rd node n3 point can be by the 6th transistor t6's Leakage current flows out the low-light level it is ensured that during black picture, improves display effect.

For example, when the grid of the 6th transistor t6 electrically connects reception reseting controling signal reset with reseting controling signal line When, in reseting stage t1, the 6th transistor t6 is in the conduction state, and the current potential of the 3rd node n3 is initialization voltage vre (example As initialization voltage vre is equal to resetting voltage vint).For example, initialization voltage vre is little with the difference of second source voltage elvss In the bright voltage of Organic Light Emitting Diode oled, and for example, initialization voltage vre is less than or equal to second source voltage elvss, The abnormal luminous of Organic Light Emitting Diode can be prevented, lift display quality.In glow phase t4, the 6th transistor t6 is in Closed mode, when showing black picture, the voltage of the 3rd node n3 point can be flowed out by the leakage current of the 6th transistor t6, protects Demonstrate,prove low-light level during black picture, improve display effect.

For example, according to mentioned above, initializing circuit receives the first scanning signal gate or reseting controling signal reset simultaneously Initialization voltage vre is write to the 3rd node n3 according to the first scanning signal gate or reseting controling signal reset.Initialization electricity Pressure vre is for example equal to resetting voltage vint.

For example, in the driving method that the embodiment of the present disclosure provides, the duration of glow phase t4 accounts for a frame display time period f Ratio can be conditioned.As such, it is possible to account for, by adjusting the duration of glow phase t4, the ratio control that a frame shows time period f Brightness.

For example, shown by controlling the duration that the scanner driver 12 in display floater realizes adjusting glow phase t4 to account for a frame Show the ratio of time period f.

For example, the driving method that the embodiment of the present disclosure provides, as shown in figure 9, showing in time period f in a frame, also includes Luminous continuation phase, luminous continuation phase includes at least one and closes sub-stage and at least one luminous sub-stage.For example, light Continuation phase includes n and closes sub-stage (t51 ... t5n) and n luminous sub-stage (t61 ... t6n).Closing sub- rank Section, setting LED control signal em is to close voltage, and setting reseting controling signal reset is to close voltage, setting first scanning Signal gate is to close voltage, and setting the second scanning signal scan is cut-in voltage, and setting data signal data is invalid data Signal；In luminous sub-stage, setting LED control signal em is cut-in voltage, and setting reseting controling signal reset is to close electricity Pressure, setting the first scanning signal gate is to close voltage, and setting the second scanning signal scan is cut-in voltage, arranges data signal Data is invalid data signal.This set can a frame show make Organic Light Emitting Diode in luminance in the time period and Repeatedly switch between non-light emitting state, that is, increased the frequency of organic light-emitting diode, reduce or avoid because vision temporary Stay the scintillation that effect leads to.

For example, show that including three in the time period closes sub-stage and three luminous sub-stages, i.e. n=3 in a frame, you can Preferably improve scintillation.

For example, in the driving method that the embodiment of the present disclosure provides, the duration of glow phase t4 and all luminous sub-stage Total duration sum account for one frame show time period f ratio can be conditioned.

For example, in the driving method that the embodiment of the present disclosure provides, the duration that each closes sub-stage is equal to reseting stage The duration of t1, data write and the duration of valve value compensation stage t2 and the duration sum of voltage-drop compensation stage t3, each luminous son The duration in stage is equal to the duration of glow phase t4.Appearance when this set can ensure that Organic Light Emitting Diode lights every time With and the interval between each light-emitting period is equal, is easy to simplify sequencing contro it is ensured that circuit stability.

Embodiment of the disclosure also provides a kind of driving method of image element circuit 100 as shown in Figure 5, in a frame display Between in section, including reseting stage t1, data write and valve value compensation stage t2, voltage-drop compensation stage t3 and glow phase t4.

In reseting stage t1, arranging LED control signal em is to close voltage, and setting reseting controling signal reset is to open Voltage, setting the first scanning signal gate is to close voltage, and setting the second scanning signal scan is to close voltage, setting data letter Number data is valid data signal.

For example, with reference to Fig. 5 and Figure 10, in reseting stage t1, LED control signal em is to close voltage, reseting controling signal Reset is cut-in voltage, and the first scanning signal gate is to close voltage, and the second scanning signal scan is to close voltage, and data is believed Number data is valid data signal.Now, the first transistor t1 and the 7th transistor t7 is in the conduction state, transistor seconds T2, third transistor t3, the 4th transistor t4 and the 5th transistor t5 are closed.The first transistor t1 is by resetting voltage Vint is transferred to primary nodal point n1, and the voltage vdata of valid data signal is transferred to secondary nodal point n2 by the 7th transistor t7. That is, reset circuit receives reseting controling signal reset and is resetted to primary nodal point n1 write according to reseting controling signal reset electric Pressure vint；Second data write circuit receives reseting controling signal reset data signal data and according to reseting controling signal Reset writes data signal data to secondary nodal point n2.

In data write and valve value compensation stage t2, LED control signal em is to close voltage, reseting controling signal reset For closing voltage, the first scanning signal gate is cut-in voltage, and the second scanning signal scan is to close voltage, data signal data For valid data signal.Now, transistor seconds t2 and third transistor t3 are in the conduction state, the first transistor t1, the 4th Transistor t4, the 5th transistor t5 and the 7th transistor t7 are closed.Now, third transistor t3 continues significant figure It is believed that number voltage vdata be transferred to secondary nodal point n2, i.e. first data write circuit receive the first scanning signal gate sum It is believed that number data and according to the first scanning signal gate to secondary nodal point n2 write data signal data.Transistor seconds t2 turns on Driving transistor dt is connected into diode structure, the voltage of primary nodal point n1 is elvdd+vth, wherein, elvdd is the first electricity Source voltage, vth is the threshold voltage of driving transistor, i.e. threshold compensation circuitry receives the first scanning signal gate and according to the Scan signal gate carries out threshold voltage compensation to the voltage of primary nodal point n1.In this stage, the voltage at storage capacitance c two ends For elvdd+vth-vdata.

In voltage-drop compensation stage t3, LED control signal em is to close voltage, and reseting controling signal reset is to close electricity Pressure, the first scanning signal gate is to close voltage, and the second scanning signal scan is cut-in voltage, and data signal data is invalid number It is believed that number.4th transistor t4 is in the conduction state, the first transistor t1, transistor seconds t2, third transistor t3, the 5th crystalline substance Body pipe t5 and the 7th transistor t7 is closed.Now, reference voltage vref is transferred to by the 4th transistor t4 again Two node n2, due to the boot strap (i.e. the voltage at storage capacitance two ends will not be mutated) of storage capacitance c, the electricity of primary nodal point n1 Buckling is elvdd+vth-vdata+vref.

In glow phase t4, LED control signal em is cut-in voltage, and reseting controling signal reset is to close voltage, the Scan signal gate be close voltage, the second scanning signal scan be cut-in voltage, data signal data be invalid number it is believed that Number.4th transistor t4, the 5th transistor and the 7th transistor t7 are in the conduction state, the first transistor t1, transistor seconds T2 and third transistor t3 are closed.The voltage of primary nodal point n1 is maintained at elvdd+vth-vdata+vref, lights Electric current ioled passes through driving transistor dt and the 5th transistor t5 flows into Organic Light Emitting Diode oled, Organic Light Emitting Diode Oled lights.That is, emission control circuit receives LED control signal em and controls organic light emission two according to LED control signal em Pole pipe oled lights.Glow current ioled meets following saturation current formula:

k(vgs-vth)²=k (elvdd+vth-vdata+vref-elvdd-vth)²=k (vref-vdata)²

For example, compared to the driving method of drive circuit shown in Fig. 3, the driving method of drive circuit shown in Fig. 5 is resetting Stage t1 starts to write data signal to secondary nodal point n2, increased the time of data signal write, prevents reset rank simultaneously When section t1 writes to data and valve value compensation stage t2 changes, the excessive impact that circuit is caused of secondary nodal point n2 change in voltage, Be conducive to stablizing of circuit.

For example, the driving method that the embodiment of the present disclosure provides, as shown in figure 11, shows in time period f in a frame, also includes Luminous continuation phase, luminous continuation phase includes at least one and closes sub-stage and at least one luminous sub-stage.For example, light Continuation phase includes n and closes sub-stage (t51 ... t5n) and n luminous sub-stage (t61 ... t6n).Closing sub- rank Section, setting LED control signal em is to close voltage, and setting reseting controling signal reset is to close voltage, setting first scanning Signal gate is to close voltage, and setting the second scanning signal scan is cut-in voltage, and setting data signal data is invalid data Signal；In luminous sub-stage, setting LED control signal em is cut-in voltage, and setting reseting controling signal reset is to close electricity Pressure, setting the first scanning signal gate is to close voltage, and setting the second scanning signal scan is cut-in voltage, arranges data signal Data is invalid data signal.This set can a frame show make Organic Light Emitting Diode in luminance in the time period and Repeatedly switch between non-light emitting state, that is, increased the frequency of organic light-emitting diode, reduce or avoid because vision temporary Stay the scintillation that effect leads to.

Although above having used general explanation and specific embodiment, the disclosure is made with detailed description, On the basis of the embodiment of the present disclosure, it can be made some modifications or improvements, this is apparent to those skilled in the art 's.Therefore, these modifications or improvements on the basis of without departing from disclosure spirit, belong to what the disclosure claimed Scope.

Claims

1. a kind of image element circuit is it is characterised in that include:

Storage capacitance, including the first end being connected with primary nodal point and the second end being connected with secondary nodal point；

Organic Light Emitting Diode, including the first pole being connected with the 3rd node；

Driving transistor, including the grid being connected with described primary nodal point, wherein, described driving transistor is configured to according to institute The voltage stating primary nodal point controls described organic light-emitting diode；

Emission control circuit, is configured to receive LED control signal and control described organic according to described LED control signal Optical diode lights or turns off；

Reset circuit, is configured to receive reseting controling signal and write to described primary nodal point according to described reseting controling signal Resetting voltage；

Threshold compensation circuitry, is configured to receive the first scanning signal and according to described first scanning signal to described primary nodal point Write offset voltage, wherein, described offset voltage is the threshold voltage sum of the first supply voltage and described driving transistor；

First data write circuit, is configured to receive the first scanning signal data signal and according to described first scanning signal Write described data signal to described secondary nodal point；

Reference voltage write circuit, is configured to receive the second scanning signal and according to described second scanning signal to described second Node writes reference voltage；And

Initializing circuit, is configured to receive described first scanning signal or described reseting controling signal and sweep according to described first Retouch signal or described reseting controling signal and write initialization voltage to the 3rd node.

2. image element circuit according to claim 1 is it is characterised in that described initialization voltage is equal to described resetting voltage.

3. image element circuit according to claim 1 is it is characterised in that described Organic Light Emitting Diode also includes the second pole, Second pole of described Organic Light Emitting Diode is electrically connected with second source line to receive second source voltage, described organic light emission two The first of pole pipe extremely anode, the second extremely negative electrode of described Organic Light Emitting Diode, described initialization voltage and described second The difference of supply voltage is less than the bright voltage of described Organic Light Emitting Diode.

4. image element circuit according to claim 3 is it is characterised in that described initialization voltage is less than or equal to described second electricity Source voltage.

5. the image element circuit according to any one of claim 1-4 is it is characterised in that described reset circuit includes first crystal Pipe, described threshold compensation circuitry includes transistor seconds, and described first data write circuit includes third transistor, described reference Voltage write circuit includes the 4th transistor, and described emission control circuit includes the 5th transistor, and described initializing circuit includes 6th transistor.

6. image element circuit according to claim 5 it is characterised in that

The grid of described driving transistor is electrically connected with described primary nodal point, the first pole of described driving transistor and the first power supply Line electrically connects to receive the first supply voltage, and the second pole of described driving transistor is electrically connected with fourth node；

First pole of described Organic Light Emitting Diode is electrically connected with described 3rd node, the second pole of described Organic Light Emitting Diode Electrically connect with second source line to receive second source voltage；

The first end of described storage capacitance is electrically connected with described primary nodal point, the second end of described storage capacitance and described second section Point electrical connection；

The grid of described the first transistor electrically connects to receive described reseting controling signal with reseting controling signal line, and described first First pole of transistor is electrically connected with reset voltage line to receive described resetting voltage, the second pole of described the first transistor and institute State primary nodal point electrical connection；

The grid of described transistor seconds is electrically connected with the first scan signal line to receive the first scanning signal, described second crystal First pole of pipe is electrically connected with described primary nodal point, and the second pole of described transistor seconds is electrically connected with described fourth node；

The grid of described third transistor is electrically connected with described first scan signal line to receive described first scanning signal, described First pole of third transistor is electrically connected with data signal line to receive described data signal, the second pole of described third transistor Electrically connect with described secondary nodal point；

The grid of described 4th transistor electrically connects to receive described second scanning signal with the second scan signal line, and the described 4th First pole of transistor is electrically connected with reference voltage line to receive described reference voltage, the second pole of described 4th transistor and institute State secondary nodal point electrical connection；

The grid of described 5th transistor electrically connects to receive described LED control signal with LED control signal line, and the described 5th First pole of transistor is electrically connected with described 3rd node, and the second pole of described 5th transistor is electrically connected with described fourth node Connect；

The grid of described 6th transistor is electrically connected with the first scan signal line or reseting controling signal line to receive described first Scanning signal or described reseting controling signal, the first pole of described 6th transistor is electrically connected with described reset voltage line to receive Described resetting voltage, the second pole of described 6th transistor is electrically connected with described 3rd node.

7. image element circuit according to claim 5 is it is characterised in that described driving transistor, described the first transistor, institute State transistor seconds, described third transistor, described 4th transistor, described 5th transistor and described 6th transistor equal For p-type transistor.

8. image element circuit according to claim 5 is it is characterised in that described driving transistor, described the first transistor, institute State transistor seconds, described third transistor, described 4th transistor, described 5th transistor and described 6th transistor equal For thin film transistor (TFT).

9. the image element circuit according to any one of claim 1-4 is it is characterised in that also include the second data write circuit, It is configured to receive described reseting controling signal and described data signal and according to described reseting controling signal to described second section Point writes described data signal.

10. image element circuit according to claim 9 is it is characterised in that described reset circuit includes the first transistor, described Threshold compensation circuitry includes transistor seconds, and described first data write circuit includes third transistor, and described reference voltage is write Enter circuit and include the 4th transistor, described emission control circuit includes the 5th transistor, it is brilliant that described initializing circuit includes the 6th Body pipe, described second data write circuit includes the 7th transistor.

11. image element circuits according to claim 10 it is characterised in that

The grid of described transistor seconds is electrically connected with the first scan signal line to receive the first scanning signal, described second crystal First pole of pipe is electrically connected with described primary nodal point, and the second pole of described transistor seconds is electrically connected with described 3rd node；

The grid of described 6th transistor is electrically connected with the first scan signal line or reseting controling signal line to receive described first Scanning signal or described reseting controling signal, the first pole of described 6th transistor is electrically connected with described reset voltage line to receive Described resetting voltage, the second pole of described 6th transistor is electrically connected with described 3rd node；

The grid of described 7th transistor electrically connects to receive described reseting controling signal with reseting controling signal line, and the described 7th First pole of transistor is electrically connected with data signal line to receive described data signal, the second pole of described 7th transistor and institute State secondary nodal point electrical connection.

12. image element circuits according to claim 10 it is characterised in that described driving transistor, described the first transistor, Described transistor seconds, described third transistor, described 4th transistor, described 5th transistor, described 6th transistor with And described 7th transistor is p-type transistor.

13. image element circuits according to claim 10 it is characterised in that described driving transistor, described the first transistor, Described transistor seconds, described third transistor, described 4th transistor, described 5th transistor, described 6th transistor with And described 7th transistor is thin film transistor (TFT).

A kind of 14. display floaters are it is characterised in that include the image element circuit as described in any one of claim 1-13.

15. display floaters according to claim 14 are it is characterised in that also include:

Data driver, is configured to provide described data signal to described image element circuit；

Scanner driver, is configured to provide described LED control signal, described first scanning signal, institute to described image element circuit State the second scanning signal and described reseting controling signal.

A kind of 16. display devices are it is characterised in that include the display floater as described in claims 14 or 15.