CN205899373U - Debugging platform of executor main control board - Google Patents

Abstract

The utility model discloses a debugging platform of executor main control board relates to electric actuator equipment technical field, include: a current output circuit for simulating the preset electric current of central control room, a switching value control circuit for simulating central control room switching value signal, a motor control circuit and position acquisition circuit for simulation executive mechanism, a preset disconnected signal circuit of simulation for simulating go up spacing and lower spacing and switching value and analog quantity switching, and the model is ATMEGA168's CPU, switching value control circuit, motor control circuit and position acquisition circuit all set up in debugging platform, switching value control circuit, position acquisition circuit all are connected with executor main control board electricity. Set signal or switching value signal input to main control board are passed through to this patent, and the control motor moved after the signal was gathered to the main control board to come the spotting through the potentiometre, each item function that can conveniently debug the main control board like this, each action of simulation executive ware improves operating personnel's work efficiency.

Description

The debugger of executor's master control borad

Technical field

This utility model is related to YE equipment technical field, more particularly to a kind of debugging of executor's master control borad Platform.

Background technology

It is known that executor (final controlling element) is to receive in automation equipment to control Information the device to controll plant applying control action.Executor is also directly to change to manipulate in control system forward path to become The instrument of amount, is made up of actuator and governor motion.Wherein: the master control borad of executor is carried out one of vitals of device, Found by practice: traditional master control borad cannot determine whether various functions are normal after the completion of producing.

Utility model content

The technical problems to be solved in the utility model is: provides a kind of debugger of executor's master control borad, this executor master The debugger of control plate can conveniently debug the various functions of master control borad, each action of simulation executing, improves operator's Work efficiency.

This utility model is adopted the technical scheme that by solving technical problem present in known technology:

A kind of debugger of executor's master control borad, at least includes:

Give the current output circuit of electric current for simulating Central Control Room；

For simulating the digital output modul circuit of Central Control Room on-off model；

For simulating circuit for controlling motor and the station acquisition circuit of actuator；

Simulation for simulating upper limit and lower limit and switching value and analog quantity switching gives break signal circuit；

And the cpu of model atmega168；Wherein: described digital output modul circuit, circuit for controlling motor and position are adopted Collector may be contained within debugger；Described digital output modul circuit, station acquisition circuit are all electrically connected with executor's master control borad.

This utility model has the advantages and positive effects that:

By adopting technique scheme, this patent is input to master control borad, master control by Setting signal or on-off model Plate collects controlled motor action after signal, and determines position by potentiometer；So can conveniently debug each of master control borad Item function, each action of simulation executing, improves the work efficiency of operator.

Brief description

Fig. 1 is the cpu electric operation control circuit figure in this utility model preferred embodiment；

Fig. 2 is the structure chart of the current output circuit in this utility model preferred embodiment；

Fig. 3 is the part figure of this utility model preferred embodiment.

Specific embodiment

For utility model content of the present utility model, feature and effect can be further appreciated that, hereby enumerate following examples, and Cooperation accompanying drawing describes in detail as follows:

Refer to Fig. 1, Fig. 2 and Fig. 3, a kind of debugger of executor's master control borad, comprising:

Give the current output circuit of electric current for simulating Central Control Room；

For simulating the digital output modul circuit of Central Control Room on-off model；

For simulating circuit for controlling motor and the station acquisition circuit of actuator；

Simulation for simulating upper limit and lower limit and switching value and analog quantity switching gives break signal circuit；

And the cpu of model atmega168；Wherein: described digital output modul circuit, circuit for controlling motor and position are adopted Collector may be contained within debugger；Described digital output modul circuit, station acquisition circuit are all electrically connected with executor's master control borad.

By adopting technique scheme, this patent is input to master control borad, master control by Setting signal or on-off model Plate collects controlled motor action after signal, and determines position by potentiometer；So can conveniently debug each of master control borad Item function, each action of simulation executing, improves the work efficiency of operator.

By adopting technique scheme, this patent has following functions:

1st, given value of current module, for simulating the given value of current of Central Control Room；Schematic diagram is shown in Fig. 1 and Fig. 2；

2nd, digital output modul, the output switch parameter for simulating Central Control Room；Schematic diagram is shown in Fig. 3；

3rd, potentiometer, circuit for controlling motor and motor, with the motor control with simulation actuator, and station acquisition；Former Reason figure is shown in Fig. 3；

4th, the relay output control display lamp of master control borad；Schematic diagram is shown in Fig. 3；

5th, given break signal, simulation upper limit and lower limit are simulated, and the switching of switching value and analog quantity；Schematic diagram is shown in Fig. 3.

Above embodiment of the present utility model is described in detail, but described content has been only of the present utility model preferable Embodiment is it is impossible to be considered for limiting practical range of the present utility model.All according to this utility model application range made equal Deng change and improvement etc., all should still belong within patent covering scope of the present utility model.

Claims (1)

1. a kind of debugger of executor's master control borad it is characterised in that: at least include:

Give the current output circuit of electric current for simulating Central Control Room；

For simulating the digital output modul circuit of Central Control Room on-off model；

For simulating circuit for controlling motor and the station acquisition circuit of actuator；

Simulation for simulating upper limit and lower limit and switching value and analog quantity switching gives break signal circuit；

And the cpu of model atmega168；Wherein: described digital output modul circuit, circuit for controlling motor and station acquisition electricity Road may be contained within debugger；Described digital output modul circuit, station acquisition circuit are all electrically connected with executor's master control borad.