CN205862049U - Display panels - Google Patents
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- CN205862049U CN205862049U CN201620731291.6U CN201620731291U CN205862049U CN 205862049 U CN205862049 U CN 205862049U CN 201620731291 U CN201620731291 U CN 201620731291U CN 205862049 U CN205862049 U CN 205862049U
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- black matrix
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Abstract
This application discloses a kind of display panels, including: the color membrane substrates that array base palte and described array base palte are oppositely arranged, the interval body array being formed between array base palte and color membrane substrates, the black matrix" that is formed on color membrane substrates, black matrix" includes multiple black matrix" row；Wherein: each interval body includes the bottom surface contacted with array base palte, and bottom surface has the first width a；First width a is the bottom surface Breadth Maximum along the direction being parallel to black matrix" row；Be formed on the insulating barrier between public electrode and thin film transistor (TFT) array offer multiple with array base palte on pixel electrode through hole one to one；Wherein, the first width a of interval body meets with the Breadth Maximum b of the through hole along the direction being parallel to black matrix" row: a ＞ b.By arranging interval body bottom surface the first width width more than through hole, when LCDs is by ambient pressure effect, interval body difficultly slips off in through hole, improves extruding colour cast and box thickness abnormal phenomena.
Description
Technical field
The disclosure relates generally to Display Technique field, particularly relates to a kind of display panels.
Background technology
Display panels generally includes array base palte, color membrane substrates and is formed at liquid crystal layer therebetween.Generally may be used
To arrange interval body array between array base palte and color membrane substrates, interval body array includes multiple interval body, in order to support battle array
Row substrate and color membrane substrates, improve the uniformity of display floater integral thickness.Array base palte and color film at display panels
After substrate para-position laminating, the bottom surface of interval body can contact with array base palte.
In existing technology, color membrane substrates is formed with colored filter, in order to split the black square of colored filter
Battle array and multiple interval body.Black matrix", by segmentation colored filter, can form multiple array arrangement on color membrane substrates
Pixel cell.Wherein, pixel cell can include red pixel cell, blue pixel cells and green pixel cell.
Additionally, the dark-state light leak caused in order to avoid display panels orientation is bad, interval body the most not with green picture
Element unit is adjacent.
But, along with improving constantly of display floater resolution, the width of the black matrix" between adjacent pixel unit is more
Come the narrowest.Such as, when resolution more than 400PPI (Pixel per Inch, per inch pixel count) time, the width of black matrix"
It is about 4～5 μm.And in order to ensure that display panels is not damaged by when being extruded by external force and box thickness is the most homogeneous, interval
The quantity of body is the most more.So, in high PPI display panels, at interval body orientation bad cause dark
The position of state light leak is the most more.
On the other hand, owing to, in high PPI display panels, the narrower width of black matrix", due to positivity liquid crystal
The bad dark-state light leak caused of orientation will be distributed in pixel cell more, cause display floater dark-state to brighten.
Additionally, in high PPI display panels, due to the narrower width of black matrix", the quantity of interval body is the most more,
Interval body position shared by between color membrane substrates and array base palte is limited, when display panels is by ambient pressure effect
Time interval body free end can easily be slipped on array base palte in the through hole of insulating barrier, cause extruding colour cast or box thickness be abnormal.
As it is shown in figure 1, be in existing display panels, interval body insulating barrier through hole between pixel electrode and public electrode
Between schematic relative position relation figure.Wherein, reference 101 is the bottom surface of the interval body contacted with array base palte, attached
Figure labelling 102 is the insulating barrier through hole on array base palte between public electrode and thin film transistor (TFT).Reference 103 is black
The orthographic projection on array base palte of the line direction of colour moment battle array, reference 104 is that the column direction of black matrix" is on array base palte
Orthographic projection, reference 105 is a sub-pixel unit.It can be seen that along the line direction of black matrix", be positioned at two
The width a1 of the interval body 101 between individual through hole narrows along with narrowing of black matrix" column width.When spacer width in figure
When a1 is less than the width b of through hole 102 in figure, when display panels is by ambient pressure effect, the easy landing of interval body 101
On array base palte in the through hole 102 of insulating barrier, thus cause the box thickness extruding colour cast or display panels abnormal.
Utility model content
In view of drawbacks described above of the prior art or deficiency, it is desirable to provide a kind of display panels, existing to solving
Technical problem present in technology.
First aspect, the embodiment of the present application provides a kind of display panels, and array base palte is relative with array base palte to be set
The color membrane substrates put, the interval body array being formed between array base palte and color membrane substrates, the black that is formed on color membrane substrates
Matrix；Wherein: black matrix" includes multiple black matrix" row and the black matrix" row intersected with each black matrix" row；Interval body
Array includes multiple interval body, and black matrix" covers the orthographic projection to black matrix" of each interval body；Each interval body includes and array
The bottom surface of substrate contact, and bottom surface has the first width a, wherein, the first width a is that bottom surface is along the side being parallel to black matrix" row
To Breadth Maximum；Array base palte includes thin film transistor (TFT) array, the pixel electrode array being formed at the first conductor layer, is formed at
The public electrode of the second conductor layer and the insulating barrier being formed between public electrode and thin film transistor (TFT) array；Open on insulating barrier
It is provided with multiple and pixel electrode through hole one to one, so that each pixel electrode is electric with the first electrode of each thin film transistor (TFT) respectively
Connect；First width a of interval body meets along the Breadth Maximum b in the direction being parallel to black matrix" row with through hole: a ＞ b.
According to the scheme of the embodiment of the present application, by arranging the bottom width of the interval body in the direction along black matrix" row
During more than the width of through hole so that display panels is by ambient pressure effect, interval body will not fall in via, keeps away
Extruding colour cast and the box thickness of having exempted from display panels are abnormal.
Additionally, in certain embodiments, it is shaped such that spacer is along black matrix" row side by arranging spacer bottom surface
To the first width more than any two vias adjacent along black matrix" line direction between distance, thus decrease spacer institute
The dark-state light leakage phenomena caused because orientation is bad in position, promotes the dark-state display effect of display panels.
Accompanying drawing explanation
By the detailed description that non-limiting example is made made with reference to the following drawings of reading, other of the application
Feature, purpose and advantage will become more apparent upon:
Fig. 1 shows in existing display panels, interval body and between public electrode and thin film transistor (TFT)
Relative position relation schematic diagram between insulating barrier through hole；
Fig. 2 shows the schematic diagram of an interval body of the application；
Fig. 3 shows in the display panels of the application, interval body and between public electrode and thin film transistor (TFT)
Insulating barrier through hole between relative position relation schematic diagram；
Fig. 4 shows in the display panels of the application, two through holes that interval body is adjacent with at black matrix" line direction
Between relative position relation schematic diagram；
Fig. 5 shows in the display panels of the application, the black matrix" that is positioned on color membrane substrates, colored filter with
And the schematic diagram of the relative position relation between spacer array；
Fig. 6 shows the first interval body and the first display pixel and the two black array edges adjacent with the first display pixel
The position relationship schematic diagram of the width of black matrix" line direction；
Fig. 7 shows thin film transistor (TFT), pixel electrode, common electrical in the array base palte in the display panels of the application
Relative position relation schematic diagram between pole and the insulating barrier through hole between public electrode and thin film transistor (TFT)；
Fig. 8 A～Fig. 8 F shows the schematic diagram of the bottom shape of the spacer of the application.
Detailed description of the invention
With embodiment, the application is described in further detail below in conjunction with the accompanying drawings.It is understood that this place is retouched
The specific embodiment stated is used only for explaining related application, rather than the restriction to this application.It also should be noted that, for
It is easy to describe, accompanying drawing illustrate only the part relevant to the application.
It should be noted that in the case of not conflicting, the embodiment in the application and the feature in embodiment can phases
Combination mutually.Describe the application below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
The display panels of the application, the color membrane substrates being oppositely arranged including array base palte and array base palte, is formed at
Interval body array between array base palte and color membrane substrates and the black matrix" being formed on color membrane substrates.Wherein, interval body
Array includes multiple interval body, and each interval body has the bottom surface contacted with array base palte, as in figure 2 it is shown, be the application
The schematic diagram of an interval body 200, wherein, interval body 200 includes bottom surface 201 and the top parallel with bottom surface 201
Face 202, the bottom surface 201 of each interval body has the first width a, and the first width a is along the line direction of black matrix".
Black matrix" includes multiple black matrix" row and the black matrix" row intersected with black matrix" row, and black matrix" covers
Each spacer is entirely located on black matrix" to the orthographic projection of black matrix" to the orthographic projection of black matrix", the most each spacer.
Array base palte includes thin film transistor (TFT) array, is formed at the pixel electrode array of the first conductor layer, pixel electrode battle array
Each pixel electrode in row lays respectively in each display pixel.Array base palte also includes the public electrode being formed at the second conductor layer
And the insulating barrier being formed between thin film transistor (TFT) array and public electrode.Multiple and pixel electrode one is offered on insulating barrier
The through hole of one correspondence, so that each pixel electrode can be corresponding with the thin film transistor (TFT) in thin film transistor (TFT) array even by through hole
Connect.
Shown in Figure 3, in the display panels of the application, interval body be positioned at thin film transistor (TFT) and public electrode
Between the schematic diagram of an embodiment of position relationship of insulating barrier through hole.
As it is shown on figure 3, in the present embodiment, reference 301 is the bottom surface of the interval body contacted with array base palte, accompanying drawing
Labelling 302 is the insulating barrier through hole on array base palte between thin film transistor (TFT) and public electrode, and reference 303 is black
The orthographic projection on array base palte of the line direction of matrix, reference 304 is that the column direction of black matrix" is on array base palte
Orthographic projection, reference 305 is a sub-pixel unit.
Here, unlike the prior art shown in Fig. 1, the first width a and through hole of the bottom surface 301 of interval body
302 is satisfied along the Breadth Maximum b in the direction being parallel to black matrix" row: a ＞ b.
So, due to a ＞ b, during so that display panels is by ambient pressure effect, interval body will not fall
Enter in through hole 302, it is to avoid the extruding colour cast of display panels and box thickness are abnormal.
Alternatively, it is positioned at along black square when the orthographic projection of interval body insulating barrier on array base palte is at least part of
Time between two through holes that battle array line direction is adjacent, the first width a of interval body is parallel to adjacent the appointing of black matrix" line direction with edge
Distance c between two through holes of anticipating meets: a ＞ c.
Here, it is along black matrix" row along distance c between adjacent any two vias in the direction of black matrix" row
Distance between the geometric center of any two vias that direction is adjacent.
As shown in Figure 4, the relative position relation signal between two through holes that interval body is adjacent with at black matrix" line direction
Figure.Through hole 401 is adjacent along black matrix" line direction with through hole 402, and its geometric center is respectively L and L ', and geometric center L and
Geometric center L ' between distance be c.O is the geometric center of interval body 403, and O point be positioned at through hole 401 and through hole 402 it
Between.Bottom surface first width of interval body 403 is a, and a ＞ c.
Due to a ＞ c, when display panels is extruded by external force, interval body 403 is difficult to clamp-on in any one via,
And then make the box that display panels remains to when being extruded by external force keep relative stability thick, and then ensure good display effect
Really.
Fig. 5 shows in the display panels of the present embodiment, the black matrix" that is formed on color membrane substrates, colorized optical filtering
Relative position relation between sheet and spacer.
As it is shown in figure 5, each black matrix" row 501 and each black matrix" row 502 separate colored filter to form multiple battle arrays
The display pixel 503 of row arrangement.
Here, it should be noted that the display panels of the present embodiment can comprise and multiple to have different colours
Colored filter.So, when deflection under liquid crystal molecule is at electric field action, the light through each display pixel 503 can be in
Existing different color.
Additionally, as it is shown in figure 5, interval body array includes that the first interval body 504, the first interval body 504 are formed at display picture
On black matrix" row 501 adjacent with display pixel 503 in pixel array.So, each interval body contacts with color membrane substrates
Position is respectively positioned in black matrix, is not at showing in pixel 503 region, and that can weaken that transmitance in each display pixel produces is negative
Face rings.
Alternatively, in the display panels of the present embodiment, the bottom surface of the first interval body 504 can be zhou duicheng tuxing,
And a wherein axis of symmetry (the i.e. first axis of symmetry) of bottom surface is parallel to the direction that black matrix" arranges.
First interval body covers a through hole to the orthographic projection of the insulating barrier between public electrode and thin film transistor (TFT) array,
And this through hole is symmetrical about the first axis of symmetry.In other words, when the first interval body landing is on through hole, the first interval body edge
The width being parallel to black matrix" line direction is more than this through hole width along black matrix" line direction, and the bottom surface of the first interval body
With this through hole, there is same axis of symmetry.
Meanwhile, the first width a and the 3rd width d of the first interval body meets: a ＜ d, simultaneously d=d1+d2+d3, wherein d1
Being the first display pixel width along black matrix" line direction, d2 and d3 is respectively the two black squares adjacent with the first display pixel
Array is along the width of black matrix" line direction.
As shown in Figure 6, Fig. 6 shows the first interval body and the first display pixel and adjacent with the first display pixel two
Black array is along the position relationship of the width of black matrix" line direction.The bottom surface of the first interval body 601 is positioned at and the first display picture
Between element 602 two adjacent black array 603,604, and bottom surface the first width a of the first interval body 601 is less than the first display
Pixel 602 and with the first display adjacent two black array 603,604 of pixel along width sum d of black matrix" line direction.
The width a in the direction that the first interval body 601 extends along black matrix" row not over first display pixel 602 and
Two adjacent black array 603,604 are along width sum d of black matrix" line direction.So, when liquid crystal panel is by outward
During boundary's extruding, it is possible to ensure on the premise of the first interval body is not fall off in through hole so that the first interval body is on through hole
Uniform force, it is to avoid cause that orientation is bad causes box thickness abnormal, can also avoid the bottom surface first due to the first interval body simultaneously
Width is wide to have a negative impact to the light transmittance in the two display pixels adjacent with the first display pixel.
In some optional implementations, the bottom surface of interval body also has the second width e, and wherein the second width is bottom surface
Along the width in the direction being parallel to black matrix" row, meet a ＞ e simultaneously.So can be along black square due to interval body bottom surface
The direction of battle array row extends, even if in the case of high PPI display panels has narrower black matrix" row, it is also possible to make
Interval body bottom surface has bigger area and more firmly can be supported display panels.
As it is shown in fig. 7, be in the display panels of the application, the pixel electrode 701 that is positioned on array base palte, common electrical
Pole 702, thin film transistor (TFT) 703 and the relative position of the insulating barrier 704 between public electrode 701, thin film transistor (TFT) 703
Relation schematic diagram.
Array base palte include thin film transistor (TFT) 703, be positioned at the pixel electrode 701 of each display pixel, public electrode 702 with
And the insulating barrier 704 between public electrode 701, thin film transistor (TFT) 703.Thin film transistor (TFT) 703 includes being formed at the first gold medal
The grid 705 belonging to layer and the source electrode 707 being formed at the second metal level, drain electrode 706.Additionally, array base palte also includes a plurality of sweeping
Retouch line and the data wire intersected with multi-strip scanning line.Scan line such as can set with layer with the grid 705 of thin film transistor (TFT) 703
Put, and data wire can be arranged with layer with the source electrode 707 of thin film transistor (TFT) 703 and drain electrode 706.
The grid 705 of thin film transistor (TFT) 703 is connected with scan line, and the drain electrode 706 of thin film transistor (TFT) 703 is with data wire even
Connect.When the scanning signal of scan line makes thin film transistor (TFT) 703 open, the source electrode 707 of thin film transistor (TFT) 703, drain electrode 706 are even
Logical, thus by the data signal transmission that applies on data wire to pixel electrode 701.So, array base palte and color film it are positioned at
Phase under the electric field action that the liquid crystal molecule in liquid crystal layer between substrate is formed between pixel electrode 701 and public electrode 702
Should deflect on ground, thus show predetermined picture.
See shown in Fig. 8 A～Fig. 8 F, for the schematic diagram of bottom shape of the spacer of the application.It should be noted that figure
Illustrate to 8A～Fig. 8 being only intended to illustrate property of F the end of spacer in the display panels that can be used for realizing the application
The bottom shape of the spacer in face shape, rather than the display panels of restriction the application.
Such as, as shown in Figure 8 A, in the display panels of the present embodiment, interval body array can include that bottom surface is first
The interval body of round rectangle 810, and the long limit of the first round rectangle 810 can be parallel to the direction of black matrix" row.
Or, as shown in Figure 8 B, interval body array includes the interval that bottom surface is spliced by two isosceles triangles 821 and 822
Body 820；Two isosceles triangle 821 and 822 congruences, the drift angle of two isosceles triangles 821 and 822 overlaps and two isosceles three
Dihedral 821 and 822 is about same second axis of symmetry axial symmetry；Wherein, the second axis of symmetry is parallel to described black matrix" row
Direction.
Or, in the display panels of the present embodiment, spacer array can also include that bottom surface is by second fillet
The interval body that rectangle and at least one the 3rd round rectangle are spliced to form, and the long limit of the second round rectangle is parallel to black matrix"
The direction of row.As shown in Fig. 8 C-8F.
Wherein, Fig. 8 C schematically shows and is spliced by second round rectangle 831 and the 3rd round rectangle 832
The interval body 830 formed, wherein the second round rectangle 831 and the 3rd round rectangle 832 are congruent, its of the second round rectangle 831
In one article of long limit overlap with wherein one article of long limit of the 3rd round rectangle 832.
Fig. 8 D schematically shows by second round rectangle 841 and two the 3rd round rectangle 842,843 splicings
The interval body 840 formed, wherein, the direction of the long edge black matrix" row of the second round rectangle 842,843 extends, the 3rd fillet
Wherein long limit of rectangle 842,843 two minor faces with the second round rectangle 841 respectively partially overlap respectively.
Fig. 8 E schematically shows by second round rectangle 851 and two the 3rd round rectangle 852,853 splicings
The interval body 850 formed, wherein, the direction of the long edge black matrix" row of the 3rd round rectangle 852,853 extends, the 3rd fillet
Wherein long limit of rectangle 852,853 two minor faces with the second round rectangle 851 respectively partially overlap respectively.
Fig. 8 F schematically shows and is spliced to form by second round rectangle 861 and the 3rd round rectangle 862
Interval body 860, wherein, the direction of the long edge black matrix" row of the 3rd round rectangle 862 extends, the 3rd round rectangle 862
Two long limits divide with two long legs of the second round rectangle 861 and overlap.
In addition it should be noted that in the display panels of the application, the bottom surface of spacer and the end face of spacer can
To be of similar shape, so that spacer is in manufacturing process, can etch only with the mask plate of a kind of pattern
Make.
Additionally, the display panels of the application also includes both alignment layers and liquid crystal layer.Liquid crystal layer be formed at array base palte and
Between color membrane substrates, and liquid crystal layer includes negative liquid crystal.The alignment direction of both alignment layers is parallel to the direction of black matrix" row.
So, in process of alignment, the orientation not good general caused due to the occupy-place of spacer fully falls into black
In row matrix, without entering in pixel region, thus avoid the bad dark-state light leakage phenomena caused of orientation.Further,
Spacer can be arranged on black matrix" row adjacent with random color pixel region in display panels, and without avoiding
There is the pixel region of maximum brightness.
It will be appreciated by those skilled in the art that technical scheme scope involved in the application, however it is not limited to above-mentioned technology
The technical scheme of the particular combination of feature, also should contain in the case of conceiving without departing from described technical scheme simultaneously, by
Other technical scheme that above-mentioned technical characteristic or its equivalent feature carry out combination in any and formed.Such as features described above and the application
Disclosed in (but not limited to) there is the technical characteristic of similar functions replace mutually and the technical scheme that formed.
Claims (10)
1. a display panels, it is characterised in that including: the color film that array base palte and described array base palte are oppositely arranged
Substrate, the interval body array being formed between described array base palte and described color membrane substrates and be formed on described color membrane substrates
Black matrix"；
Wherein:
Described black matrix" includes multiple black matrix" row and the black matrix" row intersected with each described black matrix" row；
Described interval body array includes multiple interval body, and described black matrix" covers each described interval body to described black matrix"
Orthographic projection；
Each described interval body includes the bottom surface contacted with described array base palte, and described bottom surface has the first width a, wherein, institute
Stating the first width a is the described bottom surface Breadth Maximum along the direction being parallel to described black matrix" row；
Described array base palte includes thin film transistor (TFT) array, the pixel electrode array being formed at the first conductor layer, is formed at second
The public electrode of conductor layer and be formed at the insulating barrier between described public electrode and described thin film transistor (TFT) array；
Multiple and described pixel electrode through hole one to one is offered, so that each described pixel electrode is respectively on described insulating barrier
Electrically connect with the first electrode of each described thin film transistor (TFT)；
The described first width a of described interval body is parallel to the Breadth Maximum in the direction of described black matrix" row with described through hole edge
B meets:
A ＞ b.
Display panels the most according to claim 1, it is characterised in that:
Described interval body to the orthographic projection of described insulating barrier be at least partially situated at along described black matrix" line direction adjacent two
Between described through hole, and distance c between through hole described in described adjacent with along described black matrix" line direction for first width a two
Meet:
A ＞ c.
Display panels the most according to claim 1, it is characterised in that:
Described color membrane substrates includes colored filter, and described black matrix" separates described colored filter and forms display pixel battle array
Row；
Described interval body array includes that the first interval body, described first interval body are formed at and in described display pel array
On the described black matrix" row that one display pixel is adjacent, the bottom surface of described first interval body is zhou duicheng tuxing, and has parallel
The first axis of symmetry in described black matrix" column direction；
Described first interval body covers a through hole to the orthographic projection of described insulating barrier, and this through hole is about described first axis of symmetry
Axial symmetry；
First width a of described first interval body and the 3rd width d meets:
A ＜ d；
Wherein, d=d1+d2+d3, d1 are the described first display pixel width maximum along described black matrix" line direction, d2
It is respectively two black matrix"s adjacent with described first display pixel with d3 and arranges the width along described black matrix" line direction.
4. according to the display panels described in claim 1-3 any one, it is characterised in that:
The bottom surface of described interval body also has the second width e, and described second width is that described bottom surface is along being parallel to described black square
The width maximum in the direction of array；
And meet:
A ＞ e.
Display panels the most according to claim 4, it is characterised in that:
Described interval body array includes the interval body that described bottom surface is the first round rectangle；
Wherein, the long limit of described first round rectangle is parallel to the direction of described black matrix" row.
Display panels the most according to claim 4, it is characterised in that:
Described interval body array includes that described bottom surface is for by second round rectangle and at least one the 3rd round rectangle splicing
The interval body formed, wherein, the long limit of described second round rectangle is parallel to the direction of described black matrix" row.
Display panels the most according to claim 6, it is characterised in that:
Described second round rectangle and described 3rd round rectangle congruence, and a wherein long limit of described second round rectangle
Overlap with wherein one article of long limit of described 3rd round rectangle.
Display panels the most according to claim 6, it is characterised in that:
Described in the long edge of described 3rd round rectangle, the direction of black matrix" row extends, and at least one described 3rd fillet square
A wherein long limit of shape overlaps at least in part with a wherein minor face of described second round rectangle.
Display panels the most according to claim 4, it is characterised in that:
Described interval body array includes the interval body that described bottom surface is spliced by two isosceles triangles；
Said two isosceles triangle congruence, the drift angle of said two isosceles triangle is overlapping and said two isosceles triangle closes
In same second axis of symmetry axial symmetry；
Wherein, described second axis of symmetry is parallel to the direction of described black matrix" row.
10. according to the display panels described in claim 1-3 any one, it is characterised in that:
Described display panels also includes being formed at the liquid crystal layer between described array base palte and described color membrane substrates and shape
Both alignment layers on color membrane substrates described in Cheng Yu；
Wherein, described liquid crystal layer includes that negative liquid crystal, the alignment direction of described both alignment layers are parallel to the side of described black matrix" row
To.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620731291.6U CN205862049U (en) | 2016-07-12 | 2016-07-12 | Display panels |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620731291.6U CN205862049U (en) | 2016-07-12 | 2016-07-12 | Display panels |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106681059A (en) * | 2017-02-09 | 2017-05-17 | 厦门天马微电子有限公司 | Liquid crystal display device |
| CN113946073A (en) * | 2020-06-30 | 2022-01-18 | 京东方科技集团股份有限公司 | Display device and manufacturing method thereof |
| WO2022193684A1 (en) * | 2021-03-19 | 2022-09-22 | 京东方科技集团股份有限公司 | Liquid crystal display panel and display apparatus |
-
2016
- 2016-07-12 CN CN201620731291.6U patent/CN205862049U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106681059A (en) * | 2017-02-09 | 2017-05-17 | 厦门天马微电子有限公司 | Liquid crystal display device |
| CN106681059B (en) * | 2017-02-09 | 2019-09-24 | 厦门天马微电子有限公司 | A kind of liquid crystal display device |
| CN113946073A (en) * | 2020-06-30 | 2022-01-18 | 京东方科技集团股份有限公司 | Display device and manufacturing method thereof |
| WO2022193684A1 (en) * | 2021-03-19 | 2022-09-22 | 京东方科技集团股份有限公司 | Liquid crystal display panel and display apparatus |
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