CN205842784U - A kind of multi core chip and comprise the microwave oven of this multi core chip - Google Patents
A kind of multi core chip and comprise the microwave oven of this multi core chip Download PDFInfo
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- CN205842784U CN205842784U CN201620835713.4U CN201620835713U CN205842784U CN 205842784 U CN205842784 U CN 205842784U CN 201620835713 U CN201620835713 U CN 201620835713U CN 205842784 U CN205842784 U CN 205842784U
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Abstract
This utility model relates to household appliance technical field, discloses a kind of multi core chip and the microwave oven comprising this multi core chip, and this multi core chip comprises: the first kernel, is used for running high-speed cruising program；And second kernel, it is used for running low cruise program.Pass through technique scheme, the program module of low cruise and the program module of high-speed cruising are separated, the program needing high-speed cruising is made to be in the state of high-speed cruising in the first kernel all the time, the program being limited low cruise by interface is individually placed in the second kernel operation, thus can promote software program operational reliability in multi core chip and efficiency.
Description
Technical field
This utility model relates to household appliance technical field, in particular it relates to a kind of multi core chip and comprise this multi core chip
Microwave oven.
Background technology
Microwave oven is to utilize food to absorb microwave energy in microwave field and make the cooking apparatus of conducting self-heating.At microwave oven
The microwave that microwave generator produces sets up microwave electric field at microwave cavity, and takes certain measure to make this microwave electric field exist
Furnace chamber is uniformly distributed as far as possible, food is put in this microwave electric field, control centre control its cooking time and microwave electric field
Intensity, carries out various cooking process.
Existing microwave oven controls many employing mechanical types and controls to control with electronic type.For mechanical type control, its
Being the power to microwave oven and the time is controlled, not comprising relevant control algolithm of cooking, control mode is more comparatively speaking
Single, it is increasingly difficult to meet the demand of microwave oven intelligentized control method.For electronic type control, it is simple that it is substantially employing
8 or 32 8-digit microcontrollers as control core.It is all of that microcontroller runs software algorithm and control external circuit etc.
Thing.
The utility model people of the application finds, operationally, internal software algorithm is in height to the chip of microcontroller
Speed is run, and the processing speed of some interfaces of chip is affected by the restriction of ardware feature, is in low cruise.In single
The chip of core can only process something in the same time, accordingly, it would be desirable to the in house software algorithm of high-speed cruising and low cruise
Interface Controller be conflicting, so using the chip control system of monokaryon, it is impossible to realize semiconductor microwave system
Good effect.
Utility model content
The purpose of this utility model is to provide a kind of multi core chip and the microwave oven comprising this multi core chip, and it can improve micro-
The data processing speed of controller and efficiency.
To achieve these goals, this utility model provides a kind of multi core chip, and this multi core chip comprises: the first kernel,
For running high-speed cruising program；And second kernel, it is used for running low cruise program.
Wherein, described low cruise program can be to process the interface routine of external circuit.
Wherein, described multi core chip also can comprise data sharing district, the high-speed cruising program in described first kernel and institute
The low cruise program stated in the second kernel carries out data interaction by this data sharing district.
Wherein, this multi core chip can be used for performing the control relevant to microwave oven.
Wherein, described first kernel can perform one or more in following operation: properties of foods analysis, calculating, logic
Control and analysis.
Wherein, described second kernel can perform one or more in operating: pin controls, external data communication with
And data acquisition.
Wherein, described second kernel read described microwave oven correlation acquisition data, and by these collection data deposit to
Data sharing district；Described first kernel reads described collection data from described data sharing district, and performs spy according to these data
Property analyze, calculate and/or contrast judgement, the corresponding information that controls of output afterwards is to described data sharing district；And described second
Kernel reads described control information from described data sharing district, and by chip pin output corresponding control signal to external electrical
Road.
Wherein, described collection data can comprise following one or more: load temperature, cavity humidity, load weight and
Output.
Wherein, described control information can comprise following one or more: frequency, phase place and power.
Accordingly, this utility model also provides for a kind of microwave oven, and this microwave oven comprises above-mentioned multi core chip.
By technique scheme, the program module of low cruise and the program module of high-speed cruising are separated, makes needs
The program of high-speed cruising is in the state of high-speed cruising in the first kernel all the time, and the program being limited low cruise by interface is independent
It is placed in the second kernel operation, thus software program operational reliability in multi core chip and efficiency can be promoted.
Other features and advantages of the utility model will be described in detail in detailed description of the invention part subsequently.
Accompanying drawing explanation
Accompanying drawing is used to offer and is further appreciated by of the present utility model, and constitutes a part for description, with following
Detailed description of the invention be used for explaining this utility model together, but be not intended that restriction of the present utility model.In the accompanying drawings:
The structural representation of the multi core chip that Fig. 1 provides for this utility model one embodiment；
The structural representation of the multi core chip that Fig. 2 provides for another embodiment of this utility model；And
The operational flow diagram of the multi core chip that Fig. 3 provides for another embodiment of this utility model.
Description of reference numerals
10 first kernel 20 second kernels
30 data sharing district 100 MCU
40 external interfaces
Detailed description of the invention
Below in conjunction with accompanying drawing, detailed description of the invention of the present utility model is described in detail.It should be appreciated that herein
Described detailed description of the invention is merely to illustrate and explains this utility model, is not limited to this utility model.
The structural representation of the multi core chip that Fig. 1 provides for this utility model one embodiment.As it is shown in figure 1, this practicality is new
Type provides a kind of multi core chip, and this multi core chip can be embodied as the process chip in microcontroller 100, this multi core chip
Comprise: the first kernel 10, be used for running high-speed cruising program；And second kernel 20, it is used for running low cruise program.Mat
This, by by the program module of the program module of low cruise and high-speed cruising separately, make the program needing high-speed cruising the
One kernel is in the state of high-speed cruising all the time, and the program of low cruise is individually placed in the second kernel operation, thus can
Promote software program operational reliability in multi core chip and efficiency.Certainly, although in the present embodiment only gives first
Core 10 and the second kernel 20 the two kernel, but this utility model is not limited to this, it is also possible to set according to program operating rate
Put greater number of kernel, so that each kernel runs the program of corresponding operating rate, thus promote operational efficiency.
It is said that in general, the operating rate of chip is quickly, and the speed of its peripheral interface is the fortune relatively lower than chip
Scanning frequency rate, this peripheral interface can for example, serial port RS232C, parallel port etc., chip is through these peripheral interfaces
Communicate with ancillary equipment, such as, can receive the data from ancillary equipment, or the information that will control accordingly is through outside described
Closed structure and send to ancillary equipment, perform to control operation accordingly controlling this ancillary equipment.Institute in above-mentioned second kernel 20
The low cruise program run can be to process the interface routine of external circuit, and the high speed fortune run in above-mentioned first kernel 10
Line program can be then that software algorithm etc. performs the program that speed is not limited by peripheral interface speed.
The structural representation of the multi core chip that Fig. 2 provides for another embodiment of this utility model.With the embodiment shown in Fig. 1
Difference be, the multi core chip that another embodiment shown in this Fig. 2 is provided also comprises data sharing district 30, described
High-speed cruising program in one kernel 10 is entered by this data sharing district 30 with the low cruise program in described second kernel 20
Row data interaction.
Specifically, described data sharing district can be that random access memory, flash memory, cache memory etc. are various
For accessing the memorizer of data.The operation result of low cruise program can be stored in described data sharing district 30 by the second kernel 20
In, in order to the first kernel 10 reads operation result from this data sharing district.First kernel 10 can be according to the operation of the second kernel 20
Result and perform to calculate accordingly, and export the corresponding information that controls to described data sharing district 30, in order to the second kernel is from this
Data sharing district 30 reads control information, and controls signal to ancillary equipment accordingly through external interface output.Thereby, can shape
Become a closed loop procedure so that a certain program of high-speed cruising information (that is, the second kernel needed for it runs in the first kernel 10
The operation result of 20) the most complete time, other computings can be performed, and after information needed for described program is run is complete, fortune
This program of row, thus promote operational efficiency.It addition, in the setting in data sharing district can be the first kernel 10 and the second kernel 20
Program traffic control provides the biggest motility, and can promote the effect that the program in the first kernel 10 and the second kernel 20 is run
Rate.
The operational flow diagram of the multi core chip that Fig. 3 provides for another embodiment of this utility model.Come below in conjunction with Fig. 3 with micro-
Operation stream to multi core chip of the present utility model as a example by the implementation environment of the multi core chip that ripple stove provides as this utility model
Journey is introduced.
Step S10, described second kernel 20 reads the correlation acquisition data of described microwave oven, and these collection data is deposited
Put to data sharing district.These data can comprise the load temperature in microwave oven quasiconductor heating system, cavity humidity, load weight
Collection data, after it is processed by described second kernel 20, are placed on data sharing district 30 by the related datas such as amount, output.
Step S20, described first kernel 10 reads described collection data from described data sharing district 30, and according to these numbers
According to performing specificity analysis, calculating and/or contrast judgement, the corresponding information that controls of output afterwards is to described data sharing district 30.Institute
State that the first kernel 10 can perform in following operation for described collection data one or more: properties of foods analysis, calculate, patrol
Volume control and analysis, the corresponding control information exported can be following one or more: frequency, phase place and power.
Thereby, first the first kernel 10 can read the collection data in data sharing district 30, understands the current state of microwave oven, load
Heats, then carry out specificity analysis, calculate, contrast judgement etc., finally according to the control logic preset in software,
The control information such as corresponding frequency, phase place, power that export are to data sharing district 30.
Step S30, described second kernel 20 reads described control information from described data sharing district 30, and by chip pipe
What foot output was corresponding controls signal to external circuit, in order to be controlled external circuit, and then the heating process to microwave oven
It is controlled.
Through the flow process shown in Fig. 3, use the chip control core as semiconductor microwave system of this utility model offer
The heart, by the characteristic of food, analyze, calculate, program that logic control, the simple software algorithm such as analysis are run is placed in one
Core runs, pin control, external data communication, data acquisition etc. are placed in another kernel fortune by the program of hardware limitation
OK, and in public territory one data shared region is set.Each kernel is placed on shared region by needing the data shared, in order to other
Kernel can quickly read.Thereby, can make microwave oven control software can more quickly analyze, real-time control, change
The heats of kind microwave oven.
Accordingly, this utility model also provides for a kind of microwave oven, and this microwave oven comprises above-mentioned multi core chip.Certainly, this reality
Being not limited to this with novel, other can use the household electrical appliance of above-mentioned multi core chip to be also feasible, such as flue gas kitchen range, ice
Case, washing machine, air-conditioning, electric fan etc..
Preferred implementation of the present utility model is described in detail above in association with accompanying drawing, but, this utility model does not limit
Detail in above-mentioned embodiment, in technology concept of the present utility model, can be to skill of the present utility model
Art scheme carries out multiple simple variant, and these simple variant belong to protection domain of the present utility model.
It is further to note that each the concrete technical characteristic described in above-mentioned detailed description of the invention, at not lance
In the case of shield, can be combined by any suitable means.In order to avoid unnecessary repetition, this utility model is to respectively
Plant possible compound mode to illustrate the most separately.
Additionally, combination in any can also be carried out, as long as it is not disobeyed between various different embodiment of the present utility model
Carrying on the back thought of the present utility model, it should be considered as content disclosed in the utility model equally.
Claims (10)
1. a multi core chip, it is characterised in that this multi core chip comprises:
First kernel, is used for running high-speed cruising program；And
Second kernel, is used for running low cruise program.
Multi core chip the most according to claim 1, it is characterised in that described low cruise program is to process external circuit
Interface routine.
Multi core chip the most according to claim 1, it is characterised in that described multi core chip also comprises data sharing district, institute
The high-speed cruising program stated in the first kernel is carried out by this data sharing district with the low cruise program in described second kernel
Data interaction.
4. according to the multi core chip described in claim any one of claim 1-3, it is characterised in that this multi core chip is used for
Perform the control relevant to microwave oven.
Multi core chip the most according to claim 4, it is characterised in that described first kernel performs the one in following operation
Or many persons: properties of foods analysis, calculating, logic control and analysis.
Multi core chip the most according to claim 4, it is characterised in that described second kernel performs the one in operating
Or many persons: pin controls, external data communication and data acquisition.
Multi core chip the most according to claim 4, it is characterised in that
Described second kernel reads the correlation acquisition data of described microwave oven, and deposits these collection data to data sharing
District；
Described first kernel from described data sharing district read described collection data, and according to these data perform specificity analysis,
Calculating and/or contrast judgement, the corresponding information that controls of output afterwards is to described data sharing district；And
Described second kernel reads described control information from described data sharing district, and by the control of chip pin output correspondence
Signal is to external circuit.
Multi core chip the most according to claim 7, it is characterised in that described collection packet containing following one or more:
Load temperature, cavity humidity, load weight and output.
Multi core chip the most according to claim 7, it is characterised in that described control information comprise following one or more:
Frequency, phase place and power.
10. a microwave oven, it is characterised in that this microwave oven comprises according to described in claim any one of claim 1-9
Multi core chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620835713.4U CN205842784U (en) | 2016-08-01 | 2016-08-01 | A kind of multi core chip and comprise the microwave oven of this multi core chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620835713.4U CN205842784U (en) | 2016-08-01 | 2016-08-01 | A kind of multi core chip and comprise the microwave oven of this multi core chip |
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| CN205842784U true CN205842784U (en) | 2016-12-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109557838A (en) * | 2017-09-27 | 2019-04-02 | 浙江苏泊尔家电制造有限公司 | Household appliance control method and device |
-
2016
- 2016-08-01 CN CN201620835713.4U patent/CN205842784U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109557838A (en) * | 2017-09-27 | 2019-04-02 | 浙江苏泊尔家电制造有限公司 | Household appliance control method and device |
| CN109557838B (en) * | 2017-09-27 | 2021-12-07 | 浙江苏泊尔家电制造有限公司 | Household appliance control method and device |
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